Search results for "Codesign"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Benoît Bossavit, Sarah Parsons	Outcomes for design and learning when teenagers with autism codesign a serious game: A pilot study.	J. Comput. Assist. Learn.	2018	DBLP DOI BibTeX RDF
16	Wei Chen 0047, Songbai Wang, Li Qiu 0001	A Majorization Condition for Multi-Input Networked Stabilization via Coding/Control Codesign.	SIAM J. Control. Optim.	2018	DBLP DOI BibTeX RDF
16	Qi Zhu 0002, Alberto L. Sangiovanni-Vincentelli	Codesign Methodologies and Tools for Cyber-Physical Systems.	Proc. IEEE	2018	DBLP DOI BibTeX RDF
16	Yuan-Xin Li 0001, Guang-Hong Yang	Observer-Based Fuzzy Adaptive Event-Triggered Control Codesign for a Class of Uncertain Nonlinear Systems.	IEEE Trans. Fuzzy Syst.	2018	DBLP DOI BibTeX RDF
16	Xichuan Zhou, Shengli Li 0007, Fang Tang, Shengdong Hu, Zhi Lin, Lei Zhang 0038	DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip.	IEEE Trans. Neural Networks Learn. Syst.	2018	DBLP DOI BibTeX RDF
16	Tony Nowatzki, Newsha Ardalani, Karthikeyan Sankaralingam, Jian Weng 0002	Hybrid optimization/heuristic instruction scheduling for programmable accelerator codesign.	PACT	2018	DBLP DOI BibTeX RDF
16	Guilherme C. Pereira, Maria Cecília Calani Baranauskas	Empowering Lesbian, Gay, Bisexual, and Transgender (LGBT) People with Codesign: A Critical Evaluation Through the Lens of Simplicity.	HCI (18)	2018	DBLP DOI BibTeX RDF
16	Stanislaw Deniziak, Robert Tomaszewski	Codesign of energy and resource efficient contention-free Network-on Chip for real-time embedded systems.	NoCArc@MICRO	2018	DBLP DOI BibTeX RDF
16	Monia Ettouil, Habib Smei, Abderrazak Jemai, Mohamed Ghazel	Codesign of an IoT Using a Metaheuristic IP.	IINTEC	2018	DBLP DOI BibTeX RDF
16	Polianna Paim, Soraia Silva Prietch, Anderson Duarte	CoDesign in the Exploratory Phase of an Assistive Technology product Design to support the Teaching-Learning Process of Brazilian-Portuguese Language for Visual Persons.	IHC	2018	DBLP DOI BibTeX RDF
16	Vincent T. Lee, Amrita Mazumdar, Carlo C. del Mundo, Armin Alaghi, Luis Ceze, Mark Oskin	Application Codesign of Near-Data Processing for Similarity Search.	IPDPS	2018	DBLP DOI BibTeX RDF
16	Florian Kastner, Benedikt Janßen, Frederik Kautz, Michael Hübner 0001, Giulio Corradi	Hardware/Software Codesign for Convolutional Neural Networks Exploiting Dynamic Partial Reconfiguration on PYNQ.	IPDPS Workshops	2018	DBLP DOI BibTeX RDF
16	Aviral Shrivastava, Sudeep Pasricha (eds.)	Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2018, part of ESWEEK 2018, Torino, Italy, September 30 - October 5, 2018	CODES+ISSS	2018	DBLP BibTeX RDF
16	Josep Balasch, Arthur Beckers, Dusan Bozilov, Sujoy Sinha Roy, Furkan Turan, Ingrid Verbauwhede	Teaching HW/SW codesign with a Zynq ARM/FPGA SoC.	EWME	2018	DBLP DOI BibTeX RDF
16	Christopher Kumar Anand, Lucas Dutton, Adele Olejarz, Robert F. Enenkel, Wolfram Kahl	Hardware/software codesign for mathematical function acceleration.	CASCON	2018	DBLP BibTeX RDF
16	Abdussalam Ali	Managing CoDesign in dynamic alliance networks		2018	RDF
16	Thomas Haywood Dadzie, Jihye Kim, Hyunok Oh	Secure non-volatile memory with scratch pad memory using dual encryption mode: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Selma Saidi, Sebastian Steinhorst, Arne Hamann, Dirk Ziegenbein, Marko Wolf	Future automotive systems design: research challenges and opportunities: special session.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Kang Yang, Rui Wang 0024, Yu Jiang 0001, Chenxia Luo, Yong Guan, Xiaojuan Li, Zhiping Shi 0002	Enhanced resilient sensor attack detection using fusion interval and measurement history.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Xuan Wang, Chao Wang 0003, Xuehai Zhou	WinoNN: optimising FPGA-based neural network accelerators using fast winograd algorithm (work-in-progress).	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Wei Jiang 0016, Liugen Xiu, Jinyu Zhan, Ke Jiang	Co-design of security-critical real-time systems to prevent fault injection attacks: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Markus Miettinen, Ahmad-Reza Sadeghi	Internet of things or threats?: on building trust in IoT (keynote).	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Manuele Rusci, Alessandro Capotondi, Francesco Conti 0001, Luca Benini	Quantized NNs as the definitive solution for inference on low-power ARM MCUs?: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Xue-Yang Zhu	Equivalence of transformations of synchronous data flow graphs: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Lihui Jin, Chao Wang 0003, Lei Gong, Chongchong Xu, Yahui Hu, Luchao Tan, Xuehai Zhou	Furion: alleviating overheads for deep learning framework on single machine (work-in-progress).	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Stefano Spellini, Michele Lora, Sudipta Chattopadhyay 0001, Franco Fummi	Introducing assume-guarantee contracts for verifying robotic applications: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Hongfei Wang, Jianwen Li, Kun He 0001, Wenjie Cai	Hierarchical ensemble learning for resource-aware FPGA computing: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Sena Hounsinou, Aishwarya Vasu, Harini Ramaprasad	Hardware implementation of a multi-mode-aware mixed-criticality scheduler: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Mengquan Li, Weichen Liu, Lei Yang 0018, Yiyuan Xie, Yaoyao Ye, Nan Guan	Communication optimization for thermal reliable optical network-on-chip: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Kai Neubauer, Christian Haubelt, Philipp Wanko, Torsten Schaub	On leveraging approximations for exact system-level design space exploration: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Taimour Wehbe, Vincent John Mooney, David C. Keezer	A chip-level security framework for assessing sensor data integrity: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Minjun Seo, Roman Lysecky	Runtime requirements monitoring for state-based hardware: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Jian Fang 0004, Jianyu Chen, Zaid Al-Ars, H. Peter Hofstee, Jan Hidders	A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Jan Henrik Weinstock, Robert Lajos Bücs, Florian Walbroel, Rainer Leupers, Gerd Ascheid	AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Jinyu Zhan, Junhuan Yang, Wei Jiang 0016, Yixin Li	Dynamic data management for automotive ECUs with hybrid RAM-NVM memory: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Yejia Di, Liang Shi, Congming Gao, Qiao Li 0001, Chun Jason Xue	Revisiting wear leveling design on compression applied 3D NAND flash memory: work-in-progress.	CODES+ISSS	2018	DBLP DOI BibTeX RDF
16	Soonhoi Ha, Jürgen Teich (eds.)	Handbook of Hardware/Software Codesign.		2017	DBLP DOI BibTeX RDF
16	Kaiyuan Guo, Song Han 0003, Song Yao, Yu Wang 0002, Yuan Xie 0001, Huazhong Yang	Software-Hardware Codesign for Efficient Neural Network Acceleration.	IEEE Micro	2017	DBLP DOI BibTeX RDF
16	Mehul Bhatt, James Cutting, Daniel Levin, Clayton Lewis	Cognition, Interaction, Design - Discussions as Part of the Codesign Roundtable 2017.	Künstliche Intell.	2017	DBLP DOI BibTeX RDF
16	Andrea Censi	Uncertainty in Monotone Codesign Problems.	IEEE Robotics Autom. Lett.	2017	DBLP DOI BibTeX RDF
16	Javier Olivito, Javier Resano, José Luis Briz	Accelerating Board Games Through Hardware/Software Codesign.	IEEE Trans. Comput. Intell. AI Games	2017	DBLP DOI BibTeX RDF
16	Jiang Wan, Arquimedes Canedo, Mohammad Abdullah Al Faruque	Cyber-Physical Codesign at the Functional Level for Multidomain Automotive Systems.	IEEE Syst. J.	2017	DBLP DOI BibTeX RDF
16	Nirmal Prajapati, Sanjay V. Rajopadhye, Hristo N. Djidjev, Nandakishore Santhi, Tobias Grosser, Rumen Andonov	Accelerator Codesign as Non-Linear Optimization.	CoRR	2017	DBLP BibTeX RDF
16	Hokchhay Tann, Soheil Hashemi, Iris Bahar, Sherief Reda	Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks.	CoRR	2017	DBLP BibTeX RDF
16	Paul E. Mendez-Monroy	Fuzzy codesign for networked control systems.	CCE	2017	DBLP DOI BibTeX RDF
16	Carlos Alberto Oliveira De Souza, Erinaldo Pereira, Eduardo Marques	A Hardware/Software Codesign for the Chemical Reactivity of BRAMS.	DSD	2017	DBLP DOI BibTeX RDF
16	Matthias Göbel 0001, Ahmed Elhossini, Ben H. H. Juurlink	A Methodology for Predicting Application-Specific Achievable Memory Bandwidth for HW/SW-Codesign.	DSD	2017	DBLP DOI BibTeX RDF
16	Ruoxi Jia 0001, Roy Dong, Shankar Sastry 0001, Costas J. Spanos	Optimal sensor-controller codesign for privacy in dynamical systems.	CDC	2017	DBLP DOI BibTeX RDF
16	Venkateshwarlu Y. Gudur, Amit Acharyya	Accelerated reconfigurable string matching using hardware-software codesign for computational bioinformatics applications.	ECCTD	2017	DBLP DOI BibTeX RDF
16	Luciana de Micco, Maximiliano Antonelli, Maria Liz Crespo, Andres Cicuttin	HW/SW codesign of maximum Lyapunov exponent estimator.	LASCAS	2017	DBLP DOI BibTeX RDF
16	Guilherme C. Pereira, Maria Cecília Calani Baranauskas	Supporting people on fighting lesbian, gay, bisexual, and transgender (LGBT) prejudice: a critical codesign process.	IHC	2017	DBLP DOI BibTeX RDF
16		Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, CODES+ISSS 2017, Seoul, Republic of Korea, October 15-20, 2017	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Okan Zafer Batur, Günhan Dündar, Mutlu Koca	LNA-ESD-PCB codesign for robust operation of IR-UWB non-coherent receiver.	SMACD	2017	DBLP DOI BibTeX RDF
16	K. B. Anuroop, Anu James, M. Neema	Hardware Software Codesign for a Hybrid Substitution Box.	VLSID	2017	DBLP DOI BibTeX RDF
16	Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda	Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks.	DAC	2017	DBLP DOI BibTeX RDF
16	Umar Sharif	Hardware/Software Codesign Approaches to Public Key Cryptosystems.		2017	RDF
16	Thierry Moreau, Felipe Augusto, Patrick Howe, Armin Alaghi, Luis Ceze	Exploiting quality-energy tradeoffs with arbitrary quantization: special session paper.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Hamid Nejatollahi, Nikil D. Dutt, Rosario Cammarota	Trends, challenges and needs for lattice-based cryptography implementations: special session.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Sudeep Pasricha, Janardhan Rao Doppa, Krishnendu Chakrabarty, Saideep Tiku, Daniel Dauwe, Shi Jin 0001, Partha Pratim Pande	Data analytics enables energy-efficiency and robustness: from mobile to manycores, datacenters, and networks (special session paper).	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Alessandro Danese, Graziano Pravadelli, Valeria Bertacco	DOVE: pinpointing firmware security vulnerabilities via symbolic control flow assertion mining (work-in-progress).	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Festus Hategekimana, Christophe Bobda	Towards the application of flask security architecture to SoC design: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Korosh Vatanparvar, Sina Faezi, Igor Burago, Marco Levorato, Mohammad Abdullah Al Faruque	Driving behavior modeling and estimation for battery optimization in electric vehicles: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Yue Zhu, Fei Wu 0005, Qin Xiong, Changsheng Xie	Alert-and-transfer: an evolutionary architecture for SSD-based storage systems.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Hantao Huang, Suleman Khalid Rai, Wenye Liu, Hao Yu 0001	A fast online sequential learning accelerator for IoT network intrusion detection: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Xue-Yang Zhu	A unified framework for throughput analysis of synchronous data flow graphs under memory constraints: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Nina Bindel, Juliane Krämer, Johannes Schreiber	Hampering fault attacks against lattice-based signature schemes: countermeasures and their efficiency (special session).	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Elizabeth O'Sullivan, Francesco Regazzoni 0001	Efficient arithmetic for lattice-based cryptography: special session paper.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Forrest N. Iandola, Kurt Keutzer	Small neural nets are beautiful: enabling embedded systems with small deep-neural-network architectures.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Keni Qiu, Zhiyao Gong, Dongqin Zhou, Weiwen Chen, Yongpan Liu	Retention state-aware energy management for efficient nonvolatile processors: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Lei Gong, Chao Wang 0003, Xi Li 0003, Huaping Chen 0001, Xuehai Zhou	A power-efficient and high performance FPGA accelerator for convolutional neural networks: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Qiao Li 0001, Liang Shi, Yejia Di, Yajuan Du, Kaijie Wu 0001, Chun Jason Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha	A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Honglan Jiang, Leibo Liu, Jie Han 0001	An efficient hardware design for cerebellar models using approximate circuits: special session paper.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Weichen Liu, Lei Yang 0018, Weiwen Jiang, Nan Guan	Communication optimization for thermal reliable many-core systems: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Dave Burke, Dainius Jenkus, Issa Qiqieh, Rishad A. Shafik, Shidhartha Das, Alex Yakovlev	Significance-driven adaptive approximate computing for energy-efficient image processing applications: special session paper.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Fatih Karabacak, Ümit Y. Ogras, Sule Ozev	Remote detection of unauthorized activity via spectral analysis: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Omayma Matoussi, Frédéric Pétrot	IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	M. Naghashi, Sayyed Hasan Mozafari, Shaahin Hessabi	Heterogeneous redundancy to address performance and cost in multi-core SIMT: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Bryan Donyanavard, Amir Mahdi Hosseini Monazzah, Tiago Mück, Nikil D. Dutt	Exploring fast and slow memories in HMP core types: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	William Hwang, Mohamed M. Sabry Aly, Yash H. Malviya, Mingyu Gao 0001, Tony F. Wu, Christos Kozyrakis, H.-S. Philip Wong, Subhasish Mitra	3D nanosystems enable embedded abundant-data computing: special session paper.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Arman Iranfar, Marina Zapater, David Atienza	A machine learning-based approach for power and thermal management of next-generation video coding on MPSoCs: work-in-progress.	CODES+ISSS	2017	DBLP DOI BibTeX RDF
16	Ryan Gary Kim, Wonje Choi 0001, Zhuo Chen, Partha Pratim Pande, Diana Marculescu, Radu Marculescu	Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
16	George Lentaris, Ioannis Stamoulias, Dimitrios Soudris, Manolis I. A. Lourakis	HW/SW Codesign and FPGA Acceleration of Visual Odometry Algorithms for Rover Navigation on Mars.	IEEE Trans. Circuits Syst. Video Technol.	2016	DBLP DOI BibTeX RDF
16	Bowen Zheng, Peng Deng, Anguluri Rajasekhar, Qi Zhu 0002, Fabio Pasqualetti	Cross-Layer Codesign for Secure Cyber-Physical Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
16	Edwin G. W. Peters, Daniel E. Quevedo, Minyue Fu 0001	Controller and Scheduler Codesign for Feedback Control Over IEEE 802.15.4 Networks.	IEEE Trans. Control. Syst. Technol.	2016	DBLP DOI BibTeX RDF
16	Xuan Wang 0001, Jiang Xu 0001, Zhe Wang 0003, Haoran Li 0002, Peng Yang 0003, Luan H. K. Duong, Rafael K. V. Maeda, Zhifei Wang	Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
16	Diya Joseph, Geetika Kaur, Pinaki Chakraborty	An exercise on hardware/software codesign following the RISC model.	Comput. Appl. Eng. Educ.	2016	DBLP DOI BibTeX RDF
16	Imène Mhadhbi, Slim Ben Othman, Slim Ben Saoud	An Efficient Technique for Hardware/Software Partitioning Process in Codesign.	Sci. Program.	2016	DBLP DOI BibTeX RDF
16	Caleb Serafy, Zhiyuan Yang 0001, Ankur Srivastava 0001, Yuanchen Hu, Yogendra Joshi	Thermoelectric Codesign of 3-D CPUs and Embedded Microfluidic Pin-Fin Heatsinks.	IEEE Des. Test	2016	DBLP DOI BibTeX RDF
16	Hassan Sepehrian, Amin Yekani, Leslie A. Rusch, Wei Shi 0007	CMOS-Photonics Codesign of an Integrated DAC-Less PAM-4 Silicon Photonic Transmitter.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
16	S. M. Shamsul Alam, GoangSeog Choi	Design and implementation of a novel LT codec architecture on TTA based codesign environment.	IEICE Electron. Express	2016	DBLP DOI BibTeX RDF
16	Hyun-Jun Cha, Woo-Hyuk Jeong, Jong-Chan Kim	Control-Scheduling Codesign Exploiting Trade-Off between Task Periods and Deadlines.	Mob. Inf. Syst.	2016	DBLP DOI BibTeX RDF
16	Robert de Simone	Keynote talk II: Multiform logical time for Me/Mo-codesign.	MEMOCODE	2016	DBLP DOI BibTeX RDF
16	Mingyu Wang, Zhaolin Li	STLAC: A spatial and temporal locality-aware cache and network-on-chip codesign for tiled many-core systems.	ASP-DAC	2016	DBLP DOI BibTeX RDF
16	Venkateshwarlu Y. Gudur, Sandeep Thallada, Abhinay R. Deevi, Venkata Krishna Gande, Amit Acharyya, Vasundhra Bhandari, Paresh Sharma, S. Saqib Khursheed, Ganesh R. Naik	Reconfigurable hardware-software codesign methodology for protein identification.	EMBC	2016	DBLP DOI BibTeX RDF
16	Malik Umar Sharif, Rabia Shahid, Kris Gaj, Marcin Rogawski	Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off.	FPL	2016	DBLP DOI BibTeX RDF
16	Leandro Andrade Martinez, Eduardo Marques	A hardware/software codesign framework for vision-based ADAS.	FPL	2016	DBLP DOI BibTeX RDF
16		Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES 2016, Pittsburgh, Pennsylvania, USA, October 1-7, 2016	CODES+ISSS	2016	DBLP DOI BibTeX RDF
16	Qin Wang 0005, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li 0005, Ulf Schlichtmann, Yici Cai	Control-fluidic CoDesign for paper-based digital microfluidic biochips.	ICCAD	2016	DBLP DOI BibTeX RDF
16	Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar	Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems.	CASES	2016	DBLP DOI BibTeX RDF
16	Rita Maldonado Branco, Joana Quental, Óscar Ribeiro	Playing with personalisation and openness in a codesign project involving people with dementia.	PDC (1)	2016	DBLP DOI BibTeX RDF