Search results for "D-latch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Debesh Bhatta, Suvadeep Banerjee, Abhijit Chatterjee	A Noise Aware CML Latch Modelling for Large System Simulation.	VLSID	2015	DBLP DOI BibTeX RDF
16	Dongsuk Jeon, Michael B. Henry, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester	An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
16	Hong-Ting Lin, Yi-Lin Chuang, Zong-Han Yang, Tsung-Yi Ho	Pulsed-Latch Utilization for Clock-Tree Power Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
16	Taehui Na, Seung-Han Woo, Jisu Kim, Hanwool Jeong, Seong-Ook Jung	Comparative Study of Various Latch-Type Sense Amplifiers.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
16	I-Chyn Wey, Yu-Sheng Yang, Bing-Chen Wu, Chien-Chang Peng	A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
16	Neeta Pandey, Kirti Gupta, Maneesha Gupta	An efficient triple-tail cell based PFSCL D latch.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
16	Weicheng Qiu, Xiang-Ai Cheng, Rui Wang, Zhongjie Xu, Chao Shen	The transient analysis of latch-up in CMOS transmission gate induced by laser.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
16	Niklas U. Andersson, Mark Vesterbacka	A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
16	Jianguo Hu, Zhikui Duan, Junrui Qin	Multiple nodes upset tolerance DICE latch based on on-state transistor.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
16	Hao Zheng, Xiangning Fan	A preamplifier-latch comparator for high accuracy high speed switched-capacitors pipelined ADC.	CSNDSP	2014	DBLP DOI BibTeX RDF
16	Zhengfeng Huang	A high performance SEU-tolerant latch for nanoscale CMOS technology.	DATE	2014	DBLP DOI BibTeX RDF
16	Hayoung Kim, Dongyoung Kim, Jae-Joon Kim, Sungjoo Yoo, Sunggu Lee	Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs.	DATE	2014	DBLP DOI BibTeX RDF
16	Huaguo Liang, Zhi Wang, Zhengfeng Huang, Aibin Yan	Design of a Radiation Hardened Latch for Low-Power Circuits.	ATS	2014	DBLP DOI BibTeX RDF
16	Dennis Oland Larsen, Pere Llimos Muntal, Ivan H. H. Jørgensen, Erik Bruun	High-voltage pulse-triggered SR latch level-shifter design considerations.	NORCHIP	2014	DBLP DOI BibTeX RDF
16	Puwanan Chumtong, Masaru Kojima, Mitsuhiro Horade, Kenichi Ohara, Kazuto Kamiyama, Yasushi Mae, Yoshikatsu Akiyama, Masayuki Yamato, Tatsuo Arai	Analytical design and fabrication of thermal latch valve driven flexible microscaffold for applications in tissue engineering.	NEMS	2014	DBLP DOI BibTeX RDF
16	Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang 0005, Min-Jer Wang, Wei Hwang	A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC.	CICC	2014	DBLP DOI BibTeX RDF
16	Katerina Katsarou, Yiorgos Tsiatouhas	Double node charge sharing SEU tolerant latch design.	IOLTS	2014	DBLP DOI BibTeX RDF
16	Ravi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian	Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths.	VLSID	2014	DBLP DOI BibTeX RDF
16	Stephan Held, Ulrike Schorr	Post-Routing Latch Optimization for Timing Closure.	DAC	2014	DBLP DOI BibTeX RDF
16	Jong-In Kim, Ba-Ro-Saim Sung, Wan Kim, Seung-Tak Ryu	A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
16	Justin J. Levandoski, Sudipta Sengupta	The BW-Tree: A Latch-Free B-Tree for Log-Structured Flash Storage.	IEEE Data Eng. Bull.	2013	DBLP BibTeX RDF
16	Hyoungjun Na, Tetsuo Endoh	A High Performance Current Latch Sense Amplifier with Vertical MOSFET.	IEICE Trans. Electron.	2013	DBLP DOI BibTeX RDF
16	Tadao Matsunaga, Kentaro Totsu, Masayoshi Esashi, Yoichi Haga	Tactile display using shape memory alloy micro-coil actuator and magnetic latch mechanism.	Displays	2013	DBLP DOI BibTeX RDF
16	Bill Teng, Jason Helge Anderson	Latch-Based Performance Optimization for Field-Programmable Gate Arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
16	Chih-Long Chang, Iris Hui-Ru Jiang	Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
16	Rahebeh Niaraki Asli, Saeideh Shirinzadeh	High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design.	J. Electron. Test.	2013	DBLP DOI BibTeX RDF
16	I-Chyn Wey, Yi-Jung Lan, Chien-Chang Peng	Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
16	Luca Sterpone	SEL-UP: A CAD tool for the sensitivity analysis of radiation-induced Single Event Latch-Up.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
16	Jie Chen, Zhengwei Du	Device simulation studies on latch-up effects in CMOS inverters induced by microwave pulse.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
16	Ramin Rajaei, Mahmoud Tabandeh, Mahdi Fazeli	Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
16	Jie Chen, Zhengwei Du	Understanding and modeling of internal transient latch-up susceptibility in CMOS inverters due to microwave pulses.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
16	Melvin Eze, Ozcan Ozturk 0001, Vijaykrishnan Narayanan	Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
16	Sangmin Kim, Duckhwan Kim 0001, Youngsoo Shin	Pulsed-latch ASIC synthesis in industrial design flow.	ASP-DAC	2013	DBLP DOI BibTeX RDF
16	Tae-Keun Kim, Dong Yeop Kim, Dong Hoon Cha, Seung Hwan Lim, Bong-Seok Kim, Chang-Woo Park	Solenoid-based and latch-typed brake system for in-wheel module.	URAI	2013	DBLP DOI BibTeX RDF
16	Takashi Horikawa	Latch-free data structures for DBMS: design, implementation, and evaluation.	SIGMOD Conference	2013	DBLP DOI BibTeX RDF
16	Dan Stoica, Mario Motz	A dual vertical Hall latch with direction detection.	ESSCIRC	2013	DBLP DOI BibTeX RDF
16	Xuanchang Zhou, Guoqiang Hang	Design of ternary D flip-flop using one latch with neuron-MOS literal circuit.	ICNC	2013	DBLP DOI BibTeX RDF
16	Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li 0001, Charles J. Alpert, David Z. Pan	Clock power minimization using structured latch templates and decision tree induction.	ICCAD	2013	DBLP DOI BibTeX RDF
16	Minsik Cho, Hua Xiang 0001, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri	LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs.	ICCAD	2013	DBLP DOI BibTeX RDF
16	Vladimir M. Milovanovic, Horst Zimmermann	A fully differential CMOS self-biased two-stage preamplifier-latch threshold detection comparator.	ISCAS	2013	DBLP DOI BibTeX RDF
16	Chorng-Sii Hwang, Ting-Li Chu, Po-Hsun Chen	DLL-based programmable clock multiplier using differential toggle-pulsed latch.	SoCC	2013	DBLP DOI BibTeX RDF
16	Zong-Han Yang, Tsung-Yi Ho	Timing-aware clock gating of pulsed-latch circuits for low power design.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
16	Pi-Feng Chiu, Meng-Fan Chang, Che-Wei Wu, Ching-Hao Chuang, Shyh-Shyuan Sheu, Yu-Sheng Chen, Ming-Jinn Tsai	Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
16	Xiayu Li, Song Jia, Limin Liu, Yuan Wang 0001	A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF).	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
16	Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin	Clock Gating Synthesis of Pulsed-Latch Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2012	DBLP DOI BibTeX RDF
16	Bing Li 0005, Ning Chen 0006, Ulf Schlichtmann	Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2012	DBLP DOI BibTeX RDF
16	Terrence S. T. Mak	Truncation error analysis of MTBF computation for multi-latch synchronizers.	Microelectron. J.	2012	DBLP DOI BibTeX RDF
16	Haiqing Nan, Ken Choi	Low cost and highly reliable hardened latch design for nanoscale CMOS technology.	Microelectron. Reliab.	2012	DBLP DOI BibTeX RDF
16	Peter Grossmann, Miriam Leeser, Marvin Onabajo	Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
16	Haiqing Nan, Ken Choi	High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
16	Minjae Lee	A 20GHz variability-aware robust, high-speed and low-power MOS CML latch.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
16	Khosrov Dabbagh-Sadeghipour	An accurate track-and-latch comparator.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
16	Chan-Soo Lee, Jung-Woong Park, Hyung-Gyoo Lee, Nam-Soo Kim, Hai-Feng Jin	Latch-Controlled Current Cell for Low Power Current-Steering D/A Converter.	UKSim	2012	DBLP DOI BibTeX RDF
16	Yongsuk Choi, Yong-Bin Kim, Fabrizio Lombardi	Soft error masking latch for sub-threshold voltage operation.	MWSCAS	2012	DBLP DOI BibTeX RDF
16	Keisuke Inoue, Mineo Kaneko	Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis.	MWSCAS	2012	DBLP DOI BibTeX RDF
16	Ricky Yiu-kee Choi, Chi-Ying Tsui	A novel offset cancellation technique for dynamic comparator latch.	MWSCAS	2012	DBLP DOI BibTeX RDF
16	Chih-Long Chang, Iris Hui-Ru Jiang, Yu-Ming Yang, Evan Y.-W. Tsai, Aki S.-H. Chen	Novel pulsed-latch replacement based on time borrowing and spiral clustering.	ISPD	2012	DBLP DOI BibTeX RDF
16	Thomas Kissinger, Benjamin Schlegel, Dirk Habich, Wolfgang Lehner	KISS-Tree: smart latch-free in-memory indexing on modern architectures.	DaMoN	2012	DBLP DOI BibTeX RDF
16	Kazuyuki Tanimura, Nikil D. Dutt	LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
16	Haiqing Nan, Ken Choi	Soft error tolerant latch design with low cost for nanoelectronic systems.	ISCAS	2012	DBLP DOI BibTeX RDF
16	Norhuzaimin Julai, Alexandre Yakovlev, Alexandre V. Bystrov	Error detection and correction of single event upset (SEU) tolerant latch.	IOLTS	2012	DBLP DOI BibTeX RDF
16	Keisuke Inoue, Mineo Kaneko	Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
16	Riadul Islam	A highly reliable SEU hardened latch and high performance SEU hardened flip-flop.	ISQED	2012	DBLP DOI BibTeX RDF
16	Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita	SEU Tolerant Robust Latch Design.	VDAT	2012	DBLP DOI BibTeX RDF
16	Keisuke Inoue, Mineo Kaneko	Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation.	IPSJ Trans. Syst. LSI Des. Methodol.	2011	DBLP DOI BibTeX RDF
16	Haipeng Zhang, Ruisheng Qi, Liang Zhang, Buchun Su, Dejun Wang	Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity.	VLSI Design	2011	DBLP DOI BibTeX RDF
16	Seungwhun Paik, Seonggwan Lee, Youngsoo Shin	Retiming Pulsed-Latch Circuits With Regulating Pulse Width.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
16	Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang	Pulsed-Latch Aware Placement for Timing-Integrity Optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
16	Jason Sewall, Jatin Chhugani, Changkyu Kim, Nadathur Satish, Pradeep Dubey	PALM: Parallel Architecture-Friendly Latch-Free Modifications to B+ Trees on Many-Core Processors.	Proc. VLDB Endow.	2011	DBLP BibTeX RDF
16	Ippokratis Pandis, Pinar Tözün, Ryan Johnson 0001, Anastasia Ailamaki	PLP: Page Latch-free Shared-everything OLTP. (PDF / PS)	Proc. VLDB Endow.	2011	DBLP DOI BibTeX RDF
16	Dionyz Pogany, Sergey Bychikhin, Michael Heer, W. Mamanee, Erich Gornik	Application of transient interferometric mapping method for ESD and latch-up analysis.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
16	Haiqing Nan, Ken Choi	Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
16	Roxane Llido, J. Gomez, Vincent Goubier, N. Froidevaux, L. Dufayard, Gérald Haller, Vincent Pouget, Dean Lewis	Photoelectric Laser Stimulation applied to Latch-Up phenomenon and localization of parasitic transistors in an industrial failure analysis laboratory.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
16	Youngsoo Shin, Seungwhun Paik	Pulsed-Latch Circuits: A New Dimension in ASIC Design.	IEEE Des. Test Comput.	2011	DBLP DOI BibTeX RDF
16	Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh	Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor.	ETS	2011	DBLP DOI BibTeX RDF	GRAAL, fault detection, DSP, soft error, SETs
16	Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin	Pulser gating: A clock gating of pulsed-latch circuits.	ASP-DAC	2011	DBLP DOI BibTeX RDF
16	Bill Teng, Jason Helge Anderson	Latch-Based Performance Optimization for FPGAs.	FPL	2011	DBLP DOI BibTeX RDF
16	Carlos Aristoteles De la Cruz-Blas, Michael M. Green	CMOS latch based on a class-AB transconductor.	ECCTD	2011	DBLP DOI BibTeX RDF
16	Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin	Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power.	ICCAD	2011	DBLP DOI BibTeX RDF
16	Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu	PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs.	ICCAD	2011	DBLP DOI BibTeX RDF
16	Peiyuan Wang, Xiang Chen 0010, Yiran Chen 0001, Hai Li 0001, Seung H. Kang, Xiaochun Zhu, Wenqing Wu	A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.	CICC	2011	DBLP DOI BibTeX RDF
16	Jong-In Kim, Wan Kim, Barosaim Sung, Seung-Tak Ryu	A time-domain latch interpolation technique for low power flash ADCs.	CICC	2011	DBLP DOI BibTeX RDF
16	Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho	Pulsed-latch-based clock tree migration for dynamic power reduction.	ISLPED	2011	DBLP BibTeX RDF
16	Li Yu, Jingyong Zhang, Lei Wang 0029, Jianguo Lu	A 12-bit fully differential SAR ADC with dynamic latch comparator for portable physiological monitoring applications.	BMEI	2011	DBLP DOI BibTeX RDF
16	Chih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker	Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events.	ISCAS	2011	DBLP DOI BibTeX RDF
16	Ramin Rajaei, Mahmoud Tabandeh, Bizhan Rashidian	Single event upset immune latch circuit design using C-element.	ASICON	2011	DBLP DOI BibTeX RDF
16	Sandeep Sriram, Haiqing Nan, Ken Choi	Low power latch design in near sub-threshold region to improve reliability for soft error.	ISQED	2011	DBLP DOI BibTeX RDF
16	Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo	Low power semi-static TSPC D-FFs using split-output latch.	ISOCC	2011	DBLP DOI BibTeX RDF
16	Pan Dong, Long Fan, Suge Yue, Hongchao Zheng, Shougang Du	New Latch-Up Model for Deep Sub-micron Integrated Circuits.	DASC	2011	DBLP DOI BibTeX RDF
16	S. H. Woo, H. Kang, K. Park, S.-O. Jung	Offset voltage estimation model for latch-type sense amplifiers.	IET Circuits Devices Syst.	2010	DBLP DOI BibTeX RDF
16	X. She, N. Li	Low-overhead single-event upset hardened latch using programmable resistance cells.	IET Comput. Digit. Tech.	2010	DBLP DOI BibTeX RDF
16	Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin	HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
16	Karl Malbrain	A Blink Tree latch method and protocol to support synchronous node deletion	CoRR	2010	DBLP BibTeX RDF
16	Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang	A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
16	Hossein Karimiyan Alidash, Vojin G. Oklobdzija	Low-Power Soft Error Hardened Latch.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
16	Augusto Tazzoli, Martina Cordoni, Paolo Colombo, C. Bergonzoni, Gaudenzio Meneghesso	Time-To-Latch-Up investigation of SCR devices as ESD protection structures on 65 nm technology platform.	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
16	Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo	Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
16	Yeonbae Chung, Weijie Cheng	CMOS latch bit-cell array for low-power SRAM design.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
16	Santosh N. Varanasi, Kenneth S. Stevens, Graham M. Birtwistle	Concurrency Reduction of Untimed Latch Protocols - Theory and Practice.	ASYNC	2010	DBLP DOI BibTeX RDF
16	Seungwhun Paik, Lee-eun Yu, Youngsoo Shin	Statistical time borrowing for pulsed-latch circuit designs.	ASP-DAC	2010	DBLP DOI BibTeX RDF