Search results for "DRAM"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Meng Huang, Shufang Si, Zheng He, Ying Zhou, Sijia Li, Hong Wang, Jinying Liu, Dongsheng Xie, Mengmeng Yang, Kang You, Chris Choi, Yi Tang, Xiaojie Li, Shibing Qian, Xiaodong Yang, Long Hou, Weiping Bai, Zhongming Liu, Yanzhe Tang, Qiong Wu, Yanqin Wang, Tao Dou, Jake Kim, Guilei Wang, Jie Baisp, Adachi Takao, Chao Zhao, Abraham Yoo	A 3D Stackable 1T1C DRAM: Architecture, Process Integration and Circuit Simulation.	IMW	2023	DBLP DOI BibTeX RDF
13	Woosong Jung, Hyojun Kim, Yeonggeun Song, Kwang-Hoon Lee, Deog-Kyoon Jeong	A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces.	CICC	2023	DBLP DOI BibTeX RDF
13	Ziming Chen, Quan Deng, Yongwen Wang	Fast Approximate LUT-based Vector Multiplication in DRAM.	ICPADS	2023	DBLP DOI BibTeX RDF
13	Arghavan Mohammadhassani, Anup Das 0001	Improving Performance of Network-on-Memory Architectures via (De-)/Compression-in-DRAM.	SLIP	2023	DBLP DOI BibTeX RDF
13	Ruey-Heng Lee, Peng-Sheng Chen	Pointer Analysis for Programs on Hybrid DRAM-PM Memory Systems.	ICPP Workshops	2023	DBLP DOI BibTeX RDF
13	Yuhwan Shin, Yongwoo Jo, Juyeop Kim, Junseok Lee, Jongwha Kim, Jaehyouk Choi	A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Woongrae Kim, Chulmoon Jung, Seong Nyuh Yoo, Duckhwa Hong, Jeongjin Hwang, Jungmin Yoon, Oh-Yong Jung, Joonwoo Choi, Sanga Hyun, Mankeun Kang, Sangho Lee, Dohong Kim, Sanghyun Ku, Donhyun Choi, Nogeun Joo, Sangwoo Yoon, Junseok Noh, Byeongyong Go, Cheolhoe Kim, Sunil Hwang, Mihyun Hwang, Seol-Min Yi, Hyungmin Kim, Sanghyuk Heo, Yeonsu Jang, Kyoungchul Jang, Shinho Chu, Yoonna Oh, Kwidong Kim, Junghyun Kim, Soohwan Kim, Jeongtae Hwang, Sangil Park, Junphyo Lee, In-Chul Jeong, Joohwan Cho, Jonghwan Kim	A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Nezam Rohbani, Mohammad Arman Soleimani, Hamid Sarbazi-Azad	CoolDRAM: An Energy-Efficient and Robust DRAM.	ISLPED	2023	DBLP DOI BibTeX RDF
13	Heewoo Kim, Haojie Ye, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati	RecPIM: A PIM-Enabled DRAM-RRAM Hybrid Memory System For Recommendation Models.	ISLPED	2023	DBLP DOI BibTeX RDF
13	Baptiste Lepers, Willy Zwaenepoel	Johnny Cache: the End of DRAM Cache Conflicts (in Tiered Main Memory Systems).	OSDI	2023	DBLP BibTeX RDF
13	Xu Zhang, Tianyue Lu, Yisong Chang, Ke Zhang 0017, Mingyu Chen 0001	Morpheus: An Adaptive DRAM Cache with Online Granularity Adjustment for Disaggregated Memory.	ICCD	2023	DBLP DOI BibTeX RDF
13	Aman Sinha, Yuhao Fang, Bo-Cheng Lai	REGAL: Reprogrammable Engines for Genome Analysis on LPDDR4x-based Stacked DRAM.	ISCAS	2023	DBLP DOI BibTeX RDF
13	Tai-Feng Chen, Yutaka Masuda, Tohru Ishihara	A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design.	SOCC	2023	DBLP DOI BibTeX RDF
13	Wenya Deng, Zhi Wang, Yang Guo, Jian Zhang, Zhenyu Wu, Yaohua Wang	DAS: A DRAM-Based Annealing System for Solving Large-Scale Combinatorial Optimization Problems.	ICA3PP (3)	2023	DBLP DOI BibTeX RDF
13	Tao Tao, Zhiwen Xiao, Jibin Wang, Jing Shang, Zhihui Wu	THRCache: DRAM-NVM Multi-level Cache with Thresholded Heterogeneous Random Choices.	ICA3PP (4)	2023	DBLP DOI BibTeX RDF
13	Supreeth Mysore Shivanandamurthy, Sairam Sri Vatsavai, Ishan G. Thakkar, Sayed Ahmad Salehi	AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning.	ISQED	2023	DBLP DOI BibTeX RDF
13	Mayank Kabra, Prashanth H. C., Kedar Deshpande, Madhav Rao	eDRAM-OESP: A novel performance efficient in-embedded-DRAM-compute design for on-edge signal processing application.	ISQED	2023	DBLP DOI BibTeX RDF
13	Hyunsoo Lee, Hyundong Lee, Minseung Shin, Gyuri Shin, Sumin Jeon, Taigon Song	High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture.	ISOCC	2023	DBLP DOI BibTeX RDF
13	Taegun Kim, Dong Keun Lee, Sihyun Kim, Sangwan Kim	A simulation study about the memory operation of 3D-stacked capacitor-less 1T DRAM cells based on ferroelectric field-effect transistors (FeFETs).	ISOCC	2023	DBLP DOI BibTeX RDF
13	Manolis Katsaragakis, Konstantinos Stavrakakis, Dimosthenis Masouros, Lazaros Papadopoulos, Dimitrios Soudris	Adjacent LSTM-Based Page Scheduling for Hybrid DRAM/NVM Memory Systems.	PARMA-DITAM	2023	DBLP DOI BibTeX RDF
13	Lukas Steiner, Gustavo Delazeri, Iron Prando da Silva, Matthias Jung 0001, Norbert Wehn	Automatic DRAM Subsystem Configuration with irace.	DroneSE/RAPIDO@HiPEAC	2023	DBLP DOI BibTeX RDF
13	Vikram Narayanan, David Detweiler, Tianjiao Huang, Anton Burtsev	DRAMHiT: A Hash Table Architected for the Speed of DRAM.	EuroSys	2023	DBLP DOI BibTeX RDF
13	Hyun-A. Ahn, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Garam Choi, Jun-Seo Park, Bo-Hyeon Lee, Jin-Hyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Changsik Yoo, Tae-Young Oh	A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications.	A-SSCC	2023	DBLP DOI BibTeX RDF
13	Hyunji Kim, Eunkyung Ham, Sunyoung Park, Hana Kim, Ji-Hoon Kim	A DRAM Bandwidth-Scalable Sparse Matrix-Vector Multiplication Accelerator with 89% Bandwidth Utilization Efficiency for Large Sparse Matrix.	A-SSCC	2023	DBLP DOI BibTeX RDF
13	Byeongkeon Lee, Donghyeon Lee, Jisu Ok, Wonsup Yoon, Sue Moon	Host Efficient Networking Stack Utilizing NIC DRAM.	APNet	2023	DBLP DOI BibTeX RDF
13	Haocong Luo, Ataberk Olgun, Abdullah Giray Yaglikçi, Yahya Can Tugrul, Steve Rhyner, Meryem Banu Cavlak, Joël Lindegger, Mohammad Sadrosadati, Onur Mutlu	RowPress: Amplifying Read Disturbance in Modern DRAM Chips.	ISCA	2023	DBLP DOI BibTeX RDF
13	Palash Das, Hemangee K. Kapoor	NDIE: A Near DRAM Inference Engine Exploiting DIMM's Parallelism.	APCCAS	2023	DBLP DOI BibTeX RDF
13	Yanqi Pan, Yifeng Zhang, Wen Xia, Xiangyu Zou, Cai Deng	HUNTER: Releasing Persistent Memory Write Performance with A Novel PM-DRAM Collaboration Architecture.	DAC	2023	DBLP DOI BibTeX RDF
13	Yan Ding 0004, Chubo Liu, Mingxing Duan, Wanli Chang 0001, Keqin Li 0001, Kenli Li 0001	HAIMA: A Hybrid SRAM and DRAM Accelerator-in-Memory Architecture for Transformer.	DAC	2023	DBLP DOI BibTeX RDF
13	Timothy M. Hollis, Ronny Schneider, Martin Brox, Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon Garrido, David Ovard, Karl Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez Gonzalez, Cristian Chetreanu, Andrea Sorrentino, Jörg Weller, Peter Mayer 0003, Michael Richter 0003, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong	An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
13	Minjae Kim, Bryan S. Kim, Eunji Lee, Sungjin Lee 0001	A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores.	IEEE Comput. Archit. Lett.	2022	DBLP DOI BibTeX RDF
13	Lingxi Wu, Rasool Sharifi, Ashish Venkat, Kevin Skadron	DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching.	IEEE Comput. Archit. Lett.	2022	DBLP DOI BibTeX RDF
13	Yongwon Shin, Juseong Park, Jeongmin Hong, Hyojin Sung	Runtime Support for Accelerating CNN Models on Digital DRAM Processing-in-Memory Hardware.	IEEE Comput. Archit. Lett.	2022	DBLP DOI BibTeX RDF
13	Ranyang Zhou, Sepehr Tabrizchi, Arman Roohi, Shaahin Angizi	LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking.	IEEE Comput. Archit. Lett.	2022	DBLP DOI BibTeX RDF
13	Xinfeng Xie, Peng Gu, Jiayi Huang 0001, Yufei Ding, Yuan Xie 0001	MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures.	IEEE Comput. Archit. Lett.	2022	DBLP DOI BibTeX RDF
13	Sudershan Kumar, Prabuddha Sinha, Shirshendu Das	WinDRAM: Weak rows as in-DRAM cache.	Concurr. Comput. Pract. Exp.	2022	DBLP DOI BibTeX RDF
13	Cheng Ji, Zongwei Zhu, Xianmin Wang, Wenjie Zhai, Xuemei Zong, Anqi Chen, Mingliang Zhou	Task-aware swapping for efficient DNN inference on DRAM-constrained edge systems.	Int. J. Intell. Syst.	2022	DBLP DOI BibTeX RDF
13	Geraldo F. Oliveira, Juan Gómez-Luna, Saugata Ghose, Amirali Boroumand, Onur Mutlu	Accelerating Neural Network Inference With Processing-in-DRAM: From the Edge to the Cloud.	IEEE Micro	2022	DBLP DOI BibTeX RDF
13	Michael B. Sullivan 0001, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai 0002, Siva Kumar Sastry Hari, Stephen W. Keckler	Characterizing and Mitigating Soft Errors in GPU DRAM.	IEEE Micro	2022	DBLP DOI BibTeX RDF
13	Mingtai Li, Tuanjie Li, Yaqiong Tang	Improved thermal network modeling of die stacking DRAM and optimization.	Integr.	2022	DBLP DOI BibTeX RDF
13	Yoonah Paik, Chang Hyun Kim, Won Jun Lee, Seon Wook Kim	Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling.	IEEE Access	2022	DBLP DOI BibTeX RDF
13	Dong-Wan Ko, Won-Young Lee	A Single-Ended Transmitter With Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface.	IEEE Access	2022	DBLP DOI BibTeX RDF
13	Jeonghun Son, Jonghyeon Kim, Donghui Lee, Young-Jae Min	A Hybrid Low-Dropout (LDO) Regulator Using a Load Replication Circuit for DRAM Cores.	IEEE Access	2022	DBLP DOI BibTeX RDF
13	Matteo Andreozzi, Antonio Frangioni, Laura Galli, Giovanni Stea, Raffaele Zippo	A MILP approach to DRAM access worst-case analysis.	Comput. Oper. Res.	2022	DBLP DOI BibTeX RDF
13	Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang 0001	ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
13	Mengzhao Zhang, Jeong-Geun Kim, Su-Kyung Yoon, Shin-Dug Kim	Dynamic recognition prefetch engine for DRAM-PCM hybrid main memory.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
13	Zihao Zhan, Zhenkai Zhang, Xenofon D. Koutsoukos	A High-Speed, Long-Distance and Wall-Penetrating Covert Channel Based on EM Emanations from DRAM Clock.	J. Hardw. Syst. Secur.	2022	DBLP DOI BibTeX RDF
13	Susovan Chanda, Ashish Kumar Luhach, Waleed S. Alnumay, Indranil SenGupta, Diptendu Sinha Roy	A lightweight device-level Public Key Infrastructure with DRAM based Physical Unclonable Function (PUF) for secure cyber physical systems.	Comput. Commun.	2022	DBLP DOI BibTeX RDF
13	Po-Wei Chiu, Chris H. Kim	A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
13	Sangyoon Lee, Yong-Un Jeong, Jaekwang Yun, Joo-Hyung Chae, Suhwan Kim	A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
13	Pei Huang 0018, Kuan-Chang Chang, Junlin Ge, Chunyu Peng, Xiulong Wu, Junning Chen, Zhiting Lin	Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
13	Lukas Steiner, Matthias Jung 0001, Felipe S. Prado, Kirill Bykov, Norbert Wehn	DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM Analyses.	Int. J. Parallel Program.	2022	DBLP DOI BibTeX RDF
13	Payman Behnam, Mahdi Nazm Bojnordi	Adaptively Reduced DRAM Caching for Energy-Efficient High Bandwidth Memory.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
13	Renping Liu, Zhenhua Tan, Linbo Long, Yu Wu 0016, Yujuan Tan, Duo Liu	Improving Fairness for SSD Devices through DRAM Over-Provisioning Cache Management.	IEEE Trans. Parallel Distributed Syst.	2022	DBLP DOI BibTeX RDF
13	Yinjin Fu, Yutong Lu, Zhiguang Chen, Yang Wu, Nong Xiao	Design and Simulation of Content-Aware Hybrid DRAM-PCM Memory System.	IEEE Trans. Parallel Distributed Syst.	2022	DBLP DOI BibTeX RDF
13	Shu-Yen Lin, Shao-Cheng Wang	Thermal-constrained memory management for three-dimensional DRAM-PCM memory with deep neural network applications.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
13	Dongsuk Shin, Hakbeom Jang, Kiseok Oh, Jae W. Lee	An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory.	ACM Trans. Embed. Comput. Syst.	2022	DBLP DOI BibTeX RDF
13	Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury	Design of novel 3T ternary DRAM with single word-line using CNTFET.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
13	A. V. Arun, P. S. Sreelekshmi, Jobymol Jacob	Design and analysis of dopingless 1T DRAM using work function engineered tunnel field effect transistors.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
13	Ataberk Olgun, Juan Gómez-Luna, Konstantinos Kanellopoulos, Behzad Salami 0001, Hasan Hassan, Oguz Ergin, Onur Mutlu	PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques.	CoRR	2022	DBLP DOI BibTeX RDF
13	Minki Jeong, Wanyeong Jung	MAC-DO: Charge Based Multi-Bit Analog In-Memory Accelerator Compatible with DRAM Using Output Stationary Mapping.	CoRR	2022	DBLP DOI BibTeX RDF
13	Kaustav Goswami 0002, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee	VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design.	CoRR	2022	DBLP BibTeX RDF
13	Geraldo F. Oliveira, Juan Gómez-Luna, Saugata Ghose, Amirali Boroumand, Onur Mutlu	Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud.	CoRR	2022	DBLP DOI BibTeX RDF
13	Abdullah Giray Yaglikçi, Haocong Luo, Geraldo F. de Oliviera, Ataberk Olgun, Minesh Patel, Jisung Park 0001, Hasan Hassan, Jeremie S. Kim, Lois Orosa 0001, Onur Mutlu	Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices.	CoRR	2022	DBLP DOI BibTeX RDF
13	Lukas Steiner, Chirag Sudarshan, Matthias Jung 0001, Dominik Stoffel, Norbert Wehn	A Framework for Formal Verification of DRAM Controllers.	CoRR	2022	DBLP DOI BibTeX RDF
13	Adar Zeitak, Adam Morrison 0001	Cuckoo Trie: Exploiting Memory-Level Parallelism for Efficient DRAM Indexing.	CoRR	2022	DBLP BibTeX RDF
13	Nisa Bostanci, Ataberk Olgun, Lois Orosa 0001, Abdullah Giray Yaglikçi, Jeremie S. Kim, Hasan Hassan, Oguz Ergin, Onur Mutlu	DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators.	CoRR	2022	DBLP BibTeX RDF
13	Zhi Zhang 0001, Jiahao Qi, Yueqiang Cheng, Shijie Jiang, Yiyang Lin, Yansong Gao, Surya Nepal, Yi Zou	A Retrospective and Futurespective of Rowhammer Attacks and Defenses on DRAM.	CoRR	2022	DBLP BibTeX RDF
13	Abdullah Giray Yaglikçi, Ataberk Olgun, Minesh Patel, Haocong Luo, Hasan Hassan, Lois Orosa 0001, Oguz Ergin, Onur Mutlu	HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips.	CoRR	2022	DBLP DOI BibTeX RDF
13	Owen Millwood, Jack Miskelly, Bohao Yang, Prosanta Gope, Elif Bilge Kavun, Chenghua Lin	PUF-Phenotype: A Robust and Noise-Resilient Approach to Aid Intra-Group-based Authentication with DRAM-PUFs Using Machine Learning.	CoRR	2022	DBLP DOI BibTeX RDF
13	Minesh Patel, Taha Shahroodi, Aditya Manglik, Abdullah Giray Yaglikçi, Ataberk Olgun, Haocong Luo, Onur Mutlu	A Case for Transparent Reliability in DRAM Systems.	CoRR	2022	DBLP DOI BibTeX RDF
13	Chirag Sudarshan, Taha Soliman, Jan Lappas, Christian Weis, Mohammad Hassani Sadi, Matthias Jung 0001, Andre Guntoro, Norbert Wehn	A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2022	DBLP DOI BibTeX RDF
13	Aman Sinha, Huei-Chun Yang, Pei-Yi Liu, Yen-Shi Kuo, Yuhao Fang, Tien-Shuo Chang, Ke-Han Li, Bo-Cheng Lai	DSIM: Distributed Sequence Matching on Near-DRAM Accelerator for Genome Assembly.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2022	DBLP DOI BibTeX RDF
13	Subin Kim, Jun-Eun Park	Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes.	Sensors	2022	DBLP DOI BibTeX RDF
13	Chenji Liu, Lan Chen, Xiaoran Hao, Mao Ni	Optimized fast data migration for hybrid DRAM/STT-MRAM main memory.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
13	Bindu Agarwalla, Shirshendu Das, Nilkanta Sahu	Process variation aware DRAM-Cache resizing.	J. Syst. Archit.	2022	DBLP DOI BibTeX RDF
13	Yong Li, Lingfang Zeng, Guang Chen, Chunhua Gu, Fei Luo 0002, Weichao Ding, Zhan Shi, Joel Fuentes	A Multi-hashing Index for hybrid DRAM-NVM memory systems.	J. Syst. Archit.	2022	DBLP DOI BibTeX RDF
13	João Dinis Ferreira, Gabriel Falcão 0001, Juan Gómez-Luna, Mohammed Alser, Lois Orosa 0001, Mohammad Sadrosadati, Jeremie S. Kim, Geraldo F. Oliveira, Taha Shahroodi, Anant Nori, Onur Mutlu	pLUTo: Enabling Massively Parallel Computation In DRAM via Lookup Tables.		2022	DOI RDF
13	Irina Alam, Puneet Gupta 0001	COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors.	DSN	2022	DBLP DOI BibTeX RDF
13	Abdullah Giray Yaglikçi, Haocong Luo, Geraldo F. de Oliviera, Ataberk Olgun, Minesh Patel, Jisung Park 0001, Hasan Hassan, Jeremie S. Kim, Lois Orosa 0001, Onur Mutlu	Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices.	DSN	2022	DBLP DOI BibTeX RDF
13	Pengcheng Zhang, Yunong Wang, Xuhua Ma, Yaoheng Xu, Bin Yao 0002, Xudong Zheng, Linquan Jiang	Predicting DRAM-Caused Node Unavailability in Hyper-Scale Clouds.	DSN	2022	DBLP DOI BibTeX RDF
13	Chirag Sudarshan, Mohammad Hassani Sadi, Lukas Steiner, Christian Weis, Norbert Wehn	A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions.	SAMOS	2022	DBLP DOI BibTeX RDF
13	Yaakov Cohen, Kevin Sam Tharayil, Arie Haenel, Daniel Genkin, Angelos D. Keromytis, Yossi Oren, Yuval Yarom	HammerScope: Observing DRAM Power Consumption Using Rowhammer.	CCS	2022	DBLP DOI BibTeX RDF
13	Shu-Yen Lin, Guang-Fong Liu	Dynamic Thermal-Predicted Workload Movement with Three-Dimensional DRAM-RRAM Hybrid Memories for Convolutional Neural Network Applications.	ICCE-TW	2022	DBLP DOI BibTeX RDF
13	Felipe Lisboa Malaquias, Mihail Asavoae, Florian Brandner	A Coq Framework for More Trustworthy DRAM Controllers.	RTNS	2022	DBLP DOI BibTeX RDF
13	Ataberk Olgun, Juan Gómez-Luna, Konstantinos Kanellopoulos, Behzad Salami 0001, Hasan Hassan, Oguz Ergin, Onur Mutlu	PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques.	ISVLSI	2022	DBLP DOI BibTeX RDF
13	Jorge Semião, Luís Santos, Marcelino B. Santos	DRAM Performance Sensor.	HCI (7)	2022	DBLP DOI BibTeX RDF
13	Chirag Sudarshan, Taha Soliman, Thomas Kämpfe, Christian Weis, Norbert Wehn	FeFET versus DRAM based PIM Architectures: A Comparative Study.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
13	Da Wang, Yong Liu, Pengpeng Ren, Longda Zhou, Zhigang Ji, Junhua Liu, Runsheng Wang, Ru Huang	Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies.	IRPS	2022	DBLP DOI BibTeX RDF
13	Stefan Saroiu, Alec Wolman, Lucian Cojocar	The Price of Secrecy: How Hiding Internal DRAM Topologies Hurts Rowhammer Defenses.	IRPS	2022	DBLP DOI BibTeX RDF
13	Nam-Hyun Lee, S. Lee, S.-H. Kim, G.-J. Kim, K. W. Lee, Y. S. Lee, Y. C. Hwang, H. S. Kim, S. Pae	Transistor Reliability Characterization for Advanced DRAM with HK+MG & EUV process technology.	IRPS	2022	DBLP DOI BibTeX RDF
13	Yong Liu, Pengpeng Ren, Da Wang, Longda Zhou, Zhigang Ji, Junhua Liu, Runsheng Wang, Ru Huang	New Insight into the Aging Induced Retention Time Degraded of Advanced DRAM Technology.	IRPS	2022	DBLP DOI BibTeX RDF
13	Young Seo Lee, Gunjae Koo, Young-Ho Gong, Sung Woo Chung	Stealth ECC: A Data-Width Aware Adaptive ECC Scheme for DRAM Error Resilience.	DATE	2022	DBLP DOI BibTeX RDF
13	Yongfeng Wang, Yinjin Fu, Yubo Liu, Zhiguang Chen, Nong Xiao	Characterizing and Optimizing Hybrid DRAM-PM Main Memory System with Application Awareness.	DATE	2022	DBLP DOI BibTeX RDF
13	Manolis Katsaragakis, Lazaros Papadopoulos, Christos Baloukas, Dimitrios Soudris	Memory Management Methodology for Application Data Structure Refinement and Placement on Heterogeneous DRAM/NVM Systems.	DATE	2022	DBLP DOI BibTeX RDF
13	Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu, Shyh-Jye Jou	DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks.	DATE	2022	DBLP DOI BibTeX RDF
13	Abdullah Giray Yaglikçi, Ataberk Olgun, Minesh Patel, Haocong Luo, Hasan Hassan, Lois Orosa 0001, Oguz Ergin, Onur Mutlu	HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips.	MICRO	2022	DBLP DOI BibTeX RDF
13	Fei Gao 0016, Georgios Tziantzioulis, David Wentzlaff	FracDRAM: Fractional Values in Off-the-Shelf DRAM.	MICRO	2022	DBLP DOI BibTeX RDF
13	João Dinis Ferreira, Gabriel Falcão 0001, Juan Gómez-Luna, Mohammed Alser, Lois Orosa 0001, Mohammad Sadrosadati, Jeremie S. Kim, Geraldo F. Oliveira, Taha Shahroodi, Anant Nori, Onur Mutlu	pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables.	MICRO	2022	DBLP DOI BibTeX RDF
13	Rachit Rajat, Yongqin Wang, Murali Annavaram	PageORAM: An Efficient DRAM Page Aware ORAM Strategy.	MICRO	2022	DBLP DOI BibTeX RDF