Search results for "EURO-DAC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Bernd Kleinjohann, Elisabeth Kupitz	Tool communication in an integrated synthesis environment.	EURO-DAC	1991	DBLP BibTeX RDF
1	Alice McKeon, Antony Wakeling	The automatic diagnosis of faults in analogue and mixed-signal circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Ton Kalker	Formal methods for silicon compilation.	EURO-DAC	1991	DBLP BibTeX RDF
1	Wim F. J. Verhaegh, Emile H. L. Aarts, Jan H. M. Korst, Paul E. R. Lippens	Improved force-directed scheduling.	EURO-DAC	1991	DBLP BibTeX RDF
1	Tara Weber, Fabio Somenzi	Periodic signal suppression in a concurrent fault simulator.	EURO-DAC	1991	DBLP BibTeX RDF
1	Tony Ambler, Jochen A. G. Jess, Hugo De Man (eds.)	Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991	EURO-DAC	1991	DBLP BibTeX RDF
1	Gjalt G. de Jong	Data flow graphs: system specification with the most unrestricted semantics.	EURO-DAC	1991	DBLP BibTeX RDF
1	K. Z. Dimopoulos, John N. Avaritsiotis, S. J. White	Electrical modelling of lossy on-chip multilevel interconnecting lines.	EURO-DAC	1991	DBLP BibTeX RDF
1	F. Crowet, Marc Davio, C. Dierieck, J. Durieu, G. Louis, Chantal Ykman-Couvreur	PHIFACT a design space exploration program.	EURO-DAC	1991	DBLP BibTeX RDF
1	Georg Sigl, Ulf Schlichtmann	Goal oriented slicing enumeration through shape function clipping.	EURO-DAC	1991	DBLP BibTeX RDF
1	Spyros Tragoudas, R. Farrell, Fillia Makedon	Circuit partitioning into small sets: a tool to support testing with further applications.	EURO-DAC	1991	DBLP BibTeX RDF
1	Larry G. Jones	Incremental switch-level simulation with zero/integer-delay.	EURO-DAC	1991	DBLP BibTeX RDF
1	Michele Favalli, Piero Olivo, Bruno Riccò	A probabilistic fault model for analog faults.	EURO-DAC	1991	DBLP BibTeX RDF
1	Ernst G. Ulrich, Karen Panetta Lentz, Stephen R. Demba, Rahul Razdan	Concurrent MIN-MAX simulation.	EURO-DAC	1991	DBLP BibTeX RDF
1	Larry McMurchie, Craig Anderson 0001, Gaetano Borriello	Hybrid compiled/interpreted simulation of MOS circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Harald Gundlach, Bernd K. Koch, Klaus-Dieter Müller-Glaser	On the selection of a partial scan path with respect to target faults.	EURO-DAC	1991	DBLP BibTeX RDF
1	S. Bapat, James P. Cohoon	SHARP-looking geometric partitioning.	EURO-DAC	1991	DBLP BibTeX RDF
1	Frank P. Burns, D. J. Kinniment, Albert Koelmans	Correct interactive transformational synthesis of DSP hardware.	EURO-DAC	1991	DBLP BibTeX RDF
1	Einar J. Aas, Gunnar Nystu	Experiments with autonomous test of PLAs.	EURO-DAC	1991	DBLP BibTeX RDF
1	Sanjiv Narayan, Frank Vahid, Daniel D. Gajski	Translating system specifications to VHDL.	EURO-DAC	1991	DBLP BibTeX RDF
1	Paul E. R. Lippens, Jef L. van Meerbergen, Albert van der Werf, Wim F. J. Verhaegh, B. T. McSweeney, Jos Huisken, O. McArdle	PHIDEO: a silicon compiler for high speed algorithms.	EURO-DAC	1991	DBLP BibTeX RDF
1	Thomas M. Niermann, Janak H. Patel	HITEC: a test generation package for sequential circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Wanlin Cao, Y. Edmund Lien, Yuane Qiu, Li Shao	A distributed engineering database management system for IC design.	EURO-DAC	1991	DBLP BibTeX RDF
1	Piet Wambacq, Georges G. E. Gielen, Willy Sansen	Interactive symbolic distortion analysis of analogue integrated circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Jan Madsen	Delay estimation for CMOS functional cells.	EURO-DAC	1991	DBLP BibTeX RDF
1	Martin Rudolph, Michael Neher, Wolfgang Rosenstiel	Test scheduling and controller synthesis in the CADDY-system.	EURO-DAC	1991	DBLP BibTeX RDF
1	Achim G. Hoffmann	Towards optimizing global MinCut partitioning.	EURO-DAC	1991	DBLP BibTeX RDF
1	Glenn Jennings	GRTL: a graphical platform for pipelined system design.	EURO-DAC	1991	DBLP BibTeX RDF
1	Sandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar	Symbolic implication in test generation.	EURO-DAC	1991	DBLP BibTeX RDF
1	Louis-Oliver Donzelle, Pierre-François Dubois	A new approach to layout of custom analog cells.	EURO-DAC	1991	DBLP BibTeX RDF
1	Masahiro Fujita, Yusuke Matsunaga, Taeko Kakuda	On variable ordering of binary decision diagrams for the application of multi-level logic synthesis.	EURO-DAC	1991	DBLP BibTeX RDF
1	David T. Blaauw, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham	Functional abstraction of logic gates for switch-level simulation.	EURO-DAC	1991	DBLP BibTeX RDF
1	Farid Mheir-El-Saadi, Bozena Kaminska	A framework for hierarchical performance analysis.	EURO-DAC	1991	DBLP BibTeX RDF
1	Douglas M. Grant, Peter B. Denyer	Address Generation for array access based on modulus m counters.	EURO-DAC	1991	DBLP BibTeX RDF
1	Wayne H. Wolf	Decomposing data machines.	EURO-DAC	1991	DBLP BibTeX RDF
1	Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert	Formal sizing rules of CMOS circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Werner John, Werner Rissiek, Karl L. Paap	Circuit partitioning for waveform relaxation.	EURO-DAC	1991	DBLP BibTeX RDF
1	D. Bochmann, F. Dresig, B. Steinbach	A new decomposition method for multilevel circuit design.	EURO-DAC	1991	DBLP BibTeX RDF
1	Lalgudi N. Kannan, D. Sarma	Fast heuristic algorithms for finite state machine minimization.	EURO-DAC	1991	DBLP BibTeX RDF
1	David W. Knapp	Datapath optimization using feedback.	EURO-DAC	1991	DBLP BibTeX RDF
1	F. Monteiro, Bruno Rouzeyre, Georges Sagnes	High level synthesis: a data path partitioning method dedicated to speed enhancement.	EURO-DAC	1991	DBLP BibTeX RDF
1	Klaus Gröning, Walter Heijenga	Why to incorporate a data definition language into a CAD frameworks extension language.	EURO-DAC	1991	DBLP BibTeX RDF
1	Tadeusz Luba, Jerzy Kalinowski, Krzysztof Jasinski	PLATO: a CAD tool for logic synthesis based on decomposition.	EURO-DAC	1991	DBLP BibTeX RDF
1	P. Hallam, T. I. Pritchard, Gloria Childress Townsend	Performance macromodelling and optimization of regular VLSI structures.	EURO-DAC	1991	DBLP BibTeX RDF
1	Luis París, G. Berbel, T. Osés	Floorplanning strategy for mixed analog-digital VLSI integrated circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Koen Swings, Willy Sansen	DONALD: a workbench for interactive design space exploration and sizing of analog circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Françoise Martinolle, Jean Claude Geffroy, Bernard Soulas	Testability analysis of hierarchical finite state machines.	EURO-DAC	1991	DBLP BibTeX RDF
1	James Haralambides, Fillia Makedon	Iterative compaction: an improved approach to graph and circuit bisection.	EURO-DAC	1991	DBLP BibTeX RDF
1	Jos van Sas, Francky Catthoor, Peter Vandeput, Frank Rossaert, Hugo De Man	Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment.	EURO-DAC	1991	DBLP BibTeX RDF
1	Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham	Parallel switch-level simulation for VLSI.	EURO-DAC	1991	DBLP BibTeX RDF
1	Rumi Zahir, Wolfgang Fichtner	Specification of timing constraints for controller synthesis.	EURO-DAC	1991	DBLP BibTeX RDF
1	Shankar R. Mukherjee, Maqsoodul Mannan	Switch and logic-level modeling in EDIF 200: limitations and proposed solutions.	EURO-DAC	1991	DBLP BibTeX RDF
1	A. Compan, Alain Greiner, François Pêcheux, Frédéric Pétrot	GENVIEW: a portable source-level debugger for macrocell generators.	EURO-DAC	1991	DBLP BibTeX RDF
1	A. J. van der Hoeven, Ed F. Deprettere, P. van Prooijen, Patrick M. Dewilde	A hardware design system based on object-oriented principles.	EURO-DAC	1991	DBLP BibTeX RDF
1	Anas Kabbaj, Eduard Cerny, Michel R. Dagenais, François Bouthillier	Design by similarity using transaction modeling and statistical techniques.	EURO-DAC	1991	DBLP BibTeX RDF
1	M. Ambanelli, Michele Favalli, Piero Olivo, Bruno Riccò	Detection of PLA multiple crosspoint faults.	EURO-DAC	1991	DBLP BibTeX RDF
1	Frank Buijs, Thomas Lengauer	Synthesis of multi-level logic with one symbolic input.	EURO-DAC	1991	DBLP BibTeX RDF
1	Ting-Chi Wang, D. F. Wong 0001	Efficient shape curve construction in floorplan design.	EURO-DAC	1991	DBLP BibTeX RDF
1	Shen Lin 0001, Malgorzata Marek-Sadowska	A fast and efficient algorithm for determining fanout trees in large networks.	EURO-DAC	1991	DBLP BibTeX RDF
1	P. Duchene, Michel J. Declercq, S. M. Kang	An integrated layout system for sea-of-gates module generation.	EURO-DAC	1991	DBLP BibTeX RDF
1	Suresh Rajgopal, Akhilesh Tyagi	On probabilistic switch-level simulation for asynchronous circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Don E. Ross, Kenneth M. Butler, Rohit Kapur, M. Ray Mercer	Fast functional evaluation of candidate OBDD variable orderings.	EURO-DAC	1991	DBLP BibTeX RDF
1	Roy Thomas, Sandip Kundu	Synthesis of fully testable sequential machines.	EURO-DAC	1991	DBLP BibTeX RDF
1	Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer	Area and performance optimizations in path-based scheduling.	EURO-DAC	1991	DBLP BibTeX RDF
1	Gerard Tarroux, Bruno Rouzeyre, Georges Sagnes	Optimization of micro-controllers by partitioning.	EURO-DAC	1991	DBLP BibTeX RDF
1	Daniel Cock, Andy Carpenter	A proposed hardware fault simulation engine.	EURO-DAC	1991	DBLP BibTeX RDF
1	Benjamin Rogel-Favila, Antony Wakeling, Peter Y. K. Cheung	Model-based fault diagnosis of sequential circuits and its acceleration.	EURO-DAC	1991	DBLP BibTeX RDF
1	Steven T. Healey	An algorithm for improving optimal placement for river-routing.	EURO-DAC	1991	DBLP BibTeX RDF
1	Bernd Becker 0001, Ralf Hahn, Rolf Krieger, Uwe Sparmann	Structure based methods for parallel pattern fault simulation in combinational circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Jan Rosseel, Michaël F. X. B. van Swaaij, Francky Catthoor, Hugo De Man	Affine transformations for multi-dimensional signal processing on ASIC regular arrays.	EURO-DAC	1991	DBLP BibTeX RDF
1	David Filo, Jerry Chih-Yuan Yang, Frédéric Mailhot 0001, Giovanni De Micheli	Technology mapping for a two-output RAM-based field programmable gate array.	EURO-DAC	1991	DBLP BibTeX RDF
1	Mattie N. Sim, Patrick M. Dewilde	Design of a persistent programming environment in an object oriented language using clustering and composite objects.	EURO-DAC	1991	DBLP BibTeX RDF
1	Fridtjof Feldbusch, Ramayya Kumar	Verification of synthesized circuits at register transfer level with flow graphs.	EURO-DAC	1991	DBLP BibTeX RDF
1	Michael Kishinevsky, Alex Kondratyev, Alexander Taubin	Formal method for self-timed design.	EURO-DAC	1991	DBLP BibTeX RDF
1	Ravi Nair, Vivek Chickermane, Ray Chamberlain	Restructuring VLSI layout representations for efficiency.	EURO-DAC	1991	DBLP BibTeX RDF
1	Hongzhong Wu	On L × n boolean matrices with all L × k submatrices having 2k distinct row vectors.	EURO-DAC	1991	DBLP BibTeX RDF
1	Rafael Peset Llopis, R. J. H. Koopman, Hans G. Kerkhoff, J. A. Braat	A performance analysis tool for performance-driven micro-cell generation.	EURO-DAC	1991	DBLP BibTeX RDF
1	Fadi J. Kurdahi, Champaka Ramachandran	LAST: a Layout Area and Shape function esTimator for high level applications.	EURO-DAC	1991	DBLP BibTeX RDF
1	H. G. Yang, David M. Holburn	A hierarchical approach to timing verification in CMOS VLSI design.	EURO-DAC	1991	DBLP BibTeX RDF
1	Dahe Chen, Carl Sechen	Mickey: a macro cell global router.	EURO-DAC	1991	DBLP BibTeX RDF
1	Gary D. Hachtel, June-Kyung Rho, Fabio Somenzi, Reily M. Jacoby	Exact and heuristic algorithms for the minimization of incompletely specified state machines.	EURO-DAC	1991	DBLP BibTeX RDF
1	Kees van Berkel 0001, Joep L. W. Kessels, Marly Roncken, Ronald Saeijs, Frits D. Schalij	The VLSI-programming language tangram and its translation into handshake circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Mahesh Mehendale	An approach to design flow management in CAD frameworks.	EURO-DAC	1991	DBLP BibTeX RDF
1	Paul Stravers	Partitioning a network into n pieces with a time-efficient net cost function.	EURO-DAC	1991	DBLP BibTeX RDF
1	Bapiraju Vinnakota, Niraj K. Jha	MACHETE: synthesis of sequential machines for easy testability.	EURO-DAC	1991	DBLP BibTeX RDF
1	Amjad Hajjar, Alain Greiner, Roland Marbot, Payam Kiani	TAS: an accurate timing analyser for CMOS VLSI.	EURO-DAC	1991	DBLP BibTeX RDF
1	Kholdoun Torki, Michael Nicolaidis, Antônio Otávio Fernandes	A self-checking PLA automatic generator tool based on unordered codes encoding.	EURO-DAC	1991	DBLP BibTeX RDF
1	Robert Tjärnström	Clock independent timing verification of level-sensitive latches.	EURO-DAC	1991	DBLP BibTeX RDF
1	Antonio Rubio 0001, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita	An approach to the analysis and test of crosstalk faults in digital VLSI circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Kai-Win Lee, Carl Sechen	A global router for sea-of-gates circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Joel Besnard, Jacques Benkoski, Bernard Hennion	Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator.	EURO-DAC	1991	DBLP BibTeX RDF
1	Paolo Camurati, Tiziana Margaria, Paolo Prinetto	Resolution-based correctness proofs of synchronous circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Jacques Benkoski, Ronald B. Stewart	TATOO: an industrial timing analyzer with false path elimination and test pattern generation.	EURO-DAC	1991	DBLP BibTeX RDF
1	Tzi-cker Chiueh	HERESY: a hybrid approach to automatic schematic generation.	EURO-DAC	1991	DBLP BibTeX RDF
1	Shen Lin 0001, Malgorzata Marek-Sadowska, Ernest S. Kuh	SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits.	EURO-DAC	1991	DBLP BibTeX RDF
1	Lalgudi N. Kannan, D. Sarma	Array folding using heuristics and simulated annealing.	EURO-DAC	1991	DBLP BibTeX RDF
1	Chin-Yuan Kuo, Liang-Gee Chen, Tai-Ming Parng	An automatic synthesizer for CMOS operational amplifiers.	EURO-DAC	1991	DBLP BibTeX RDF
1	A. Kuehlmann, Yiannos Manoli	Module synthesis for finite state machines.	EURO-DAC	1991	DBLP BibTeX RDF
1	Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli	Optimization techniques for multiple output function synthesis.	EURO-DAC	1991	DBLP BibTeX RDF
1	Allen C.-H. Wu, Daniel D. Gajski	Glue-logic partitioning for floorplans with a rectilinear datapath.	EURO-DAC	1991	DBLP BibTeX RDF

Publications at "EURO-DAC"( http://dblp.L3S.de/Venues/EURO-DAC )