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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 210 occurrences of 148 keywords
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Results
Found 3186 publication records. Showing 3186 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Umar Afzaal, Jeong-A Lee |
FPGA-based design of a self-checking TMR voter.  |
FPL  |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely |
Line rate programmable packet processing in 100Gb networks. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario Werner, Thomas Unterluggauer, Robert Schilling, David Schaffenrath, Stefan Mangard |
Transparent memory encryption and authentication. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehya Nasser, Jean-Christophe Prévotet, M. Heiard, Jordane Lorandel |
Dynamic power estimation based on switching activity propagation. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco D. Santambrogio, Diana Göhringer, Dirk Stroobandt, Nele Mentens, Jari Nurmi (eds.) |
27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, September 4-8, 2017 |
FPL |
2017 |
DBLP BibTeX RDF |
|
| 1 | Jin Qiu, Ping Kang, Li Ding, Yipeng Yuan, Wenbo Yin, Lingli Wang |
FPGA acceleration of the scoring process of X!TANDEM for protein identification. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongyuan Ding, Miaoqing Huang |
PolyPC: Polymorphic parallel computing framework on embedded reconfigurable system. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaofan Zhang 0001, Xinheng Liu, Anand Ramachandran 0001, Chuanhao Zhuge, Shibin Tang, Peng Ouyang, Zuofu Cheng, Kyle Rupnow, Deming Chen |
High-performance video content recognition with long-term recurrent convolutional network for FPGA. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Christoforos Kachris, Elias Koromilas, Ioannis Stamelos, Dimitrios Soudris |
FPGA acceleration of spark applications in a Pynq cluster. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Size Xiao, Neil Bergmann, Adam Postula |
Parallel RRT∗ architecture design for motion planning. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mirjana Stojilovic |
Parallel FPGA routing: Survey and challenges. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Christos Rousopoulos, Ektoras Karandeinos, Grigorios Chrysos 0001, Apostolos Dollas, Dionisios N. Pnevmatikatos |
A generic high throughput architecture for stream processing. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaël Deest, Tomofumi Yuki, Sanjay V. Rajopadhye, Steven Derrien |
One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhe Lin 0007, Wei Zhang 0012, Sharad Sinha |
Decision tree based hardware power monitoring for run time dynamic power management in FPGA. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hosseinabady, José Luis Núñez-Yáñez |
A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ibrahim Ahmed 0001, Shuze Zhao, Olivier Trescases, Vaughn Betz |
Find the real speed limit: FPGA CAD for chip-specific application delay measurement. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Jiao, Cheng Luo, Wei Cao 0002, Xuegong Zhou, Lingli Wang |
Accelerating low bit-width convolutional neural networks with embedded FPGA. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Ting Chen, Jason Helge Anderson |
Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | John Clow, Georgios Tzimpragos, Deeksha Dangwal, Sammy Guo, Joseph McMahan, Timothy Sherwood |
A pythonic approach for rapid hardware prototyping and instrumentation. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Vladimir Rozic, Bohan Yang 0001, Jo Vliegen, Nele Mentens, Ingrid Verbauwhede |
The Monte Carlo PUF. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Naif Tarafdar, Thomas Lin, Nariman Eskandari, David Lion, Alberto Leon-Garcia, Paul Chow |
Heterogeneous virtualized network function framework for the data center. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yufei Ma 0002, Yu Cao 0001, Sarma B. K. Vrudhula, Jae-sun Seo |
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Julián Caba, Fernando Rincón, Julio Dondo Gazzano |
Functional & timing in-hardware verification of FPGA-based designs using unit testing frameworks. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond |
FPGA acceleration of multilevel ORB feature extraction for computer vision. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | David Sidler, Muhsen Owaida, Zsolt István, Kaan Kara, Gustavo Alonso |
doppioDB: A hardware accelerated database. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Shengjia Shao, Wayne Luk |
Customised pearlmutter propagation: A hardware architecture for trust region policy optimisation. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong |
High performance binary neural networks on the Xeon+FPGA™ platform. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Anuj Vaishnav, Jose Raul Garcia Ordaz, Dirk Koch |
A security library for FPGA interlays. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | ChenYang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui, ChongYang Zeng, Jie Jin, Bin Li 0013 |
An implementation of list successive cancellation decoder with large list size for polar codes. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinnan Ding, Shuguo Li |
Broken-Karatsuba multiplication and its application to Montgomery modular multiplication. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Yan 0005, Chenglu Jin, Fatemeh Tehranipoor, John A. Chandy |
Phase calibrated ring oscillator PUF design and implementation on FPGAs. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Nolting, Lin Liu, Guillermo Payá Vayá |
Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Michal Kekely, Jan Korenek |
Mapping of P4 match action tables to FPGA. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat |
ARMHEx: A framework for efficient DIFT in real-world SoCs. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroki Nakahara, Tomoya Fujii, Shimpei Sato |
A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto |
Parallel dot-products for deep learning on FPGA. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani |
In-switch approximate processing: Delayed tasks management for MapReduce applications. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano |
Body bias optimization for variable pipelined CGRA. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot, Hande Alemdar, Nicholas Caldwell, Vincent Leroy 0001 |
Scalable high-performance architecture for convolutional ternary neural networks on FPGA. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ho-Cheung Ng, Shuanglong Liu, Wayne Luk |
Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yohann Uguen, Florent de Dinechin, Steven Derrien |
Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | David J. Greaves |
Kiwi scientific acceleration at large: Incremental compilation and multi-FPGA HLS demo. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Artur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka |
Evaluating high-level design strategies on FPGAs for high-performance computing. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato |
A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Wild, Georg T. Becker, Tim Güneysu |
A fair and comprehensive large-scale analysis of oscillation-based PUFs for FPGAs. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Dennis R. E. Gnad, Fabian Oboril, Mehdi Baradaran Tahoori |
Voltage drop-based fault attacks on FPGAs using valid bitstreams. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio |
Optimizing streaming stencil time-step designs via FPGA floorplanning. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai |
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Benjamin Drozdenko, Suranga Handagala, Kaushik R. Chowdhury, Miriam Leeser |
FPGA modeling techniques for detecting and demodulating multiple wireless protocols. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivo Bolsens |
"All programmable FPGA, providing hardware efficiency to software programmers". |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuangnan Liu, Benjamin Carrión Schäfer |
Learning-based interconnect-aware dataflow accelerator optimization. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Festus Hategekimana, Taylor J. L. Whitaker, Md Jubaer Hossain Pantho, Christophe Bobda |
Shielding non-trusted IPs in SoCs. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitrios Bozikas, Nikolaos Alachiotis 0001, Pavlos Pavlidis, Euripides Sotiriades, Apostolos Dollas |
Deploying FPGAs to future-proof genome-wide analyses based on linkage disequilibrium. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Robin Aggleton, Luis E. Ardila-Perez, Fionn Amhairghen Ball, Matthias Norbert Balzer, James John Brooke, Luigi Calligaris, Michele Caselle, Davide Cieri, Emyr John Clement, Geoffrey Hall, Kristian Harder, Peter R. Hobson, Gregory M. Iles, Thomas James, Konstantinos Manolopoulos, Takashi Matsushita, Alexander D. Morton, David Newbold, Sudarshan Paramesvaran, Mark Franco Pesaresi, Ivan D. Reid, Andrew W. Rose, Oliver Sander, Thomas Schuh, Claire Shepherd-Themistocleous, Antoni Shtipliyski, Sioni Paris Summers, Alexander D. Tapper, Ian Tomalin, Kirika Uchida, Paschalis Vichoudis, Marc Weber |
A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Stylianos I. Venieris, Christos-Savvas Bouganis |
Latency-driven design for FPGA-based convolutional neural networks. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch |
Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric Matthews, Lesley Shannon |
TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | James J. Davis 0001, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides |
STRIPE: Signal selection for runtime power estimation. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Nachiket Kapre |
Deflection-routed butterfly fat trees on FPGAs. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanzhe Li, Kai Huang 0002, Luc Claesen |
High-quality view interpolation based on depth maps and its hardware implementation. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Bruno da Silva 0001, Laurent Segers, An Braeken, Abdellah Touhafi |
Runtime reconfigurable beamforming architecture for real-time sound-source localization. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel C. Dinis, Rui Fiel Cordeiro, Arnaldo S. R. Oliveira, José M. N. Vieira |
Towards an all-digital antenna array transmitter. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Weina Lu, Yu Hu 0001, Jing Ye 0001, Xiaowei Li 0001 |
TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Christoforos Kachris, Dimitrios Soudris |
A survey on reconfigurable accelerators for cloud computing. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jungwook Choi, Rob A. Rutenbar |
Configurable and scalable belief propagation accelerator for computer vision. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Fraser D. Robinson, Louise H. Crockett, William H. Nailon, Robert W. Stewart |
High-level synthesis for medical image processing on Systems on Chip: A case study. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele |
Preface. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Oleg Petelin, Vaughn Betz |
The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jose Canilho, Mário P. Véstias, Horácio C. Neto |
Multi-core for K-means clustering on FPGA. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Luke Newmeyer, Doran Wilde, Brent E. Nelson, Michael J. Wirthlin |
Efficient processing of phased array radar in sense and avoid application using heterogeneous computing. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Xinyu Niu, Nicholas Ng, Tomofumi Yuki, Shaojun Wang, Nobuko Yoshida, Wayne Luk |
EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Bajaj Ronak, Suhaib A. Fahmy |
Improved resource sharing for FPGA DSP blocks. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt |
Runtime-quality tradeoff in partitioning based multithreaded packing. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Heiner Giefers, Peter W. J. Staar, Raphael Polig |
Energy-efficient stochastic matrix function estimator for graph analytics on FPGA. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko |
Fast hierarchical NPN classification. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi 0001 |
Stress-aware routing to mitigate aging effects in SRAM-based FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ammon Gruwell, Peter Zabriskie, Michael J. Wirthlin |
High-speed programmable FPGA Configuration through JTAG. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jacob Couch, John Arkoian |
An investigation into a circuit based supply chain analyzer for FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Yufei Ma 0002, Naveen Suda, Yu Cao 0001, Jae-sun Seo, Sarma B. K. Vrudhula |
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama |
Annotation-based finite-state transducers on reconfigurable devices. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Daisuke Suzuki, Takahiro Hanyu |
A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hadi Mardani Kamali, Shaahin Hessabi |
AdapNoC: A fast and flexible FPGA-based NoC simulator. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoyin Ma, Jose M. Rodriguez Borbon, Walid A. Najjar, Amit K. Roy-Chowdhury |
Optimizing hardware design for Human Action Recognition. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Naouss, François Marc |
Modelling delay degradation due to NBTI in FPGA Look-up tables. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Oto Petura, Ugo Mureddu, Nathalie Bochard, Viktor Fischer, Lilian Bossuet |
A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Onur Ulusel, Christopher B. Picardo, Christopher B. Harris, Sherief Reda, R. Iris Bahar |
Hardware acceleration of feature detection and description algorithms on low-power embedded platforms. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Bruno da Silva 0001, Laurent Segers, An Braeken, Abdellah Touhafi |
A runtime reconfigurable FPGA-based microphone array for sound source localization. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Aaron Stoddard, Ammon Gruwell, Peter Zabriskie, Michael J. Wirthlin |
High-speed PCAP configuration scrubbing on Zynq-7000 All Programmable SoCs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles Lo, Paul Chow |
Model-based optimization of High Level Synthesis directives. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongming Shen 0001, Michael Ferdman, Peter A. Milder |
Overcoming resource underutilization in spatial CNN accelerators. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Nina Engelhardt, Hayden Kwok-Hay So |
GraVF: A vertex-centric distributed graph processing framework on FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin Hau Hoo, Yajun Ha, Akash Kumar 0001 |
ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Malik Umar Sharif, Rabia Shahid, Kris Gaj, Marcin Rogawski |
Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Xitian Fan, Huimin Li 0005, Wei Cao 0002, Lingli Wang |
DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Xijie Jia, Kaiyuan Guo, Wenqiang Wang, Yu Wang 0002, Huazhong Yang |
SRI-SURF: A better SURF powered by scaled-RAM interpolator on FPGA. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne |
Designing a virtual runtime for FPGA accelerators in the cloud. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Huimin Li 0005, Xitian Fan, Li Jiao, Wei Cao 0002, Xuegong Zhou, Lingli Wang |
A high performance FPGA-based accelerator for large-scale convolutional neural networks. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Christophe Huriaux, Olivier Sentieys, Russell Tessier |
Effects of I/O routing through column interfaces in embedded FPGA fabrics. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Elias Vansteenkiste, Seppe Lenders, Dirk Stroobandt |
Liquid: Fast placement prototyping through steepest gradient descent movement. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Zdenek Vasícek, Lukás Sekanina |
Search-based synthesis of approximate circuits implemented into FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
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