Search results for "Programmability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Christian Sauer 0001, Matthias Gries, Sebastian Dirk	Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform.	DATE	2007	DBLP DOI BibTeX RDF
9	Zhuan Ye, John Grosspietsch, Gokhan Memik	Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio.	DATE	2007	DBLP DOI BibTeX RDF
9	Weiguo Liu, Bertil Schmidt, Gerrit Voss, Wolfgang Müller-Wittig	Molecular Dynamics Simulations on Commodity GPUs with CUDA.	HiPC	2007	DBLP DOI BibTeX RDF
9	Ralf Lämmel	Scrap your boilerplate with XPath-like combinators.	POPL	2007	DBLP DOI BibTeX RDF	XML programming, generic functional programming
9	Afshin Niktash, Hooman Parizi, Nader Bagherzadeh	A Reconfigurable Processor for Forward Error Correction.	ARCS	2007	DBLP DOI BibTeX RDF	Turbo, Forward Error Correction, Processing Element, Reconfigurable Processor, Viterbi
9	Yong Li 0006, Zhiying Wang 0003, Jian Ruan, Kui Dai	A Low-Power Globally Synchronous Locally Asynchronous FFT Processor.	HPCC	2007	DBLP DOI BibTeX RDF
9	Tiffany M. Mintz, James P. Davis	Low-power tradeoffs for mobile computing applications: embedded processors versus custom computing kernels.	ACM Southeast Regional Conference	2007	DBLP DOI BibTeX RDF	algorithmic state machine, low-power design, reconfigurable computing, embedded processors
9	Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis 0001, Soo-Ik Chae, Ahmed Amine Jerraya	Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.	SCOPES	2007	DBLP DOI BibTeX RDF
9	André Ribeiro Cardoso, Ahmed Serhrouchni, Joaquim Celestino Jr., Mikaël Salaün	Convergence among Peer-to-Peer and Programmable Networks.	ECUMN	2007	DBLP DOI BibTeX RDF
9	A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy 0001, Ranjani Narayan	REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.	FPL	2007	DBLP DOI BibTeX RDF
9	Emilena Specht, Ricardo Miotto Redin, Luigi Carro, Luís da Cunha Lamb, Érika F. Cota, Flávio Rech Wagner	Analysis of the use of declarative languages for enhanced embedded system software development.	SBCCI	2007	DBLP DOI BibTeX RDF	embedded software, modeling languages, system level modeling, system level synthesis
9	Philip A. Bernstein, Sergey Melnik 0001	Model management 2.0: manipulating richer mappings.	SIGMOD Conference	2007	DBLP DOI BibTeX RDF	engineered mapping, data integration, data exchange, schema mapping, schema matching, schema evolution, model management, data translation
9	Thomas Weigold, Thorsten Kramp, Peter Buhler	ePVM - An Embeddable Process Virtual Machine.	COMPSAC (1)	2007	DBLP DOI BibTeX RDF
9	Akira Hatanaka, Nader Bagherzadeh	A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template.	IPDPS	2007	DBLP DOI BibTeX RDF
9	Min Xie, Youren Wang, Li Wang, Yuan Zhang	Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit.	ICES	2007	DBLP DOI BibTeX RDF	Operator-based programmable cell circuit, FPGA, Reconfigurable computing, Reconfigurable hardware, Information processing
9	Theofanis Orphanoudakis, George Kornaros, Ioannis Mavroidis, Aristides Nikologiannis, Ioannis Papaefstathiou	An Embedded Networking SoC for purely Ethernet MANs/WANs.	ISCC	2007	DBLP DOI BibTeX RDF
9	Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr	A code-generator generator for multi-output instructions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	ISS, code-selection, compiler/architecture co-design, ASIP
9	Arndt Bode	Scalability for Petaflops systems.	APPT	2007	DBLP DOI BibTeX RDF
9	Shaoshan Liu, Jean-Luc Gaudiot	Synchronization Mechanisms on Modern Multi-core Architectures.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
9	Yong Li 0006, Zhiying Wang 0003, Xue-mi Zhao, Jian Ruan, Kui Dai	Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
9	Tao Li 0008, Xiaoming Zhang, Zhigang Sun	DynaNP - A Coarse-grain Dataflow Network Processor Architecture with Dynamic Configurable Processing Path.	SNPD (3)	2007	DBLP DOI BibTeX RDF
9	Walid A. Najjar	Compiling code accelerators for FPGAs.	CASES	2007	DBLP DOI BibTeX RDF	FPGA code acceleration
9	Sebastian Fleissner	GPU-Accelerated Montgomery Exponentiation.	International Conference on Computational Science (1)	2007	DBLP DOI BibTeX RDF	Montgomery Exponentiation, Encryption, GPGPU
9	Rahul Sarpeshkar, Woradorn Wattanapanitch, Benjamin I. Rapoport, Scott K. Arfin, Michael W. Baker, Soumyajit Mandal, Michale S. Fee, Sam Musallam, Richard A. Andersen	Low-Power Circuits for Brain-Machine Interfaces.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Klaus Gaedke, Malte Borsum, Marco Georgi, Andreas Kluger, Jean-Pierre Le Glanic, Pascal Bernard	Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Ivan Padilla, Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín	Highly Linear V/I Converter with Programmable Current Mirrors.	ISCAS	2007	DBLP DOI BibTeX RDF
9	David W. Graham, Paul E. Hasler	Run-Time Programming of Analog Circuits Using Floating-Gate Transistors.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Mohammad Fazle Azeem, Asim Baig	Design and Fabrication of Basic Building Blocks For Analog Implementation of Programmable Fuzzy Logic Controller.	IRI	2007	DBLP DOI BibTeX RDF
9	Xipeng Shen, Michael L. Scott, Chengliang Zhang, Sandhya Dwarkadas, Chen Ding 0001, Mitsunori Ogihara	Analysis of input-dependent program behavior using active profiling.	Experimental Computer Science	2007	DBLP DOI BibTeX RDF	active profiling, program phase analysis and prediction, memory management, dynamic optimization
9	Michele Favalli	Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth.	DFT	2007	DBLP DOI BibTeX RDF
9	Weiguo Liu, Wolfgang Müller-Wittig, Bertil Schmidt	Performance Predictions for General-Purpose Computation on GPUs.	ICPP	2007	DBLP DOI BibTeX RDF
9	K. Scott Hemmert, Keith D. Underwood, Arun Rodrigues	An architecture to perform NIC based MPI matching.	CLUSTER	2007	DBLP DOI BibTeX RDF
9	Seng Lin Shee, Sri Parameswaran	Design Methodology for Pipelined Heterogeneous Multiprocessor System.	DAC	2007	DBLP DOI BibTeX RDF
9	Raffaella Grieco, Delfina Malandrino, Vittorio Scarano	A Scalable Cluster-based Infrastructure for Edge-computing Services.	World Wide Web	2006	DBLP DOI BibTeX RDF	intermediary systems, personalized and mobile services, World Wide Web, proxy servers, Edge Services
9	Minghua Shi, Amine Bermak	An Efficient Digital VLSI Implementation of Gaussian Mixture Models-Based Classifier.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
9	Sze Wei Lee, S.-C. Lim	VLSI Design of a Wavelet Processing Core.	IEEE Trans. Circuits Syst. Video Technol.	2006	DBLP DOI BibTeX RDF
9	Yan Lin 0001, Lei He 0001	Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	Kenneth L. Calvert, Jim Griffioen, Su Wen	Scalable Network Management Using Lightweight Programmable Network Services.	J. Netw. Syst. Manag.	2006	DBLP DOI BibTeX RDF	ephemeral state, lightweight network services, scalability, network management, Programmable networks
9	Miguel Angel Domínguez, José L. Ausín, J. Francisco Duque-Carrillo, Guido Torelli	A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	analog built-in self-test, analog IC test, on-chip spectrum analyzer, switched-capacitor circuits, non-uniform sampling
9	Tero Kangas, Timo D. Hämäläinen, Kimmo Kuusilinna	Scalable Architecture for SoC Video Encoders.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	System-on-Chip, video encoding, architecture exploration
9	Song Fu, Cheng-Zhong Xu 0001, Brian Wims, Ramzi Basharahil	Distributed shared arrays: A distributed virtual machine with mobility support for reconfiguration.	Clust. Comput.	2006	DBLP DOI BibTeX RDF	Distributed shared arrays (DSA), Distributed virtual machine, DSA service migration, Parallel programming model
9	Pavan Sikka, Peter I. Corke, Philip Valencia, Christopher Crossman, Dave Swain, Greg Bishop-Hurley	Wireless adhoc sensor and actuator networks on the farm.	IPSN	2006	DBLP DOI BibTeX RDF	farm management, sensor network applications
9	Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala	Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform.	SAMOS	2006	DBLP DOI BibTeX RDF
9	Yang Yu 0009, Loren J. Rittle, Vartika Bhandari, Jason B. LeBrun	Supporting concurrent applications in wireless sensor networks.	SenSys	2006	DBLP DOI BibTeX RDF	Maté, dynamic group formation, group-keyed code dissemination, group-keyed code distribution, melete, muse, trickle, wireless sensor networks, virtual machine, network protocols, concurrent applications
9	Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling	A type architecture for hybrid micro-parallel computers.	FPGA	2006	DBLP DOI BibTeX RDF
9	Klaus Mueller 0001, Fang Xu	Practical considerations for GPU-accelerated CT.	ISBI	2006	DBLP DOI BibTeX RDF
9	Qi Zhang 0023, Roy Eagleson, Terry M. Peters	Real-time visualization of 4D cardiac MR images using graphics processing units.	ISBI	2006	DBLP DOI BibTeX RDF
9	Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	ASIP design and synthesis for non linear filtering in image processing.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
9	Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis	Networks on chips for high-end consumer-electronics TV system architectures.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
9	Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang	A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
9	Amilcar do Carmo Lucas, Sven Heithecker, Peter Rüffer, Rolf Ernst, Holger Rückert, Gerhard Wischermann, Karin Gebel, Reinhard Fach, Wolfgang Huther, Stefan Eichner, Gunter Scheller	A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications.	DATE	2006	DBLP DOI BibTeX RDF	digital film, stream-based architecture, weak-programming, FPGA, motion-estimation, reconfigurable
9	Moti Yung, Yunlei Zhao	Interactive Zero-Knowledge with Restricted Random Oracles.	TCC	2006	DBLP DOI BibTeX RDF
9	Roberto Andreoli, Rosario De Chiara, Ugo Erra, Antonio Iannaccone, Fernando La Greca, Vittorio Scarano	Some Real Experiences in Developing Virtual Environments.	IV	2006	DBLP DOI BibTeX RDF
9	Shuyi Chen, Sheng Li 0008, Guoping Wang	Real-Time Rendering of Light Shafts on GPU.	ISVC (1)	2006	DBLP DOI BibTeX RDF
9	Lerong Cheng, Jinjun Xiong, Lei He 0001, Mike Hutton	FPGA Performance Optimization Via Chipwise Placement Considering Process Variations.	FPL	2006	DBLP DOI BibTeX RDF
9	Mike Hutton, Yan Lin 0001, Lei He 0001	Placement and Timing for FPGAs Considering Variations.	FPL	2006	DBLP DOI BibTeX RDF
9	Koen Van Renterghem, Dieter Verhulst, S. Verschuere, Pieter Demuytere, Jan Vandewege, Xing-Zhi Qiu	A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access.	FPL	2006	DBLP DOI BibTeX RDF
9	Jürgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztián Flautner	Topic 18: Embedded Parallel Systems.	Euro-Par	2006	DBLP DOI BibTeX RDF
9	Reiner W. Hartenstein	RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances.	IPDPS	2006	DBLP DOI BibTeX RDF
9	Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones	Design space exploration for low-power reconfigurable fabrics.	IPDPS	2006	DBLP DOI BibTeX RDF
9	Maya B. Gokhale	RAW keynote 1: the outer limits: reconfigurable computing in space and in orbit.	IPDPS	2006	DBLP DOI BibTeX RDF
9	Arpith C. Jacob, Brandon Harris, Jeremy Buhler, Roger D. Chamberlain, Young H. Cho	Scalable Softcore Vector Processor for Biosequence Applications.	FCCM	2006	DBLP DOI BibTeX RDF
9	Michael Attig, Gordon J. Brebner	Systematic Characterization of Programmable Packet Processing Pipelines.	FCCM	2006	DBLP DOI BibTeX RDF
9	Qi Huang, Xiaoping Chen, Bingfeng Wang, Ronghai Cai, Kaiyu Qin	The Concept of Computing on Chip (CoC) for Electric Power System Application.	PARELEC	2006	DBLP DOI BibTeX RDF	CoC, VLSI, SOC, Power System, Transient Simulation
9	Javier Setoain, Christian Tenllado, Manuel Prieto 0001, David Valencia, Antonio Plaza, Javier Plaza	Parallel Hyperspectral Image Processing on Commodity Graphics Hardware.	ICPP Workshops	2006	DBLP DOI BibTeX RDF
9	Yang Liu, Wayne Huang 0002, John Johnson, Sheila Vaidya	GPU Accelerated Smith-Waterman.	International Conference on Computational Science (4)	2006	DBLP DOI BibTeX RDF
9	Paul Gruijters, Bertrand Vandewiele	Algorithm Partitioning and SoC Design for OFDM Communication Systems Using Multiple Application Specific Processors.	ISM	2006	DBLP DOI BibTeX RDF
9	Milind S. Sawant, Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín	Linear compact CMOS OTA with multidecade tuning, -62dB IM3, -75dB SFDR, constant input range and two independent degrees of freedom for gain adjustment.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Somsubhra Mondal, Rajarshi Mukherjee, Seda Ogrenci Memik	Fine-grain thermal profiling and sensor insertion for FPGAs.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Eric D. Marsman, Robert M. Senger, Gordy A. Carichner, Sundus Kubba, Michael S. McCorquodale, Richard B. Brown	DSP architecture for cochlear implants.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Julien Mairal, Renaud Keriven, Alexandre Chariot	Fast and Efficient Dense Variational Stereo on GPU.	3DPVT	2006	DBLP DOI BibTeX RDF
9	Tae-Young Kim, Kyoung-Su Oh	Design of a Programmable Vertex Processing Unit for Mobile Platforms.	EUC Workshops	2006	DBLP DOI BibTeX RDF
9	Puxuan Dong, Griff L. Bilbro, Mo-Yuen Chow	Implementation of Artificial Neural Network for Real Time Applications Using Field Programmable Analog Arrays.	IJCNN	2006	DBLP DOI BibTeX RDF
9	Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell	Functional Test of Field Programmable Analog Arrays.	VTS	2006	DBLP DOI BibTeX RDF	analog built-in self-test, transient response analysis, FPAA
9	Tarek A. El-Ghazawi, Dave Bennett, Daniel S. Poznanovic, Allan Cantle, Keith D. Underwood, Rob Pennington, Duncan A. Buell, Alan D. George, Volodymyr V. Kindratenko	Reconfigurable supercomputing - Is high-performance reconfigurable computing the next supercomputing paradigm?	SC	2006	DBLP DOI BibTeX RDF
9	Mark I. Parsons, Francis W. Wray	Programming FPGAs - Programming FPGAs: challenges and successes.	SC	2006	DBLP DOI BibTeX RDF
9	Ana L. Milanova, Sonia Fahmy, David R. Musser, Bülent Yener	A Secure Programming Paradigm for Network Virtualization.	BROADNETS	2006	DBLP DOI BibTeX RDF
9	Yuan Lin 0002, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner	SODA: A Low-power Architecture For Software Radio.	ISCA	2006	DBLP DOI BibTeX RDF
9	Jaime H. Moreno	Chip-level integration: the new frontier for microprocessor architecture.	SPAA	2006	DBLP DOI BibTeX RDF	chip-level integration, microprocessor architecture
9	Yaron Weinsberg, Danny Dolev, Tal Anker, Pete Wyckoff	HYDRA: A Novel Framework for Making High-Performance Computing Offload Capable.	LCN	2006	DBLP DOI BibTeX RDF
9	Wei-Kai Chan, Shao-Yi Chien	Subword Parallel Architecture for Connected Component Labeling and Morphological Operations.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Aaron R. Kunze, Stephen D. Goglin, Erik J. Johnson	Symerton--using virtualization to accelerate packet processing.	ANCS	2006	DBLP DOI BibTeX RDF	networking, virtualization, communications systems
9	Piti Piyachon, Yan Luo	Efficient memory utilization on network processors for deep packet inspection.	ANCS	2006	DBLP DOI BibTeX RDF	parallel processing, pattern matching, network processor, deep packet inspection
9	Seiji Maeda, Shigehiro Asano, Tomofumi Shimada, Koichi Awazu, Haruyuki Tago	A Real-Time Software Platform for the Cell Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	real-time resource scheduler, Scalability, Consumer electronics, Cell processor
9	John Montrym, Henry P. Moreton	The GeForce 6800.	IEEE Micro	2005	DBLP DOI BibTeX RDF	GPU, Graphics, SIMD, multi-threaded, MIMD, parallel processors
9	Yan Lin 0001, Fei Li 0003, Lei He 0001	Circuits and architectures for field programmable gate array with configurable supply voltage.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
9	Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy 0001	Synthesis of application-specific highly efficient multi-mode cores for embedded systems.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, high level synthesis, synthesis, Digital signal processing (DSP), application specific integrated circuits (ASIC), reconfigurable system
9	Frederik De Keukelaere, Saar De Zutter, Rik Van de Walle	MPEG-21 digital item Processing.	IEEE Trans. Multim.	2005	DBLP DOI BibTeX RDF
9	Ruby B. Lee, A. Murat Fiskiran	PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	multimedia, processor architecture, instruction set architecture, media processing, ISA
9	Nizamettin Aydin, Tughrul Arslan, David R. S. Cumming	A direct-sequence spread-spectrum communication system for integrated sensor microsystems.	IEEE Trans. Inf. Technol. Biomed.	2005	DBLP DOI BibTeX RDF
9	Wolfgang Nebel, Bärbel Mertsching, Birger Kollmeier	Digital Hearing Aids: Challenges and Solutions for Ultra Low Power.	PATMOS	2005	DBLP DOI BibTeX RDF
9	Tarek A. El-Ghazawi, Kris Gaj, Nikitas A. Alexandridis, Allen Michalski, Osman Devrim Fidanci, Mohamed Taher, Esam El-Araby, Esmail Chitalwala, Proshanta Saha	Reconfigurable computers: an empirical analysis (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
9	Mohamed Taher, Esam El-Araby, Tarek A. El-Ghazawi, Kris Gaj	Image processing library for reconfigurable computers (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
9	Somsubhra Mondal, Seda Ogrenci Memik, Debasish Das	Hierarchical LUT structures for leakage power reduction (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
9	Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers	Optimized Generation of Data-Path from C Codes for FPGAs.	DATE	2005	DBLP DOI BibTeX RDF
9	Artur Burchard, Ewa Hekstra-Nowacka, Atul Chauhan	A Real-Time Streaming Memory Controller.	DATE	2005	DBLP DOI BibTeX RDF
9	Jan Fischer, Dirk Bartz, Wolfgang Straßer	Reality Tooning: Fast Non-Photorealism for Augmented Video Streams.	ISMAR	2005	DBLP DOI BibTeX RDF
9	Panu Hämäläinen, Jari Heikkinen, Marko Hännikäinen, Timo D. Hämäläinen	Design of Transport Triggered Architecture Processors for Wireless Encryption.	DSD	2005	DBLP DOI BibTeX RDF
9	BoonPing Lim, Md. Safi Uddin	Statistical-Based SYN-Flooding Detection Using Programmable Network Processor.	ICITA (2)	2005	DBLP DOI BibTeX RDF	non-parametric CUSUM, token bucket filtering, network security, network processor, SYN-flooding
9	Fumihiko Ino, Manabu Matsui, Keigo Goda, Kenichi Hagihara	Performance Study of LU Decomposition on the Programmable GPU.	HiPC	2005	DBLP DOI BibTeX RDF