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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 1565 publication records. Showing 1565 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
15 | Diana Kalel, Jean-Christophe Brignone, Irene Serre, Julian Massicot, Jerome Avezou |
UPF-Aware CDC Structural Verification on RTL. |
NEWCAS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Prianka Sengupta, Aakash Tyagi, Yiran Chen 0001, Jiang Hu |
Early Identification of Timing Critical RTL Components using ML based Path Delay Prediction. |
MLCAD |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Daniela Sanchez Lopera, Ishwor Subedi, Wolfgang Ecker |
Using Graph Neural Networks for Timing Estimations of RTL Intermediate Representations. |
MLCAD |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Johannes Geier, Daniel Mueller-Gritschneder |
vRTLmod: An LLVM based Open-source Tool to Enable Fault Injection in Verilator RTL Simulations. |
CF |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Rakesh M. B., Pabitra Das, Anant Terkar, Amit Acharyya |
GRASPE: Accurate Post-Synthesis Power Estimation from RTL using Graph Representation Learning. |
ISCAS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Shubham Nema, Shiva Kaushik Chunduru, Charan Kodigal, Gwendolyn Voskuilen, Arun F. Rodrigues, K. Scott Hemmert, Ben Feinberg, Hyokeun Lee, Amro Awad, Clayton Hughes |
ERAS: A Flexible and Scalable Framework for Seamless Integration of RTL Models with Structural Simulation Toolkit. |
IISWC |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Mengxi Liu, Bo Zhou 0005, Zimin Zhao, Hyeonseok Hong, Hyun Kim, Sungho Suh, Vítor Fortes Rey, Paul Lukowicz |
FieldHAR: A Fully Integrated End-to-End RTL Framework for Human Activity Recognition with Neural Networks from Heterogeneous Sensors. |
ASAP |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Xinhui Lai, Maksim Jenihhin |
Analyzing Side-Channel Attack Vulnerabilities at RTL. |
LATS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Julian Höfer, Fabian Kempf, Tim Hotfilter, Fabian Kreß, Tanja Harbaum, Jürgen Becker 0001 |
SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators. |
ACM Great Lakes Symposium on VLSI |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Hussam Murad, Fatma Newagy, M. Watheq El-Kharashi |
Improved Dynamic Collision Recovery in Wireless Ad-Hoc Networks: System and RTL Modeling. |
ICCCNT |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Vinay Kumar, Bhrugurajsinh Chudasama, Bin B. W. Wang, Manish Arora, Bharath Shankaranarayanan |
Allocating Physically Aware Embedded Memory Test & Repair Processor using Floorplan Info at the RTL Design Level. |
VTS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Oussama Laouamri, Naveen Khanna, Jeff Mayer, Nilanjan Mukherjee |
A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy. |
ITC |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Rakesh M. B., Pabitra Das, Sai Pranav K. R, Amit Acharyya |
GRILAPE: Graph Representation Inductive Learning-based Average Power Estimation for Frontend ASIC RTL Designs. |
VLSID |
2023 |
DBLP DOI BibTeX RDF |
|
15 | José-Miguel Galeas-Merchán, José-Borja Castillo-Sánchez, Martín González-García |
Simplifying RTL design and verification in chip manufacturing: A paradigm for Electronics Teaching using Open-Source tools. |
DCIS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Wu Wang, Nan Zhang 0001, Cong Tian, Zhenhua Duan, Zhijie Xu, Chaofeng Yu |
Verifying Chips Design at RTL Level. |
TASE |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Haoyuan Wang, Scott Beamer |
RepCut: Superlinear Parallel RTL Simulation with Replication-Aided Partitioning. |
ASPLOS (3) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Kevin Laeufer, Vighnesh Iyer, David Biancolin, Jonathan Bachrach, Borivoje Nikolic, Koushik Sen |
Simulator Independent Coverage for RTL Hardware Languages. |
ASPLOS (3) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Mahyar Emami, Sahand Kashani, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus |
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism. |
ASPLOS (4) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Rongjian Liang, Nathaniel Ross Pinckney, Yuji Chai, Haoxin Ren, Brucek Khailany |
Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation. |
DAC |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Eric Ohana |
Optimizing Verification of RTL Designs Using Reinforcement Learning Methods. |
|
2023 |
RDF |
|
15 | Jie Xiao 0003, Qiou Ji, Qing Shen, Jianhui Jiang, Yujiao Huang, Jungang Lou |
Accelerating stochastic-based reliability estimation for combinational circuits at RTL using GPU parallel computing. |
Int. J. Intell. Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Dan Luo, Tun Li, Liqian Chen, Hongji Zou, Mingchuan Shi |
Grammar-based fuzz testing for microprocessor RTL design. |
Integr. |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Jooho Wang, Sungkyung Park 0001, Chester Sungchung Park |
Spatial Data Dependence Graph Based Pre-RTL Simulator for Convolutional Neural Network Dataflows. |
IEEE Access |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Daniela Sanchez Lopera, Lorenzo Servadei, Sebastian Siegfried Prebeck, Wolfgang Ecker |
Early RTL delay prediction using neural networks. |
Microprocess. Microsystems |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Jian Hu, Minhui Hu, Kuang Zhao, Yun Kang, Haitao Yang 0006, Jie Cheng |
A Hybrid Method for Equivalence Checking Between System Level and RTL. |
J. Circuits Syst. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Jiaji He, Haocheng Ma, Max Panoff, Hanning Wang, Yiqiang Zhao, Leibo Liu, Xiaolong Guo, Yier Jin |
Security Oriented Design Framework for EM Side-Channel Protection in RTL Implementations. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan 0001, Ramesh Karri, Brendan Dolan-Gavitt, Siddharth Garg |
Benchmarking Large Language Models for Automated Verilog RTL Code Generation. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Syed Asad Alam, David Gregg, Giulio Gambardella, Michael Preußer, Michaela Blott |
On the RTL Implementation of FINN Matrix Vector Compute Unit. |
CoRR |
2022 |
DBLP BibTeX RDF |
|
15 | Chih-Chyau Yang, Tian-Sheuan Chang |
Pre-RTL DNN Hardware Evaluator With Fused Layer Support. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Pervesh Kumar, Huo Yingge, Imran Ali, YoungGun Pu, Keum-Cheol Hwang, Youngoo Yang, Yeon-Jae Jung, Hyung-Ki Huh, Seok-Kee Kim, Joon-Mo Yoo, Kang-Yoon Lee |
A Configurable and Fully Synthesizable RTL-Based Convolutional Neural Network for Biosensor Applications. |
Sensors |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Anuradha Chathuranga Ranasinghe, Sabih H. Gerez |
Gate-Level RTL Description of the Glitch Optimized Multipliers. |
|
2022 |
DOI RDF |
|
15 | Sheikh Ariful Islam, Srinivas Katkoori |
Behavioral Synthesis of Key-Obfuscated RTL IP. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Farhath Zareen, Robert Karam |
A Framework for Detecting Hardware Trojans in RTL Using Artificial Immune Systems. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Parmida Vahdatniya, Amirali Sharifian, Reza Hojabr, Arrvindh Shriraman |
mu-grind: A Framework for Dynamically Instrumenting HLS-Generated RTL. |
PACT |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Hongji Zou, Mingchuan Shi, Tun Li, WanXia Qu |
Towards Implementing RTL Microprocessor Agile Design Using Feature Oriented Programming. |
DATE |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Yu Zeng, Aarti Gupta, Sharad Malik |
Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators. |
DATE |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Orlando Arias, Zhaoxiang Liu, Xiaolong Guo, Yier Jin, Shuo Wang 0003 |
RTSEC: Automated RTL Code Augmentation for Hardware Security Enhancement. |
DATE |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Ganapathy Parthasarathy, Aabid Rushdi, Parivesh Choudhary, Saurav Nanda, Malan Evans, Hansika Gunasekara, Sridhar Rajakumar |
RTL Regression Test Selection using Machine Learning. |
ASP-DAC |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Yue Xing 0001, Aarti Gupta, Sharad Malik |
Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models. |
ASP-DAC |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Hao Huang, Haihua Shen, Shan Li, Huawei Li 0001 |
A Hardware Trojan Trigger Localization Method in RTL based on Control Flow Features. |
ATS |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Flavien Solt, Ben Gras, Kaveh Razavi |
CellIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in RTL. |
USENIX Security Symposium |
2022 |
DBLP BibTeX RDF |
|
15 | Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang |
RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement. |
ISPD |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Daniele Paletti, Francesco Peverelli, Davide Conficconi |
Online Learning RTL Synthesis for Automated Design Space Exploration. |
IPDPS Workshops |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Qinhan Tan, Aarti Gupta, Sharad Malik |
Usage-Based RTL Subsetting for Hardware Accelerators. |
ICCAD |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Prianka Sengupta, Aakash Tyagi, Yiran Chen 0001, Jiang Hu |
How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning. |
ICCAD |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Daniela Sanchez Lopera, Wolfgang Ecker |
Applying GNNs to Timing Estimation at RTL. |
ICCAD |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Suriya Srinivasan, Ranga Vemuri |
Model Checking Leveraged Error Localization for Complex RTL Designs. |
ICCD |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Nayoung Kwon, Daejin Park |
Lightweighted Shallow CTS Techniques for Checking Clock Tree Synthesizable Paths in RTL Design Time. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Anantharaj Thalaimalai Vanaraj, Raja Sekar Kumaresan, Marshal Raj, G. Lakshminarayanan |
Optimal Test Sequences for Logic Verification closure in State Dependent RTL Digital designs. |
ICCCNT |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Ross Daly, Caleb Donovick, Jackson Melchert, Rajsekhar Setaluri, Nestan Tsiskaridze, Priyanka Raina, Clark W. Barrett, Pat Hanrahan |
Synthesizing Instruction Selection Rewrite Rules from RTL using SMT. |
FMCAD |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Jerin Joe, Nilanjan Mukherjee 0001, Irith Pomeranz, Janusz Rajski |
Test Generation for an Iterative Design Flow with RTL Changes. |
ITC |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Xiaochen Li, Ruilian Zhao, Ying Shang |
EFSM Model Construction Method for RTL Digital Circuit. |
DSA |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Laurence Pierre |
Refinement rules for the automatic TLM-to-RTL conversion of temporal assertions. |
Integr. |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Christian Pilato, Animesh Basak Chowdhury, Donatella Sciuto, Siddharth Garg, Ramesh Karri |
ASSURE: RTL Locking Against an Untrusted Foundry. |
IEEE Trans. Very Large Scale Integr. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Mateus G. Silva, Guilherme L. Silvano, Ricardo O. Duarte |
RTL development of a parameterizable Reed-Solomon Codec. |
IET Comput. Digit. Tech. |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Yangdi Lyu, Prabhat Mishra 0001 |
Scalable Concolic Testing of RTL Models. |
IEEE Trans. Computers |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Jian Hu, Yongyang Hu, Qi Lv, Wentao Wang, Guanwu Wang, Guilin Chen, Kang Wang, Yun Kang, Haitao Yang 0006 |
A Path-Based Equivalence Checking Method Between System Level and RTL Descriptions Using Machine Learning. |
J. Circuits Syst. Comput. |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Alex Vidal-Obiols, Jordi Cortadella, Jordi Petit, Marc Galceran Oms, Ferran Martorell |
Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Yehya Nasser, Jordane Lorandel, Jean-Christophe Prévotet, Maryline Hélard |
RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Johan Laurent, Christophe Deleuze, Florian Pebay-Peyroula, Vincent Beroulle |
Bridging the Gap between RTL and Software Fault Injection. |
ACM J. Emerg. Technol. Comput. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Sheikh Ariful Islam, Love Kumar Sah, Srinivas Katkoori |
High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging. |
ACM Trans. Design Autom. Electr. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Hasini Witharana, Yangdi Lyu, Prabhat Mishra 0001 |
Directed Test Generation for Activation of Security Assertions in RTL Models. |
ACM Trans. Design Autom. Electr. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer 0001 |
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
15 | Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, Margaret Martonosi |
AutoSVA: Democratizing Formal Verification of RTL Module Interactions. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
15 | Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz |
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
15 | Haoyi Wang, Yici Cai, Qiang Zhou 0001 |
A game theory approach for RTL security verification resources allocation. |
CCF Trans. High Perform. Comput. |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Adham Osama, Ahmed Mostafa, Eslam Mamdouh, Mohamed Gamal, Usama Imam, Mohamed Taha, Ahmed H. Khalil, Islam Ahmed, Hassan Mostafa |
Fast RTL Implementation of A* Path Planning Algorithm. |
ICM |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Eiji Yoshiya, Tomoya Nakanishi, Tsuyoshi Isshiki |
RTL Design Framework for Embedded Processor by using C++ Description. |
DATE |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Yao Hsiao, Dominic P. Mulligan, Nikos Nikoleris, Gustavo Petri, Caroline Trippel |
Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations. |
MICRO |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Hyuk-Je Kwon, Myeong-Hoon Oh, Won-Ok Kwon |
Verification of Interconnect RTL Code for Memory-Centric Computing using UVM. |
ICEIC |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Swetha Varadarajulu, K. Mariammal |
Design of SentiNet RTL Library for CNN based Hardware Accelerator. |
ICCCSP |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Frederique van Leeuwen, Bas Bosma, Arjan van den Born, Eric Postma |
RTL: A Robust Time Series Labeling Algorithm. |
IDA |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Yu Zeng, Bo-Yuan Huang 0001, Hongce Zhang, Aarti Gupta, Sharad Malik |
Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables. |
ICCAD |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Daniela Sanchez Lopera, Lorenzo Servadei, Vishwa Priyanka Kasi, Sebastian Siegfried Prebeck, Wolfgang Ecker |
RTL Delay Prediction Using Neural Networks. |
NorCAS |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Kazuki Furukawa, Ryohei Kobayashi, Tomoya Yokono, Norihisa Fujita, Yoshiki Yamaguchi, Taisuke Boku, Kohji Yoshikawa, Masayuki Umemura |
An efficient RTL buffering scheme for an FPGA-accelerated simulation of diffuse radiative transfer. |
FPT |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Jizhong Yang, Ying Zhang, Yifeng Hua, Jiaqi Yao, Zhiming Mao, Xin Chen |
Hardware Trojans Detection Through RTL Features Extraction and Machine Learning. |
AsianHOST |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Tun Li, Hongji Zou, Dan Luo, WanXia Qu |
Symbolic Simulation Enhanced Coverage-Directed Fuzz Testing of RTL Design. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Jisu Kwon, Sejong Oh, Daejin Park |
Metamorphic Edge Processor Simulation Framework Using Flexible Runtime Partial Replacement of Software-Embedded Verilog RTL Models. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Chih-Chyau Yang, Tian-Sheuan Chang |
Pre-RTL DNN Hardware Evaluator With Fused Layer Support. |
ISOCC |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Serge Leef |
Algorithm to Architecture to RTL to GDSII: Incorporating Security into All Phases of SoC Design and Implementation Flow - Keynote. |
VTS |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Mertcan Temel, Warren A. Hunt |
Sound and Automated Verification of Real-World RTL Multipliers. |
FMCAD |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Nimisha Limaye, Animesh Basak Chowdhury, Christian Pilato, Mohammed Thari Nabeel, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri |
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks. |
DAC |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Sadullah Canakci, Leila Delshadtehrani, Furkan Eris, Michael Bedford Taylor, Manuel Egele, Ajay Joshi |
DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing. |
DAC |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, Margaret Martonosi |
AutoSVA: Democratizing Formal Verification of RTL Module Interactions. |
DAC |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Tao Zhang, Jungmin Park, Mark M. Tehranipoor, Farimah Farahmandi |
PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation. |
DAC |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Scott Beamer |
A Case for Accelerating Software RTL Simulation. |
IEEE Micro |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Moon Gi Seok, Hessam S. Sarjoughian, Changbeom Choi, Daejin Park |
Fast and Cycle-Accurate Simulation of RTL NoC Designs Using Test-Driven Cellular Automata. |
IEEE Access |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Cristian Andy Tanase |
Dynamic scheduler implementation used for load distribution between hardware accelerators (RTL) and software tasks (CPU) in heterogeneous systems. |
J. Supercomput. |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Sheikh Ariful Islam, Love Kumar Sah, Srinivas Katkoori |
A Framework for Hardware Trojan Vulnerability Estimation and Localization in RTL Designs. |
J. Hardw. Syst. Secur. |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Rahul S. Bhatt, Shweta Sharma, Shyam A |
Automated RTL Generator for Optimized Flop Repeater Network. |
EAI Endorsed Trans. Cloud Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Tobias Ludwig 0002, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz |
Properties First - Correct-By-Construction RTL Design in System-Level Design Flows. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Debjit Pal, Spencer Offenberger, Shobha Vasudevan |
Assertion Ranking Using RTL Source Code Analysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Shilpa Pendyala, Sheikh Ariful Islam, Srinivas Katkoori |
Interval Arithmetic and Self-Similarity Based RTL Input Vector Control for Datapath Leakage Minimization. |
ACM Trans. Design Autom. Electr. Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Christian Pilato, Animesh Basak Chowdhury, Donatella Sciuto, Siddharth Garg, Ramesh Karri |
ASSURE: RTL Locking Against an Untrusted Foundry. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
15 | David M. Russinoff |
Formal Verification of Arithmetic RTL: Translating Verilog to C++ to ACL2. |
ACL2 |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Sheikh Ariful Islam, Love Kumar Sah, Srinivas Katkoori |
DLockout: A Design Lockout Technique for Key Obfuscated RTL IP Designs. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
15 | Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul |
Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
15 | Sheikh Ariful Islam, Love Kumar Sah, Srinivas Katkoori |
Analytical Estimation and Localization of Hardware Trojan Vulnerability in RTL Designs. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
15 | Shan Cao, Wei Deng, Zhenyi Bao, Chengbo Xue, Shugong Xu, Shunqing Zhang |
SimuNN: A Pre-RTL Inference, Simulation and Evaluation Framework for Neural Networks. |
IEEE J. Emerg. Sel. Topics Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier |
Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems. |
DDECS |
2020 |
DBLP DOI BibTeX RDF |
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