Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Erkan Diken, Rosilde Corvino, Lech Józwiak |
Rapid and accurate energy estimation of vector processing in VLIW ASIPs. |
MECO |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Vasileios Porpodas, Marcelo Cintra |
CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors. |
CASES |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Xuemeng Zhang, Hui Wu 0001, Haiyan Sun |
Register Allocation by Incremental Graph Colouring for Clustered VLIW Processors. |
TrustCom/ISPA/IUCC |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Vasileios Porpodas, Marcelo Cintra |
Aligned Scheduling: Cache-Efficient Instruction Scheduling for VLIW Processors. |
LCPC |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Huan Ying, Hao Zhu, Zhiyuan Xue, Donghui Wang, Chaohuan Hou |
A Delay Slot Scheduling Framework for VLIW Architectures in Assembly-Level. |
DASC |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Abbas Rahimi, Luca Benini, Rajesh K. Gupta 0001 |
Aging-aware compiler-directed VLIW assignment for GPGPU architectures. |
DAC |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Manoj Gupta 0001 |
Improving multithreading performance for clustered VLIW architectures. |
|
2013 |
RDF |
|
16 | Fakhar Anjam |
Run-time Adaptable VLIW Processors: Resources, Performance, Power Consumption, and Reliability Trade-offs. |
|
2013 |
RDF |
|
16 | Xuemeng Zhang |
A unified approach to instruction scheduling and register allocation on clustered VLIW processors. |
|
2013 |
RDF |
|
16 | Eric J. Stotzer, Ernst L. Leiss |
Co-design of Compiler and Hardware Techniques to Reduce Program Code Size on a VLIW Processor. |
CLEI Electron. J. |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Chi-Bang Kuan, Jenq Kuen Lee |
Compiler supports for VLIW DSP processors with SIMD intrinsics. |
Concurr. Comput. Pract. Exp. |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Chung-Ju Wu, Yu-Te Lin, Jenq Kuen Lee |
Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files. |
J. Supercomput. |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Fadi Abboud, Yosi Ben-Asher, Yousef Shajrawi, Esti Stein |
Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic Operations. |
Int. J. Parallel Program. |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Rahul Nagpal, Y. N. Srikant |
Compiler-assisted energy optimization for clustered VLIW processors. |
J. Parallel Distributed Comput. |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Madhura Purnaprajna, Paolo Ienne |
Making wide-issue VLIW processors viable on FPGAs. |
ACM Trans. Archit. Code Optim. |
2012 |
DBLP DOI BibTeX RDF |
|
16 | David Stevens, Vassilios A. Chouliaras, Vicente Azorin-Peris, Jia Zheng, Angelos Echiadis, Sijung Hu |
BioThreads: A Novel VLIW-Based Chip Multiprocessor for Accelerating Biomedical Image Processing Applications. |
IEEE Trans. Biomed. Circuits Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yang Xu, Hu He, Zhizhong Tang |
Energy Consumption Optimized Scheduling Algorithm for Clustered VLIW Architectures. |
J. Low Power Electron. |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Xu Yang 0003, Hu He 0001 |
An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems. |
Sensors |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yazhi Huang, Mengying Zhao, Chun Jason Xue |
WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture. |
LCTES |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Fakhar Anjam, Stephan Wong, Luigi Carro, Gabriel L. Nazar, Mateus B. Rutzig |
Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor. |
ICSAMOS |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Luca Sterpone, Matteo Sonza Reorda |
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors. |
VLSI-SoC (Selected Papers) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
On the optimized generation of Software-Based Self-Test programs for VLIW processors. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
A new SBST algorithm for testing the register file of VLIW processors. |
DATE |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Roel Jordans, Rosilde Corvino, Lech Józwiak |
Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors. |
DSD |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Jeremy Abramson, Pedro C. Diniz |
Resiliency-aware Scheduling for reconfigurable VLIW processors. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yi He 0008, Maolin Guan, Chunyuan Zhang, Tian Tian, Qianming Yang |
Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression. |
HPCC-ICESS |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Mark Milward, David Stevens, Vassilios A. Chouliaras |
Embedded UML design flow to the configurable LE1 MultiCore VLIW processor. |
ReCoSoC |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Stefan Hauser, Nico Moser, Ben H. H. Juurlink |
SynZEN: A hybrid TTA/VLIW architecture with a distributed register file. |
NORCHIP |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yaohua Wang, Shuming Chen, Kai Zhang 0023, Hu Chen, Xiaowen Chen |
Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes. |
IPDPS Workshops |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Jongwon Lee, Jonghee M. Youn, Jihoon Lee, Minwook Ahn, Yunheung Paek |
Dynamic Operands Insertion for VLIW Architecture with a Reduced Bit-width Instruction Set. |
IPDPS |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Luc Michel, Nicolas Fournel, Frédéric Pétrot |
Fast simulation of systems embedding VLIW processors. |
CODES+ISSS |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Vasileios Porpodas, Marcelo Cintra |
UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores. |
LCPC |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Claude-Pierre Jeannerod, Jingyan Jourdan-Lu |
Simultaneous Floating-Point Sine and Cosine for VLIW Integer Processors. |
ASAP |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Alireza Rohani, Hans G. Kerkhoff |
An on-line soft error mitigation technique for control logic of VLIW processors. |
DFT |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
On the development of Software-Based Self-Test methods for VLIW processors. |
DFT |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui |
Energy-aware SA-based instruction scheduling for fine-grained power-gated VLIW processors. |
ISOCC |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Matthew Doerksen, Parimala Thulasiraman, Ruppa K. Thulasiram |
Optimizing Option Pricing Algorithms and Profiling Power Consumption on VLIW APU Architecture. |
ISPA |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yonghua Hu, Shuming Chen, Jie Huang |
Preprocessing Scheme of Intelligent Assembly for a High Performance VLIW DSP. |
CGC |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yangzhao Yang, Zeng Zhao, Naijie Gu |
DFG-base Dynamic Operation Partitioning for Heterogeneous Multicluster VLIW DSP Processor. |
CLUSTER |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Xiaoyan Jia |
Indirect code generation for VLIW architectures and a hardware optimization algorithm. |
|
2012 |
RDF |
|
16 | Joseph A. Fisher, Paolo Faraboschi, Cliff Young |
VLIW Processors. |
Encyclopedia of Parallel Computing |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Che-Wei Lin, Chang Hong Lin, Wei Jhih Wang |
A power-aware code-compression design for RISC/VLIW architecture. |
J. Zhejiang Univ. Sci. C |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Yong Guan, Jingling Xue |
Leakage-Aware Modulo Scheduling for Embedded VLIW Processors. |
J. Comput. Sci. Technol. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Yuanwu Lei, Yong Dou, Jie Zhou 0007 |
FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic. |
IEICE Trans. Inf. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Rahul Nagpal, Y. N. Srikant |
Compiler-assisted power optimization for clustered VLIW architectures. |
Parallel Comput. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Sid Ahmed Ali Touati, Frederic Brault, Karine Deschinkel, Benoît Dupont de Dinechin |
Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors. |
ACM Trans. Embed. Comput. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Shorin Kyo, Shin'ichiro Okazaki |
IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements. |
J. Signal Process. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Luca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda |
Fault injection analysis of transient faults in clustered VLIW processors. |
DDECS |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Markus Ulbricht 0002, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus |
A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors. |
DDECS |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Christian Bernard, Fabien Clermidy |
A low-power VLIW processor for 3GPP-LTE complex numbers processing. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Nayan V. Mujadiya |
Instruction Scheduling on Variable Latency Functional Units of VLIW Processors. |
ISED |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui, Praveen Raghavan, Francky Catthoor |
An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Vassilios A. Chouliaras, George Lentaris, Dionisios I. Reisis, David Stevens |
Customizing a VLIW Chip Multiprocessor for Motion Estimation Algorithms. |
ARCS Workshops |
2011 |
DBLP BibTeX RDF |
|
16 | Yuanwu Lei, Yong Dou, Jie Zhou 0007, Sufeng Wang |
VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic. |
FPL |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Timothy Anderson, Duc Bui, Shriram Moharil, Soujanya Narnur, Mujibur Rahman, Anthony Lell, Eric Biscondi, Ashish Shrivastava, Peter Dent, Mingjian Yan, Hasan Mahmood |
A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS. |
IEEE Symposium on Computer Arithmetic |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Nachiket Kapre, André DeHon |
VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration. |
FPT |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Xuemeng Zhang, Hui Wu 0001, Jingling Xue |
An efficient heuristic for instruction scheduling on clustered vliw processors. |
CASES |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Yuanwu Lei, Yong Dou, Li Shen, Jie Zhou 0007, Song Guo 0003 |
Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Francesco Menichelli, Mauro Olivieri, Simone Smorfa |
Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Xiaoyan Jia, Gerhard P. Fettweis |
Integration of code optimization and hardware exploration for a VLIW architecture by using fuzzy control system. |
SoCC |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Vincent Brost, Charles Meunier, Debyo Saptono, Fan Yang 0019 |
Flexible VLIW processor based on FPGA for real-time image processing. |
DASIP |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Lidan Bao, Hongmei Wang, Tiejun Zhang, Donghui Wang, Chaohuan Hou |
Improvement on branch scheduling for VLIW architecture. |
ASICON |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Mario Schölzel |
Fine-Grained Software-Based Self-Repair of VLIW Processors. |
DFT |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Hsien-Ching Hsieh, Shui-An Wen, Che-Yu Liao, Huang-Lun Lin, Po-Han Huang, Shing-Wu Tung |
Low power design and dynamic power management system for VLIW DSP subsystem. |
ISPACS |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Guillermo Payá Vayá |
Design and analysis of a generic VLIW processor for multimedia applications. |
|
2011 |
RDF |
|
16 | Thorsten Jungeblut |
Entwurfsraumexploration ressourceneffizienter VLIW-Prozessoren. |
|
2011 |
RDF |
|
16 | Jui-Chun Chen, Chang Hong Lin |
Improved Dictionary-Based Code-Compression Schemes with XOR Reference for RISC/VLIW Architecture. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Jih-Ching Chiu, Kai-Ming Yang |
A Novel instruction stream buffer for VLIW architectures. |
Comput. Electr. Eng. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Yung-Yuan Chen, Kuen-Long Leu |
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment. |
Microprocess. Microsystems |
2010 |
DBLP DOI BibTeX RDF |
|
16 | D. S. Ivanov |
Register allocation with instruction scheduling for VLIW-architectures. |
Program. Comput. Softw. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch |
A Multi-Shared Register File Structure for VLIW Processors. |
J. Signal Process. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Meng Wang 0005, Yi Wang 0003, Duo Liu, Zhiwei Qin 0004, Zili Shao |
Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processors. |
J. Syst. Softw. |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Christoph W. Kessler |
Compiling for VLIW DSPs. |
Handbook of Signal Processing Systems |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Tobias Koal, Heinrich Theodor Vierhaus |
A software-based self-test and hardware reconfiguration solution for VLIW processors. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
16 | David Stevens, Vassilios A. Chouliaras |
LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Meng-Hsuan Cheng, Kenn Slagter, Tai-Wen Lung, Yeh-Ching Chung |
A VLIW-Based Post Compilation Framework for Multimedia Embedded DSPs with Hardware Specific Optimizations. |
MTPP |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Stephan Wong, Fakhar Anjam, Faisal Nadeem |
Dynamically reconfigurable register file for a softcore VLIW processor. |
DATE |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Jimmy Bahuleyan, Rahul Nagpal, Y. N. Srikant |
Integrated energy-aware cyclic and acyclic scheduling for clustered VLIW processors. |
IPDPS Workshops |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Manoj Gupta 0001, Fermín Sánchez, Josep Llosa |
A low cost split-issue technique to improve performance of SMT clustered VLIW processors. |
IPDPS |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Fakhar Anjam, Stephan Wong, Faisal Nadeem |
A shared reconfigurable VLIW multiprocessor system. |
IPDPS Workshops |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Fakhar Anjam, Stephan Wong, Faisal Nadeem |
A multiported register file with register renaming for configurable softcore VLIW processors. |
FPT |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Fakhar Anjam, Muhammad Faisal Nadeem, Stephan Wong |
A VLIW softcore processor with dynamically adjustable issue-slots. |
FPT |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Claude-Pierre Jeannerod, Christophe Mouilleron, Jean-Michel Muller, Guillaume Revy, Christian Bertin, Jingyan Jourdan-Lu, Herve Knochel, Christophe Monat |
Techniques and tools for implementing IEEE 754 floating-point arithmetic on VLIW integer processors. |
PASCO |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Guillermo Payá Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch |
A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures. |
ASAP |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Che-Wei Lin, Chang Hong Lin |
A Power-saving Code-compression Design for the VLIW Embedded Systems. |
ESA |
2010 |
DBLP BibTeX RDF |
|
16 | Chengpin Tseng, Chiuyun Hung, De-Sheng Chen, Kuei-Chung Chang, Yiwen Wang 0003 |
Application Specific Instruction Set Exploration on VLIW Architectures. |
ESA |
2010 |
DBLP BibTeX RDF |
|
16 | Chia-Han Lu, Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee |
LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files. |
Concurr. Comput. Pract. Exp. |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Takahisa Wada, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Takashi Miyamori, Masaki Nakagawa |
A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
16 | C. Bruel |
If-conversion for embedded VLIW architectures. |
Int. J. Embed. Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Ya-Shuai Lü, Li Shen 0007, Libo Huang, Zhiying Wang 0003, Nong Xiao |
Optimal subgraph covering for customisable VLIW processors. |
IET Comput. Digit. Tech. |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Nayan V. Mujadiya |
Instruction scheduling for VLIW processors under variation scenario. |
ICSAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Zheng Shen, Hu He 0001, Yihe Sun |
Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
16 | David Stevens, Nick Glynn, Panagiotis Galiatsatos, Vassilios A. Chouliaras, Dionysios I. Reisis |
Evaluating the performance of a configurable, extensible VLIW processor in FFT execution. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Vassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis |
A configurable length, Fused Multiply-Add floating point unit for a VLIW processor. |
SoCC |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Manoj Gupta 0001, Fermín Sánchez, Josep Llosa |
Thread Merging Schemes for Multithreaded Clustered VLIW Processors. |
ICPP |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Guillermo Payá Vayá, Javier Martín-Langerwerf, Florian Giesemann, Holger Blume, Peter Pirsch |
Instruction merging to increase parallelism in VLIW architectures. |
SoC |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Mattias V. Eriksson, Christoph W. Kessler |
Integrated Modulo Scheduling for Clustered VLIW Architectures. |
HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Guillermo Talavera |
Scratchpad-oriented address generation for low-power embedded VLIW processors. |
|
2009 |
RDF |
|
16 | David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo |
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. |
Integr. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero |
Power-efficient VLIW design using clustering and widening. |
Int. J. Embed. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|