Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Erkan Diken, Rosilde Corvino, Lech Józwiak |
Rapid and accurate energy estimation of vector processing in VLIW ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 2nd Mediterranean Conference on Embedded Computing, MECO 2013, Budva, Montenegro, June 15-20, 2013, pp. 33-37, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Vasileios Porpodas, Marcelo Cintra |
CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013, Montreal, QC, Canada, September 29 - October 4, 2013, pp. 9:1-9:10, 2013, IEEE, 978-1-4799-1400-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Xuemeng Zhang, Hui Wu 0001, Haiyan Sun |
Register Allocation by Incremental Graph Colouring for Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TrustCom/ISPA/IUCC ![In: 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2013 / 11th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA-13 / 12th IEEE International Conference on Ubiquitous Computing and Communications, IUCC-2013, Melbourne, Australia, July 16-18, 2013, pp. 927-934, 2013, IEEE Computer Society, 978-0-7695-5022-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Vasileios Porpodas, Marcelo Cintra |
Aligned Scheduling: Cache-Efficient Instruction Scheduling for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing - 26th International Workshop, LCPC 2013, San Jose, CA, USA, September 25-27, 2013. Revised Selected Papers, pp. 275-291, 2013, Springer, 978-3-319-09966-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Huan Ying, Hao Zhu, Zhiyuan Xue, Donghui Wang, Chaohuan Hou |
A Delay Slot Scheduling Framework for VLIW Architectures in Assembly-Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASC ![In: IEEE 11th International Conference on Dependable, Autonomic and Secure Computing, DASC 2013, Chengdu, China, December 21-22, 2013, pp. 231-234, 2013, IEEE Computer Society, 978-1-4799-3380-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Abbas Rahimi, Luca Benini, Rajesh K. Gupta 0001 |
Aging-aware compiler-directed VLIW assignment for GPGPU architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013, pp. 16:1-16:6, 2013, ACM, 978-1-4503-2071-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Manoj Gupta 0001 |
Improving multithreading performance for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2013 |
RDF |
|
16 | Fakhar Anjam |
Run-time Adaptable VLIW Processors: Resources, Performance, Power Consumption, and Reliability Trade-offs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2013 |
RDF |
|
16 | Xuemeng Zhang |
A unified approach to instruction scheduling and register allocation on clustered VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2013 |
RDF |
|
16 | Eric J. Stotzer, Ernst L. Leiss |
Co-design of Compiler and Hardware Techniques to Reduce Program Code Size on a VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLEI Electron. J. ![In: CLEI Electron. J. 15(2), 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Chi-Bang Kuan, Jenq Kuen Lee |
Compiler supports for VLIW DSP processors with SIMD intrinsics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 24(5), pp. 517-532, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Chung-Ju Wu, Yu-Te Lin, Jenq Kuen Lee |
Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 61(3), pp. 1024-1047, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Fadi Abboud, Yosi Ben-Asher, Yousef Shajrawi, Esti Stein |
Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 40(5), pp. 488-513, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Rahul Nagpal, Y. N. Srikant |
Compiler-assisted energy optimization for clustered VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 72(8), pp. 944-959, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Madhura Purnaprajna, Paolo Ienne |
Making wide-issue VLIW processors viable on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 8(4), pp. 33:1-33:16, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | David Stevens, Vassilios A. Chouliaras, Vicente Azorin-Peris, Jia Zheng, Angelos Echiadis, Sijung Hu |
BioThreads: A Novel VLIW-Based Chip Multiprocessor for Accelerating Biomedical Image Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 6(3), pp. 257-268, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yang Xu, Hu He, Zhizhong Tang |
Energy Consumption Optimized Scheduling Algorithm for Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 8(2), pp. 146-157, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Xu Yang 0003, Hu He 0001 |
An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 12(4), pp. 4466-4478, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yazhi Huang, Mengying Zhao, Chun Jason Xue |
WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2012, LCTES '12, Beijing, China - June 12 - 13, 2012, pp. 31-40, 2012, ACM, 978-1-4503-1212-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Fakhar Anjam, Stephan Wong, Luigi Carro, Gabriel L. Nazar, Mateus B. Rutzig |
Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: 2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XII, Samos, Greece, July 16-19, 2012, pp. 183-192, 2012, IEEE, 978-1-4673-2295-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Luca Sterpone, Matteo Sonza Reorda |
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC (Selected Papers) ![In: VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers, pp. 162-180, 2012, Springer, 978-3-642-45072-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
On the optimized generation of Software-Based Self-Test programs for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, pp. 129-134, 2012, IEEE, 978-1-4673-2657-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
A new SBST algorithm for testing the register file of VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, pp. 412-417, 2012, IEEE, 978-1-4577-2145-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Roel Jordans, Rosilde Corvino, Lech Józwiak |
Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 15th Euromicro Conference on Digital System Design, DSD 2012, Cesme, Izmir, Turkey, September 5-8, 2012, pp. 152-155, 2012, IEEE Computer Society, 978-1-4673-2498-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Jeremy Abramson, Pedro C. Diniz |
Resiliency-aware Scheduling for reconfigurable VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012, Cancun, Mexico, December 5-7, 2012, pp. 1-7, 2012, IEEE, 978-1-4673-2919-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yi He 0008, Maolin Guan, Chunyuan Zhang, Tian Tian, Qianming Yang |
Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC-ICESS ![In: 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, HPCC-ICESS 2012, Liverpool, United Kingdom, June 25-27, 2012, pp. 25-32, 2012, IEEE Computer Society, 978-1-4673-2164-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Mark Milward, David Stevens, Vassilios A. Chouliaras |
Embedded UML design flow to the configurable LE1 MultiCore VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), York, United Kingdom, July 9-11, 2012, pp. 1-8, 2012, IEEE, 978-1-4673-2570-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Stefan Hauser, Nico Moser, Ben H. H. Juurlink |
SynZEN: A hybrid TTA/VLIW architecture with a distributed register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, pp. 1-4, 2012, IEEE, 978-1-4673-2221-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yaohua Wang, Shuming Chen, Kai Zhang 0023, Hu Chen, Xiaowen Chen |
Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012, pp. 1649-1658, 2012, IEEE Computer Society, 978-1-4673-0974-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Jongwon Lee, Jonghee M. Youn, Jihoon Lee, Minwook Ahn, Yunheung Paek |
Dynamic Operands Insertion for VLIW Architecture with a Reduced Bit-width Instruction Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 26th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2012, Shanghai, China, May 21-25, 2012, pp. 119-130, 2012, IEEE Computer Society, 978-1-4673-0975-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Luc Michel, Nicolas Fournel, Frédéric Pétrot |
Fast simulation of systems embedding VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2012, part of ESWeek '12 Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012, pp. 143-150, 2012, ACM, 978-1-4503-1426-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Vasileios Porpodas, Marcelo Cintra |
UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 25th International Workshop, LCPC 2012, Tokyo, Japan, September 11-13, 2012, Revised Selected Papers, pp. 127-142, 2012, Springer, 978-3-642-37657-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Claude-Pierre Jeannerod, Jingyan Jourdan-Lu |
Simultaneous Floating-Point Sine and Cosine for VLIW Integer Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 23rd IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012, Delft, The Netherlands, July 9-11, 2012, pp. 69-76, 2012, IEEE Computer Society, 978-1-4673-2243-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Alireza Rohani, Hans G. Kerkhoff |
An on-line soft error mitigation technique for control logic of VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, pp. 85-91, 2012, IEEE Computer Society, 978-1-4673-3043-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
On the development of Software-Based Self-Test methods for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, pp. 25-30, 2012, IEEE Computer Society, 978-1-4673-3043-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui |
Energy-aware SA-based instruction scheduling for fine-grained power-gated VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012, pp. 139-142, 2012, IEEE, 978-1-4673-2989-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Matthew Doerksen, Parimala Thulasiraman, Ruppa K. Thulasiram |
Optimizing Option Pricing Algorithms and Profiling Power Consumption on VLIW APU Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012, Leganes, Madrid, Spain, July 10-13, 2012, pp. 71-78, 2012, IEEE Computer Society, 978-1-4673-1631-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yonghua Hu, Shuming Chen, Jie Huang |
Preprocessing Scheme of Intelligent Assembly for a High Performance VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGC ![In: 2012 Second International Conference on Cloud and Green Computing, CGC 2012, Xiangtan, Hunan, China, November 1-3, 2012, pp. 187-190, 2012, IEEE Computer Society, 978-1-4673-3027-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yangzhao Yang, Zeng Zhao, Naijie Gu |
DFG-base Dynamic Operation Partitioning for Heterogeneous Multicluster VLIW DSP Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2012 IEEE International Conference on Cluster Computing, CLUSTER 2012, Beijing, China, September 24-28, 2012, pp. 557-561, 2012, IEEE Computer Society, 978-1-4673-2422-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Xiaoyan Jia |
Indirect code generation for VLIW architectures and a hardware optimization algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2012 |
RDF |
|
16 | Joseph A. Fisher, Paolo Faraboschi, Cliff Young |
VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Parallel Computing ![In: Encyclopedia of Parallel Computing, pp. 2135-2142, 2011, Springer, 978-0-387-09765-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Che-Wei Lin, Chang Hong Lin, Wei Jhih Wang |
A power-aware code-compression design for RISC/VLIW architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Zhejiang Univ. Sci. C ![In: J. Zhejiang Univ. Sci. C 12(8), pp. 629-637, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Yong Guan, Jingling Xue |
Leakage-Aware Modulo Scheduling for Embedded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 26(3), pp. 405-417, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Yuanwu Lei, Yong Dou, Jie Zhou 0007 |
FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 94-D(11), pp. 2173-2183, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Rahul Nagpal, Y. N. Srikant |
Compiler-assisted power optimization for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Comput. ![In: Parallel Comput. 37(1), pp. 42-59, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Sid Ahmed Ali Touati, Frederic Brault, Karine Deschinkel, Benoît Dupont de Dinechin |
Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 10(4), pp. 47:1-47:25, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Shorin Kyo, Shin'ichiro Okazaki |
IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 62(1), pp. 5-16, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Luca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda |
Fault injection analysis of transient faults in clustered VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, pp. 207-212, 2011, IEEE Computer Society, 978-1-4244-9755-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Markus Ulbricht 0002, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus |
A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, pp. 143-146, 2011, IEEE Computer Society, 978-1-4244-9755-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Christian Bernard, Fabien Clermidy |
A low-power VLIW processor for 3GPP-LTE complex numbers processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 234-239, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Nayan V. Mujadiya |
Instruction Scheduling on Variable Latency Functional Units of VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: International Symposium on Electronic System Design, ISED 2011, Kochi, Kerala, India, December 19-21, 2011, pp. 307-312, 2011, IEEE Computer Society, 978-1-4577-1880-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui, Praveen Raghavan, Francky Catthoor |
An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, pp. 693-700, 2011, IEEE Computer Society, 978-1-4577-1048-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Vassilios A. Chouliaras, George Lentaris, Dionisios I. Reisis, David Stevens |
Customizing a VLIW Chip Multiprocessor for Motion Estimation Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS Workshops ![In: ARCS 2011 - 24th International Conference on Architecture of Computing Systems 2011, Workshop Proceedings, February 22-23, 2011, Como, Italy., 2011, VDE-Verlag, 978-3-8007-3333-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
16 | Yuanwu Lei, Yong Dou, Jie Zhou 0007, Sufeng Wang |
VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 252-257, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Timothy Anderson, Duc Bui, Shriram Moharil, Soujanya Narnur, Mujibur Rahman, Anthony Lell, Eric Biscondi, Ashish Shrivastava, Peter Dent, Mingjian Yan, Hasan Mahmood |
A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 20th IEEE Symposium on Computer Arithmetic, ARITH 2011, Tübingen, Germany, 25-27 July 2011, pp. 82-86, 2011, IEEE Computer Society, 978-0-7695-4318-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Nachiket Kapre, André DeHon |
VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, December 12-14, 2011, pp. 1-9, 2011, IEEE, 978-1-4577-1741-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Xuemeng Zhang, Hui Wu 0001, Jingling Xue |
An efficient heuristic for instruction scheduling on clustered vliw processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 14th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2011, part of the Seventh Embedded Systems Week, ESWeek 2011, Taipei, Taiwan, October 9-14, 2011, pp. 35-44, 2011, ACM, 978-1-4503-0713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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16 | Yuanwu Lei, Yong Dou, Li Shen, Jie Zhou 0007, Song Guo 0003 |
Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011, pp. 219-225, 2011, IEEE Computer Society, 978-1-4577-1953-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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16 | Francesco Menichelli, Mauro Olivieri, Simone Smorfa |
Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 1483-1486, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Xiaoyan Jia, Gerhard P. Fettweis |
Integration of code optimization and hardware exploration for a VLIW architecture by using fuzzy control system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011, pp. 36-41, 2011, IEEE, 978-1-4577-1616-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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16 | Vincent Brost, Charles Meunier, Debyo Saptono, Fan Yang 0019 |
Flexible VLIW processor based on FPGA for real-time image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASIP ![In: 2011 Conference on Design and Architectures for Signal and Image Processing, DASIP 2011, Tampere, Finland, November 2-4, 2011, pp. 59-66, 2011, IEEE, 978-1-4577-0620-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Lidan Bao, Hongmei Wang, Tiejun Zhang, Donghui Wang, Chaohuan Hou |
Improvement on branch scheduling for VLIW architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 723-726, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Mario Schölzel |
Fine-Grained Software-Based Self-Repair of VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 41-49, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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16 | Hsien-Ching Hsieh, Shui-An Wen, Che-Yu Liao, Huang-Lun Lin, Po-Han Huang, Shing-Wu Tung |
Low power design and dynamic power management system for VLIW DSP subsystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: International Symposium on Intelligent Signal Processing and Communications Systems, ISPACS 2011, Chiang Mai, Thailand, December 7-9, 2011, pp. 1-5, 2011, IEEE, 978-1-4577-2165-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Guillermo Payá Vayá |
Design and analysis of a generic VLIW processor for multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2011 |
RDF |
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16 | Thorsten Jungeblut |
Entwurfsraumexploration ressourceneffizienter VLIW-Prozessoren. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2011 |
RDF |
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16 | Jui-Chun Chen, Chang Hong Lin |
Improved Dictionary-Based Code-Compression Schemes with XOR Reference for RISC/VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12), pp. 2517-2523, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Jih-Ching Chiu, Kai-Ming Yang |
A Novel instruction stream buffer for VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 36(1), pp. 190-198, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Yung-Yuan Chen, Kuen-Long Leu |
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 34(1), pp. 49-61, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | D. S. Ivanov |
Register allocation with instruction scheduling for VLIW-architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Program. Comput. Softw. ![In: Program. Comput. Softw. 36(6), pp. 363-367, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch |
A Multi-Shared Register File Structure for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 58(2), pp. 215-231, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Meng Wang 0005, Yi Wang 0003, Duo Liu, Zhiwei Qin 0004, Zili Shao |
Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Softw. ![In: J. Syst. Softw. 83(5), pp. 772-785, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Christoph W. Kessler |
Compiling for VLIW DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Handbook of Signal Processing Systems ![In: Handbook of Signal Processing Systems, pp. 603-638, 2010, Springer, 978-1-4419-6344-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Tobias Koal, Heinrich Theodor Vierhaus |
A software-based self-test and hardware reconfiguration solution for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010, pp. 40-43, 2010, IEEE Computer Society, 978-1-4244-6612-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | David Stevens, Vassilios A. Chouliaras |
LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2010, 5-7 July 2010, Lixouri Kefalonia, Greece, pp. 122-126, 2010, IEEE Computer Society, 978-0-7695-4076-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Meng-Hsuan Cheng, Kenn Slagter, Tai-Wen Lung, Yeh-Ching Chung |
A VLIW-Based Post Compilation Framework for Multimedia Embedded DSPs with Hardware Specific Optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTPP ![In: Methods and Tools of Parallel Programming Multicomputers - Second Russia-Taiwan Symposium, MTPP 2010, Vladivostok, Russia, May 16-19, 2010, Revised Selected Papers, pp. 51-58, 2010, Springer, 978-3-642-14821-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Stephan Wong, Fakhar Anjam, Faisal Nadeem |
Dynamically reconfigurable register file for a softcore VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, pp. 969-972, 2010, IEEE Computer Society, 978-1-4244-7054-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Jimmy Bahuleyan, Rahul Nagpal, Y. N. Srikant |
Integrated energy-aware cyclic and acyclic scheduling for clustered VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Workshop Proceedings, pp. 1-8, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Manoj Gupta 0001, Fermín Sánchez, Josep Llosa |
A low cost split-issue technique to improve performance of SMT clustered VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Conference Proceedings, pp. 1-12, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Fakhar Anjam, Stephan Wong, Faisal Nadeem |
A shared reconfigurable VLIW multiprocessor system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Workshop Proceedings, pp. 1-8, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Fakhar Anjam, Stephan Wong, Faisal Nadeem |
A multiported register file with register renaming for configurable softcore VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China, pp. 403-408, 2010, IEEE, 978-1-4244-8981-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Fakhar Anjam, Muhammad Faisal Nadeem, Stephan Wong |
A VLIW softcore processor with dynamically adjustable issue-slots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China, pp. 393-398, 2010, IEEE, 978-1-4244-8981-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Claude-Pierre Jeannerod, Christophe Mouilleron, Jean-Michel Muller, Guillaume Revy, Christian Bertin, Jingyan Jourdan-Lu, Herve Knochel, Christophe Monat |
Techniques and tools for implementing IEEE 754 floating-point arithmetic on VLIW integer processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PASCO ![In: Proceedings of the 4th International Workshop on Parallel Symbolic Computation, PASCO 2010, July 21-23, 2010, Grenoble, France, pp. 1-9, 2010, ACM, 978-1-4503-0067-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Guillermo Payá Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch |
A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010, pp. 151-158, 2010, IEEE Computer Society, 978-1-4244-6967-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Che-Wei Lin, Chang Hong Lin |
A Power-saving Code-compression Design for the VLIW Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2010 International Conference on Embedded Systems & Applications, ESA 2010, July 12-15, 2010, Las Vegas Nevada, USA, pp. 122-130, 2010, CSREA Press, 1-60132-141-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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16 | Chengpin Tseng, Chiuyun Hung, De-Sheng Chen, Kuei-Chung Chang, Yiwen Wang 0003 |
Application Specific Instruction Set Exploration on VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2010 International Conference on Embedded Systems & Applications, ESA 2010, July 12-15, 2010, Las Vegas Nevada, USA, pp. 105-108, 2010, CSREA Press, 1-60132-141-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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16 | Chia-Han Lu, Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee |
LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 21(1), pp. 101-114, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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16 | Takahisa Wada, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Takashi Miyamori, Masaki Nakagawa |
A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 17(9), pp. 1285-1296, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | C. Bruel |
If-conversion for embedded VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Embed. Syst. ![In: Int. J. Embed. Syst. 4(1), pp. 2-16, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Ya-Shuai Lü, Li Shen 0007, Libo Huang, Zhiying Wang 0003, Nong Xiao |
Optimal subgraph covering for customisable VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 3(1), pp. 14-23, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Nayan V. Mujadiya |
Instruction scheduling for VLIW processors under variation scenario. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2009), Samos, Greece, July 20-23, 2009, pp. 33-40, 2009, IEEE, 978-1-4244-4501-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Zheng Shen, Hu He 0001, Yihe Sun |
Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece, pp. 505-512, 2009, IEEE Computer Society, 978-0-7695-3782-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | David Stevens, Nick Glynn, Panagiotis Galiatsatos, Vassilios A. Chouliaras, Dionysios I. Reisis |
Evaluating the performance of a configurable, extensible VLIW processor in FFT execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunisia, 13-19 December, 2009, pp. 771-774, 2009, IEEE, 978-1-4244-5090-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Vassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis |
A configurable length, Fused Multiply-Add floating point unit for a VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Annual IEEE International SoC Conference, SoCC 2009, September 9-11, 2009, Belfast, Northern Ireland, UK, Proceedings, pp. 93-96, 2009, IEEE, 978-1-4244-4940-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Manoj Gupta 0001, Fermín Sánchez, Josep Llosa |
Thread Merging Schemes for Multithreaded Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: ICPP 2009, International Conference on Parallel Processing, Vienna, Austria, 22-25 September 2009, pp. 445-452, 2009, IEEE Computer Society, 978-0-7695-3802-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Guillermo Payá Vayá, Javier Martín-Langerwerf, Florian Giesemann, Holger Blume, Peter Pirsch |
Instruction merging to increase parallelism in VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: 2008 IEEE International Symposium on System-on-Chip, SOC 2009, Tampere, Finland, October 6-7, 2008, pp. 143-146, 2009, IEEE, 978-1-4244-4465-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Mattias V. Eriksson, Christoph W. Kessler |
Integrated Modulo Scheduling for Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 65-79, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Guillermo Talavera |
Scratchpad-oriented address generation for low-power embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2009 |
RDF |
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16 | David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo |
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 41(1), pp. 38-48, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero |
Power-efficient VLIW design using clustering and widening. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Embed. Syst. ![In: Int. J. Embed. Syst. 3(3), pp. 141-149, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|