Search results for "VLSI-SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Hyunsun Park, Chanha Kim, Sungjoo Yoo, Chanik Park	Filtering dirty data in DRAM to reduce PRAM writes.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Hyungil Park, Ingi Lim, Sungweon Kang, Whan-woo Kim	10Mbps human body communication SoC for BAN.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Namhyung Kim, Junwhan Ahn, Woong Seo, Kiyoung Choi	Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Lin Wei, Lei Zhou	An equilibrium partitioning method for multicast traffic in 3D NoC architecture.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Masahiro Fujita	Analysis and testing on delays with two time frames.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	S. E. Kim, T. W. Kang, S. W. Kang, K. H. Park, M. A. Chung	High-efficiency voltage regulation stage in energy harvesting systems.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Youngsoo Shin, Chi-Ying Tsui	Message from the technical program chairs.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Ramin Bashizade, Hamid Sarbazi-Azad	Traffic-aware buffer reconfiguration in on-chip networks.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
1	Gabriele Miorandi, Alberto Ghiribaldi, Steven M. Nowick, Davide Bertozzi	Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Jesus-Andres Mendoza-Bonilla, Alejandro Cortez-Ibarra, Edgar-Andrei Vega-Ochoa, Francisco Rangel-Patino, Brandon Gore	Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Davide Sabena, Matteo Sonza Reorda, Luca Sterpone	Soft error effects analysis and mitigation in VLIW safety-critical applications.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Moon Gi Seok, Daejin Park, Geun Rae Cho, Tag Gon Kim	Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán	Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Zeineb Bel Hadj Amor, Laurence Pierre, Dominique Borrione	A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid	VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Dongwoo Lee, Kiyoung Choi	Energy-efficient partitioning of hybrid caches in multi-core architecture.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Liang Wang 0020, Xiaohang Wang 0001, Terrence S. T. Mak	Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Alfonso Martínez-Cruz, Ricardo Barrón Fernández, Herón Molina-Lozano	Automated functional coverage directed for complex digital systems.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Matthias Jung 0001, Christian Weis, Norbert Wehn, MohammadSadegh Sadri, Luca Benini	Optimized active and power-down mode refresh control in 3D-DRAMs.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy 0001, Anupam Chattopadhyay	Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Bernard van Gastel, Freek Verbeek, Julien Schmaltz	Inference of channel types in micro-architectural models of on-chip communication networks.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Gunti Nagendra Babu, Aman Khatri, Karthikeyan Lingasubramanian	Realizing a security aware triple modular redundancy scheme for robust integrated circuits.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Jeffrey McDaniel, Daniel T. Grissom, Philip Brisk	Multi-terminal PCB escape routing for digital microfluidic biochips using negotiated congestion.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Sreenivaas S. Muthyala, Nur A. Touba	Reducing test time for 3D-ICs by improved utilization of test elevators.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Hari Anand Ravi, Mayank Goel, Prasad Bhilawadi	Circuit to reduce Gate Induced Drain Leakage in CMOS output buffers.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Zoltán Endre Rákossy	Modeling, analysis and exploration of layers: A 3D computing architecture.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Giovanni Bruni, Paolo Rech, Lucas A. Tambara, Gabriel L. Nazar, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis 0001, Alessandro Paccagnella	Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Lorena Garcia (eds.)	22nd International Conference on Very Large Scale Integration, VLSI-SoC, Playa del Carmen, Mexico, October 6-8, 2014	VLSI-SoC	2014	DBLP BibTeX RDF
1	Jeffrey McDaniel, Brendon Parker, Philip Brisk	Simulated annealing-based placement for microfluidic large scale integration (mLSI) chips.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Manoj Kumar 0001, Vijay Laxmi, Manoj Singh Gaur, Masoud Daneshtalab, Mark Zwolinski	A novel non-minimal turn model for highly adaptive routing in 2D NoCs.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Wei-Yu Tsai, Huichu Liu, Xueqing Li, Vijaykrishnan Narayanan	Low-power high-speed current mode logic using Tunnel-FETs.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	K. Chibani, Mohamed Ben Jrad, Michele Portolan, Régis Leveugle	Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Farshad Moradi, Jens Kargaard Madsen	Improved read and write margins using a novel 8T-SRAM cell.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Hiroyuki Yamauchi, Worawit Somha	Deconvolution algorithm dependencies of estimation errors of RTN effects on subnano-scaled SRAM margin variation.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Satoshi Goto	A low power 720p motion estimation processor with 3D stacked memory.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Sidinei Ghissoni, Eduardo A. C. da Costa, Angelo Goncalves da Luz	Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Ruping Cao, John Ferguson, Fabien Gays, Youssef Drissi, Alexandre Arriordaz, Ian O'Connor	Silicon photonics design rule checking: Application of a programmable modeling engine for non-Manhattan geometry verification.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Thomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana	Towards energy effective LDPC decoding by exploiting channel noise variability.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Javier Osorio Figueroa, Mónico Linares Aranda	Study of on-chip vias of resonant rotary traveling wave oscillators.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta 0001	Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Alan Mishchenko	Logic synthesis and verification on fixed topology.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Andrew A. Kennings, Nima Karimpour Darav, Laleh Behjat	Detailed placement accounting for technology constraints.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Vladan Popovic, Yusuf Leblebici	Reconfigurable forward homography estimation system for real-time applications.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Matheus T. Moreira, Ney Laert Vilar Calazans	Advances on the state of the art in QDI design.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Masaki Nakanishi, Miki Matsuyama, Yumi Yokoo	A quantum algorithm processor architecture based on register reordering.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Guillaume Hubert, Stephan De Castro, Jean-Max Dutertre, Alexandre Sarafianos, Noemie Boher, Mathieu Lisart, Joel Damiens, Philippe Candelier, Clément Tavernier	Laser-induced fault effects in security-dedicated circuits.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Filippo Cucchetto, Alessandro Lonardi, Graziano Pravadelli	A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platforms.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri	AES design space exploration new line for scan attack resiliency.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Zhen Li 0046, Sébastien Le Beux, Ian O'Connor, Christelle Monat, Xavier Letartre	Complementary logic interface for high performan optical computing with OLUT.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Alberto Nannarelli	Decimal engine for energy-efficient multicore processors.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Laurent Chusseau, Rachid Omarouayache, Jérémy Raoult, Sylvie Jarrix, Philippe Maurine, Karim Tobich, Alexandre Boyer, Bertrand Vrignon, John Shepherd 0004, Thanh-Ha Le, Maël Berthier, Lionel Rivière, Bruno Robisson, Anne-Lise Ribotta	Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI).	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Shilpa Pendyala, Srinivas Katkoori	Self similarity and interval arithmetic based leakage optimization in RTL datapaths.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Paolo Maistri, Régis Leveugle, Lilian Bossuet, Alain Aubert, Viktor Fischer, Bruno Robisson, Nicolas Moro, Philippe Maurine, Jean-Max Dutertre, Mathieu Lisart	Electromagnetic analysis and fault injection onto secure circuits.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
1	Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione	SyntHorus-2: Automatic prototyping from PSL.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Abdulkadir Akin, Ipek Baz, Luis Manuel Gaemperle, Alexandre Schmid, Yusuf Leblebici	Compressed look-up-table based real-time rectification hardware.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Yuhui Bai, Syed Zahid Ahmed, Imen Mhedhbi, Khalil Hachicha, Cedric Champion, Patrick Garda, Bertrand Granado	FPGA vs DSP: A throughput and power efficiency comparison for Hierarchical Enumerative Coding.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Sani R. Nassif, Yale N. Patt, Magdy S. Abadir	Keynote 1 - VLSI 2.0: R&D Post Moore.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Sungho Kim, Urs Frey	An inverter-based neural amplifier for neural spike detection.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Chien-Hung Kuo, Cin-De Jhang	A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Mehmet Burak Aykenar, Muhammet Ozgur, Osman Seckin Simsek, Oguz Ergin	Adapting the columns of storage components for lower static energy dissipation.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Joachim Knoch, Thomas Grap, Marcel Müller	Gate-controlled doping in carbon-based FETs.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Hussain A. Alzaher, Noman Tasadduq	Fully electronically programmable complex filter for multistandard applications.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Elmira Karimi, Mohammad Hashem Haghbayan, Adele Maleki, Mahmoud Tabandeh	Graph based fault model definition for bus testing.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Kostas Tsoumanis, Constantinos Efstathiou, Nikolaos Moschopoulos, Kiamal Z. Pekmestzi	On the design of modulo 2n±1 residue generators.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Jie Meng, Tiansheng Zhang, Ayse K. Coskun	Dynamic cache pooling for improving energy efficiency in 3D stacked multicore processors.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Melvin Eze, Ozcan Ozturk 0001, Vijaykrishnan Narayanan	Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Hailong Jiao, Volkan Kursun	Characterization of mode transition timing overhead for net energy savings in low-noise MTCMOS circuits.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Bertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart, Jean-Philippe Noel, Philippe Flatresse, Edith Beigné	Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Yann Kieffer, Salvador Mir	New techniques for selecting test frequencies for linear analog circuits.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Aydin Aysu, Murat Sayinta, Cevahir Cigla	Low cost FPGA design and implementation of a stereo matching system for 3D-TV applications.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Assia Hamouda, Rüdiger Arnold, Otto Manck, Nour-Eddine Bouguechal	7.72 ppm/°C, ultralow power, high PSRR CMOS bandgap reference voltage.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Somayeh Timarchi, Maryam Saremi, Mahmood Fazlali, Georgi Gaydadjiev	High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Yusuf Adibelli, Ilker Hamzaoglu	A high performance and low energy hardware for intra prediction with Template Matching.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Wael Adi, Shaza Zeitouni, X. Huang, Marc Fyrbiak, Christian Kison, Marc Jeske, Z. Alnahhas	IP-core protection for a non-volatile Self-reconfiguring SoC environment.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Yankin Tanurhan, Pieter van der Wolf	Processors as SoC building blocks.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Soumya Banerjee 0004, Kai Da Zhao, Wenjing Rao, Milos Zefran	Decentralized self-balancing systems.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Vazgen Melikyan, Abraham Balabanyan, Armen Durgaryan, Harutyun Stepanyan, Karen Sloyan, Hovik Musayelyan, Gayane Markosyan	PVT variation detection and compensation methods for high-speed systems.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Keni Qiu, Mengying Zhao, Chenchen Fu, Chun Jason Xue	Data re-allocation enabled cache locking for embedded systems.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita	A debugging method for gate level circuit designs by introducing programmability.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Dogan Ulus, Alper Sen 0001, I. Faik Baskaya	Analog layer extensions for analog/mixed-signal assertion languages.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Manel Elloumi, Mohamed Krid, Dorra Sellami Masmoudi	Implementation of Neuro-Fuzzy System based image edge detection.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Levent Aksoy, Paulo F. Flores, José Monteiro 0001	Towards the least complex time-multiplexed constant multiplication.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Anna Bernasconi 0001, Valentina Ciriani, Gabriella Trucco, Tiziano Villa	Minimization of EP-SOPs via Boolean relations.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Mostafa Rahimi Azghadi, Said F. Al-Sarawi, Nicolangelo Iannella, Derek Abbott	A new compact analog VLSI model for Spike Timing Dependent Plasticity.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Takeshi Matsumoto, Satoshi Jo	FOF: Functionally Observable Fault and its ATPG techniques.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Qiuling Zhu, Navjot Garg, Yun-Ta Tsai, Kari Pulli	An energy efficient time-sharing pyramid pipeline for multi-resolution computer vision.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Yajuan He, Bo Chen, Qiang Li 0021	Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Michael Schaffner, Pascal Hager, Lukas Cavigelli, Pierre Greisen, Frank K. Gürkaynak, Hubert Kaeslin	A real-time 720p feature extraction core based on Semantic Kernels Binarized.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Ali Fazli Yeknami, Atila Alvandpour	A 0.7-V 400-nW fourth-order active-passive ΔΣ modulator with one active stage.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Tetsuro Hamada, Qian Zhao 0001, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi	Three-dimensional stacking FPGA architecture using face-to-face integration.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Majid Zamani, Clemens Eder, Andreas Demosthenous	Analog-to-digital converters power dissipation limits of CBSC-based pipelined.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Francisco-Jose Sanchis-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi	Automatic mapping of OpenCV based systems on new heterogeneous SoCs.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luís Miguel Silveira, H. Fatih Ugurdag (eds.)	21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013	VLSI-SoC	2013	DBLP BibTeX RDF
1	Jonathan van de Belt, Paul D. Sutton, Linda Doyle	Accelerating software radio: Iris on the Zynq SoC.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal	Power-aware SoC test optimization through dynamic voltage and frequency scaling.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Debora Matos, Cezar Reinbrecht, Tiago Motta, Altamiro Amadeu Susin	A power-efficient hierarchical network-on-chip topology for stacked 3D ICs.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Sharareh Zamanzadeh, Ali Jahanian 0001	Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Alp Arslan Bayrakci	On the accuracy of Monte Carlo yield estimators.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Farshad Eshghabadi, Fatemeh Banitorfian, Norlaili Mohd Noh, Mohd Tafir Mustaffa, Asrulnizam Bin Abd Manaf, Othman Sidek	Multi-band tunable low noise amplifiers operating at 850MHz and 1900MHz standards.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
1	Jongbum Park, Jongpil Jung, Kang Yi, Chong-Min Kyung	Static energy minimization of 3D stacked L2 cache with selective cache compression.	VLSI-SoC	2013	DBLP DOI BibTeX RDF

Publications at "VLSI-SoC"( http://dblp.L3S.de/Venues/VLSI-SoC )