Search results for "Virtex"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	Slavisa Jovanovic, Camel Tanougast, Serge Weber	A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems.	AHS	2007	DBLP DOI BibTeX RDF
8	David P. Montminy, Rusty O. Baldwin, Paul D. Williams, Barry E. Mullins	Using Relocatable Bitstreams for Fault Tolerance.	AHS	2007	DBLP DOI BibTeX RDF
8	Xun Zhang 0002, Hassan Rabah, Serge Weber	Auto-adaptive reconfigurable architecture for scalable multimedia applications.	AHS	2007	DBLP DOI BibTeX RDF
8	Chichyang Chen, Paul Chow	Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	exponential computation, logarithmic computation, logarithmic number system (LNS) arithmetic, floating-point arithmetic
8	Xiaofang Wang, Sotirios G. Ziavras	Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors.	ISQED	2007	DBLP DOI BibTeX RDF
8	Peter Lee 0002, Esther Costa, Stephanie McBader, Luca Clementel, Alvise Sartori	LogTOTEM: A Logarithmic Neural Processor and its Implementation on an FPGA Fabric.	IJCNN	2007	DBLP DOI BibTeX RDF
8	Hugo de Garis, Jian Yu Tang, Di Huang 0003	Artificial Brains - A Cheap Method for Speeding the Evolution of Neural Network Modules for Artificial Brain Building.	IJCNN	2007	DBLP DOI BibTeX RDF
8	Ali El Kateeb, Lubna Al Azzawi	Low Cost HIV Testing System for Tele-Health Applications.	AINA Workshops (2)	2007	DBLP DOI BibTeX RDF	HIV kits, HIV screening, Field programmable gate array (FPGA), System-on-chip (SOC)
8	Wim Roelandts	Creating a Culture of Innovation.	VLSI Design	2007	DBLP DOI BibTeX RDF
8	Himanshu Patel, Sanjay Trivedi, R. Neelkanthan, V. R. Gujraty	A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance.	VLSI Design	2007	DBLP DOI BibTeX RDF
8	Daisuke Suzuki	How to Maximize the Potential of FPGA Resources for Modular Exponentiation.	CHES	2007	DBLP DOI BibTeX RDF
8	Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto	Arithmetic Operators for Pairing-Based Cryptography.	CHES	2007	DBLP DOI BibTeX RDF	FPGA, elliptic curve, hardware accelerator, finite field arithmetic, ? T pairing
8	Thaísa Leal da Silva, Cláudio Machado Diniz, João Alberto Vortmann, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi	A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder.	PSIVT	2007	DBLP DOI BibTeX RDF	8x8 2-D DCT, H.264/AVC standard, Video compression, Architectural Design
8	Marcelo Schiavon Porto, Luciano Volcan Agostini, Leandro Rosa, Altamiro Amadeu Susin, Sergio Bampi	High Throughput Hardware Architecture for Motion Estimation with 4: 1 Pel Subsampling Targeting Digital Television Applications.	PSIVT	2007	DBLP DOI BibTeX RDF	Motion estimation, hardware architecture, FPGA design
8	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt, Juanjo Noguera	Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.	DAC	2007	DBLP DOI BibTeX RDF
8	Amilcar do Carmo Lucas, Sven Heithecker, Rolf Ernst	FlexWAFE - A High-end Real-Time Stream Processing Library for FPGAs.	DAC	2007	DBLP DOI BibTeX RDF
8	Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan	Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.	DAC	2007	DBLP DOI BibTeX RDF
8	Kumara Ratnayake, Aishy Amer	An FPGA Architecture of Stable-Sorting on a Large Data Volume : Application to Video Signals.	CISS	2007	DBLP DOI BibTeX RDF
8	Abhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan	Compiling PCRE to FPGA for accelerating SNORT IDS.	ANCS	2007	DBLP DOI BibTeX RDF	deep payload inspection, nondeterministic nite automata, intrusion detection system, regular expressions
8	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt	Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
8	Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo	Low bit rate image compression core for onboard space applications.	IEEE Trans. Circuits Syst. Video Technol.	2006	DBLP DOI BibTeX RDF
8	Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides	Accuracy-Guaranteed Bit-Width Optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
8	Premachandran R. Menon, Weifeng Xu, Russell Tessier	Design-specific path delay testing in lookup-table-based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
8	Jaime Jimenez, José Luis Martín 0001, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias	Comparison of two designs for the multifunction vehicle bus.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
8	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	BIST, delay faults, look-up table
8	George A. Constantinides	Word-length optimization for differentiable nonlinear systems.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	word-length, synthesis, Signal processing, bitwidth
8	Fatma Sayadi, Emmanuel Casseau, Mohamed Atri, Mehrez Marzougui, Rached Tourki, Eric Martin 0001	G729 Voice Decoder Design.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	CELP coders, G729 standard, Hw/Sw design, LPC analysis, voice decoding, IP, VLSI design
8	Ricardo José Colom-Palero, Rafael Gadea Gironés, Angel Sebastià-Cortés	A Novel FPGA Architecture of a 2-D Wavelet Transform.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	image processing, VLSI, signal processing, programmable logic device
8	Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	reconfiguration overhead, reconfigurable computing, compiler optimization
8	Kumara Ratnayake, Aishy Amer	An FPGA-Based Implementation of Spatio-Temporal Object Segmentation.	ICIP	2006	DBLP DOI BibTeX RDF
8	Sutjipto Arifin, Peter Y. K. Cheung	User Attention Based Arousal Content Modeling.	ICIP	2006	DBLP DOI BibTeX RDF
8	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	Rescheduling for Optimized SHA-1 Calculation.	SAMOS	2006	DBLP DOI BibTeX RDF
8	Emeric K. Jolly, Martin Fleury	Parallel Multi-Sector Algorithm for the General Hough Transform.	PDP	2006	DBLP DOI BibTeX RDF
8	Young H. Cho, James Moscola, John W. Lockwood	Context-Free-Grammar based Token Tagger in Reconfigurable Devices.	ICDE Workshops	2006	DBLP DOI BibTeX RDF
8	Michael Hübner 0001, Christian Schuck, Matthias Kühnle, Jürgen Becker 0001	New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits.	ISVLSI	2006	DBLP DOI BibTeX RDF
8	Seyed Ebrahim Esmaeili, Nabil I. Khachab, Moustafa Y. Ghannam	Effect of Glitches on the Efficiency of Components' Region-Constrained Placement as a Fast Approach to Reduce FPGA's Dynamic Power Consumption.	ISVLSI	2006	DBLP DOI BibTeX RDF
8	Masood Deh-Yadegari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi	A New Protocol Stack Model for Network on Chip.	ISVLSI	2006	DBLP DOI BibTeX RDF
8	Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi	Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
8	Sinan Yalcin, Ilker Hamzaoglu	A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
8	Wagston T. Staehler, Eduardo A. Berriel, Altamiro Amadeu Susin, Sergio Bampi	Architecture of an HDTV Intraframe Predictor for a H.264 Decoder.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
8	Senthamaraikannan Raghunath, Syed Mahfuzul Aziz	High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT Processor.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
8	Joshua Noseworthy, Miriam Leeser	Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic.	FPGA	2006	DBLP DOI BibTeX RDF
8	David T. Nguyen, Gokhan Memik, Alok N. Choudhary	A reconfigurable architecture for network intrusion detection using principal component analysis.	FPGA	2006	DBLP DOI BibTeX RDF
8	Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong	Performance benefits of monolithically stacked 3D-FPGA.	FPGA	2006	DBLP DOI BibTeX RDF	3D monolithically stacked, FPGA, performance analysis
8	Christopher R. Clark, David E. Schimmel	Modeling the data-dependent performance of pattern-matching architectures.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, pattern matching
8	Young H. Cho, James Moscola, John W. Lockwood	Context-free-grammar based token tagger in reconfigurable devices.	FPGA	2006	DBLP DOI BibTeX RDF
8	Nathaniel Couture, Kenneth B. Kent	Periodic licensing of FPGA based intellectual property.	FPGA	2006	DBLP DOI BibTeX RDF
8	Lotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis	A reconfigurable hardware based embedded scheduler for buffered crossbar switches.	FPGA	2006	DBLP DOI BibTeX RDF	buffered crossbar fabric, scheduling, reconfigurable hardware
8	Thinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama	Manifold similarity search of DNA sequences with reconfigurable hardware.	FPGA	2006	DBLP DOI BibTeX RDF
8	Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel	Fast and accurate resource estimation of automatically generated custom DFT IP cores.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA resource estimation, design generator, IP, discrete fourier transform
8	Wolfgang Klingauf, Hagen Gädke, Robert Günzel	TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC.	DATE	2006	DBLP DOI BibTeX RDF
8	Sutjipto Arifin, Peter Y. K. Cheung	A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
8	Amilcar do Carmo Lucas, Sven Heithecker, Peter Rüffer, Rolf Ernst, Holger Rückert, Gerhard Wischermann, Karin Gebel, Reinhard Fach, Wolfgang Huther, Stefan Eichner, Gunter Scheller	A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications.	DATE	2006	DBLP DOI BibTeX RDF	digital film, stream-based architecture, weak-programming, FPGA, motion-estimation, reconfigurable
8	Martin Novotný, Jan Schmidt	Two Architectures of a General Digit-Serial Normal Basis Multiplier.	DSD	2006	DBLP DOI BibTeX RDF
8	Reid B. Porter, Jan R. Frigo, Maya B. Gokhale, Christophe Wolinski, François Charot, Charles Wagner	A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing.	DSD	2006	DBLP DOI BibTeX RDF
8	Tadeusz Tomczak	Residue Arithmetic in FPGA Matrices.	DepCoS-RELCOMEX	2006	DBLP DOI BibTeX RDF
8	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena	Fault Injection-based Reliability Evaluation of SoPCs.	ETS	2006	DBLP DOI BibTeX RDF
8	William N. Chelton, Mohammed Benaissa	High-Speed Pipelined EGG Processor on FPGA.	SiPS	2006	DBLP DOI BibTeX RDF
8	Choudhury A. Rahman, Wael M. Badawy	An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder.	SiPS	2006	DBLP DOI BibTeX RDF
8	Jin Wang, Chong Ho Lee	Complete FPGA Implemented Evolvable Image Filters.	MICAI	2006	DBLP DOI BibTeX RDF
8	Antonin Hermanek, Michal Kunes, Michal Kvasnicka	Using Reconfigurable HW for High Dimensional CAF Computation.	FPL	2006	DBLP DOI BibTeX RDF
8	Angel Fernandez Herrero, Alberto Jimenez-Pacheco, Gabriel Caffarena, Javier Casajús-Quirós	Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver.	FPL	2006	DBLP DOI BibTeX RDF
8	Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk	Efficient Realtime FPGA Implementation of the Trace Transform.	FPL	2006	DBLP DOI BibTeX RDF
8	Thilo Pionteck, Roman Koch, Carsten Albrecht	Applying Partial Reconfiguration to Networks-On-Chips.	FPL	2006	DBLP DOI BibTeX RDF
8	Christos A. Papachristou, J. Weaver, R. Vijayakumar, Francis G. Wolff	A Dynamic Reconfigurable Fabric for Platform SoCs.	FPL	2006	DBLP DOI BibTeX RDF
8	Shrutisagar Chandrasekaran, Abbes Amira	FPGA Implementation and Power Modelling of the Fast Walsh Transform.	FPL	2006	DBLP DOI BibTeX RDF
8	Ling Zhuo, Viktor K. Prasanna	High-Performance and Parameterized Matrix Factorization on FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
8	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design.	FPL	2006	DBLP DOI BibTeX RDF
8	Andrea Lodi 0002, Claudio Mucci, Massimo Bocchi, Andrea Cappelli, Mario de Dominicis, Luca Ciccarelli	A Multi-Context Pipelined Array for Embedded Systems.	FPL	2006	DBLP DOI BibTeX RDF
8	Pedro C. Diniz, Gokul Govindu	Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit.	FPL	2006	DBLP DOI BibTeX RDF
8	Phillip H. Jones, John W. Lockwood, Young H. Cho	A Thermal Management and Profiling Method for Reconfigurable Hardware Applications.	FPL	2006	DBLP DOI BibTeX RDF
8	Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin	FPGA Design of A H.264/AVC Main Profile Decoder for HDTV.	FPL	2006	DBLP DOI BibTeX RDF
8	Paul Saunders, Anthony D. Fagan	A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes.	FPL	2006	DBLP DOI BibTeX RDF
8	James Moscola, Young H. Cho, John W. Lockwood	Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices.	FPL	2006	DBLP DOI BibTeX RDF
8	François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater	FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks.	FPL	2006	DBLP DOI BibTeX RDF
8	María José Moure, María Dolores Valdés, Pablo Rodiz, Loreto Rodríguez-Pardo, José Fariña Rodríguez	An FPGA-Based System on Chip for the Measurement of QCM Sensors Resolution.	FPL	2006	DBLP DOI BibTeX RDF
8	Sutjipto Arifin, Peter Y. K. Cheung	Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System.	FPL	2006	DBLP DOI BibTeX RDF
8	Francisco-Javier Veredas, Hans-Jörg Pfleiderer	Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs.	FPL	2006	DBLP DOI BibTeX RDF
8	Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi	A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection.	FPL	2006	DBLP DOI BibTeX RDF
8	Luis F. Rodríguez-Ramos, Angel Alonso, Fernando Gago, Jose V. Gigante, Guillermo Herrera, Teodora Viera	Adaptive Optics Real-Time Control Using FPGA.	FPL	2006	DBLP DOI BibTeX RDF
8	Peter Alfke	Tutorial: 65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications.	FPL	2006	DBLP DOI BibTeX RDF
8	Michael Hübner 0001, Jürgen Becker 0001	Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration.	SBCCI	2006	DBLP DOI BibTeX RDF	designflow, dynamic and partial reconfiguration, reconfigurable hardware
8	Love Singhal, Elaheh Bozorgzadeh	Physically-aware exploitation of component reuse in a partially reconfigurable architecture.	IPDPS	2006	DBLP DOI BibTeX RDF
8	Jens Hagemeyer, Boris Kettelhoit, Mario Porrmann	Dedicated module access in dynamically reconfigurable systems.	IPDPS	2006	DBLP DOI BibTeX RDF
8	Brian F. Veale, John K. Antonio, Monte P. Tull, Sean A. Jones	Selection of instruction set extensions for an FPGA embedded processor core.	IPDPS	2006	DBLP DOI BibTeX RDF
8	Jeffrey William Schuster, Kshitij Gupta, Raymond R. Hoare	Speech silicon AM: an FPGA-based acoustic modeling pipeline for hidden Markov model based speech recognition.	IPDPS	2006	DBLP DOI BibTeX RDF
8	James Moscola, Young H. Cho, John W. Lockwood	Reconfigurable context-free grammar based data processing hardware with error recovery.	IPDPS	2006	DBLP DOI BibTeX RDF
8	Maryam Mizani, Daler N. Rakhmatov	Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter.	IPDPS	2006	DBLP DOI BibTeX RDF
8	Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle	An adaptive system-on-chip for network applications.	IPDPS	2006	DBLP DOI BibTeX RDF
8	Ricardo Chaves, Georgi Kuzmanov, Stamatis Vassiliadis, Leonel Sousa	Reconfigurable memory based AES co-processor.	IPDPS	2006	DBLP DOI BibTeX RDF
8	Shannon Koh, Oliver Diessel	COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
8	Michael R. Bodnar, John R. Humphrey, Petersen F. Curt, James P. Durbano, Dennis W. Prather	Floating-Point Accumulation Circuit for Matrix Applications.	FCCM	2006	DBLP DOI BibTeX RDF
8	Cao Liang, Jing Ma 0006, Xinming Huang 0001	Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms.	FCCM	2006	DBLP DOI BibTeX RDF
8	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design.	FCCM	2006	DBLP DOI BibTeX RDF
8	K. Scott Hemmert, Keith D. Underwood	Open Source High Performance Floating-Point Modules.	FCCM	2006	DBLP DOI BibTeX RDF	IEEE floating point, FPGA, reconfigurable computing
8	Reid B. Porter, Jan R. Frigo, Maya B. Gokhale, Christophe Wolinski, François Charot, Charles Wagner	A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing.	FCCM	2006	DBLP DOI BibTeX RDF
8	Li Wang, Youren Wang, Rui Yao, Zhai Zhang	Hardware Implementation of AES Based on Genetic Algorithm.	ICNC (2)	2006	DBLP DOI BibTeX RDF
8	Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking.	ARC	2006	DBLP DOI BibTeX RDF	exhaustive key search, cryptanalysis, hash-functions, FPGA implementation, time-memory trade-off, rainbow table
8	Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar	Automatic Compilation Framework for Bloom Filter Based Intrusion Detection.	ARC	2006	DBLP DOI BibTeX RDF
8	Hongzhi Wang 0003, Pierre Leray, Jacques Palicot	A Reconfigurable Architecture for MIMO Square Root Decoder.	ARC	2006	DBLP DOI BibTeX RDF