Search results for "accelerator"

Hits ?▲	Authors	Title	Venue	Year	Link
10	Wantong Li, Madison Manley, James Read, Ankit Kaul, Muhannad S. Bakir, Shimeng Yu	H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Jindong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang 0080, Yi Zeng 0001	FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Trio Adiono, Rhesa Muhammad Ramadhan, Nana Sutisna, Infall Syafalni, Rahmat Mulyawan, Chang Hong Lin	Fast and Scalable Multicore YOLOv3-Tiny Accelerator Using Input Stationary Systolic Architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Chih-Chyau Yang, Tian-Sheuan Chang	A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Pengzhou He, Yazheng Tu, Jiafeng Xie, H. S. Jacinto	KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-Based Post-Quantum Cryptography.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Sungju Ryu, Youngtaek Oh, Jae-Joon Kim	Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Pengzhou He, Yazheng Tu, Tianyou Bao, Leonel Sousa, Jiafeng Xie	COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Rongrong She, Hui Qian 0002, Zhongfeng Wang 0001	A New ACD-OMP Accelerator With Clustered Computing Look-Ahead.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Tao Li 0005, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh	Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Yishuo Meng, Chen Yang 0005, Siwei Xiang, Jianfei Wang, Kuizhi Mei, Li Geng	An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Shubham Jain, Hsinyu Tsai, Ching-Tzu Chen, Ramachandran Muralidhar, Irem Boybat, Martin M. Frank, Stanislaw Wozniak, Milos Stanisavljevic, Praneet Adusumilli, Pritish Narayanan, Kohji Hosokawa, Masatoshi Ishii, Arvind Kumar, Vijay Narayanan, Geoffrey W. Burr	A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Jordi Fornt, Pau Fontova-Musté, Martí Caro, Jaume Abella 0001, Francesc Moll, Josep Altet, Christoph Studer	An Energy-Efficient GeMM-Based Convolution Accelerator With On-the-Fly im2col.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Haikuo Shao, Jinming Lu, Meiqi Wang, Zhongfeng Wang 0001	An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Tao Li 0005, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh	Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator".	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Steven Colleman, Man Shi, Marian Verhelst	COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Yazheng Tu, Pengzhou He, Çetin Kaya Koç, Jiafeng Xie	LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Gauthaman Murali, Aditya Iyer, Lingjun Zhu, Jianming Tong, Francisco Muñoz-Martínez, Srivatsa Rangachar Srinivasa, Tanay Karnik, Tushar Krishna, Sung Kyu Lim	On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Yuyang Li 0001, Yejoong Kim, Inhee Lee	A 5-mm2, 4.7-μW Convolutional Neural Network Layer Accelerator for Miniature Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
10	Osman Volkan Karaca, Kayhan M. Imre, Ali Ziya Alkar	Network accelerator for parallel discrete event simulations.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
10	Francesco Fienga, Vincenzo Romano Marrazzo, Leonardo Sito, Francesco Giordano, Noemi Beni, Zoltan Szillasi, Andrea Irace, Wolfram Zeuner, Benoît Salvant, Salvatore Buontempo, Giovanni Breglio	Direct Measurement of Beam-Induced Heating on Accelerator Pipes With Fiber Optic Sensors: Numerical Analysis Validation.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
10	Hao Jia, Yuxiang Huan, Chen Ding, Yulong Yan, Jianjun Cui, Jiachen Wang, Chuhuang Cai, Lida Xu, Zhuo Zou, Lirong Zheng 0001	A Domain-Specific Accelerator for Ultralow Latency Market Data Distribution System.	IEEE Trans. Ind. Informatics	2023	DBLP DOI BibTeX RDF
10	Jiankuo Dong, Pinchang Zhang, Kaisheng Sun, Fu Xiao 0001, Fangyu Zheng, Jingqiang Lin	EG-Four$\mathbb {Q}$: An Embedded GPU-Based Efficient ECC Cryptography Accelerator for Edge Computing.	IEEE Trans. Ind. Informatics	2023	DBLP DOI BibTeX RDF
10	Shaahin Angizi, Sepehr Tabrizchi, David Z. Pan, Arman Roohi	PISA: A Non-Volatile Processing-in-Sensor Accelerator for Imaging Systems.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
10	Milad Tanavardi Nasab, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari	High-Performance and Robust Spintronic/CNTFET-Based Binarized Neural Network Hardware Accelerator.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
10	Weikang Qiao, Licheng Guo, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong	TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-Based FPGAs.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
10	Hui-Wen Liu, Chung-An Shen	The Design of Efficient Data Flow and Low-Complexity Architecture for a Highly Configurable CNN Accelerator.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
10	Tresa Joseph, T. S. Bindiya	Performance-Driven LSTM Accelerator Hardware Using Split-Matrix-Based MVM.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
10	Mahan Rezaei, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari	A high-capacity and nonvolatile spintronic associative memory hardware accelerator.	IET Circuits Devices Syst.	2023	DBLP DOI BibTeX RDF
10	Lingxiao Hou, Yutaka Masuda, Tohru Ishihara	An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2023	DBLP DOI BibTeX RDF
10	Hongwu Jiang, Shanshi Huang, Wantong Li, Shimeng Yu	ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Quan Cheng, Mingqiang Huang, Changhai Man, Ao Shen, Liuyao Dai, Hao Yu 0001, Masanori Hashimoto	Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Wenzhe Zhao, Qiwei Dang, Tian Xia 0008, Jingming Zhang, Nanning Zheng 0001, Pengju Ren	Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Chenjia Xie, Zhuang Shao, Ning Zhao, Yuan Du, Li Du	An Efficient CNN Inference Accelerator Based on Intra- and Inter-Channel Feature Map Compression.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Yifan Gong 0005, Jinshuo Zhang, Xin Liu, Jialin Li, Ying Lei, Zhe Zhang, Chen Yang 0005, Li Geng	A Real-Time and Efficient Optical Flow Tracking Accelerator on FPGA Platform.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Yiqi Wang 0005, Fengbin Tu, Leibo Liu, Shaojun Wei, Yuan Xie 0001, Shouyi Yin	SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng	ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Han-Gyeol Mun, Seunghyun Moon, Byungjun Kim, Kyeong-Jun Lee, Jae-Yoon Sim	Bottleneck-Stationary Compact Model Accelerator With Reduced Requirement on Memory Bandwidth for Edge Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Suchang Kim, Boseon Jang, Jaeyoung Lee, Hyungjoon Bae, Hyejung Jang, In-Cheol Park	A CNN Inference Accelerator on FPGA With Compression and Layer-Chaining Techniques for Style Transfer Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Hongtu Zhang, Yuhao Shu, Qi Deng, Hao Sun, Wenfeng Zhao, Yajun Ha	WDVR-RAM: A 0.25-1.2 V, 2.6-76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Mingqiang Huang, Junyi Luo, Chenchen Ding, Zikun Wei, Sixiao Huang, Hao Yu 0001	An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Donghyuk Kim, Sanghyun Jeong, Joo-Young Kim 0001	Agamotto: A Performance Optimization Framework for CNN Accelerator With Row Stationary Dataflow.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda	Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Naina Gupta 0001, Arpan Jati, Anupam Chattopadhyay, Gautam Jha	Lightweight Hardware Accelerator for Post-Quantum Digital Signature CRYSTALS-Dilithium.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Jiawei Xu 0002, Jiangshan Fan, Baolin Nan, Chen Ding, Lirong Zheng 0001, Zhuo Zou, Yuxiang Huan	ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Tian Xia 0008, Boran Zhao, Jian Ma, Gelin Fu, Wenzhe Zhao, Nanning Zheng 0001, Pengju Ren	An Energy-and-Area-Efficient CNN Accelerator for Universal Powers-of-Two Quantization.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Siyu Zhang, Wendong Mao, Zhongfeng Wang 0001	An Efficient Accelerator Based on Lightweight Deformable 3D-CNN for Video Super-Resolution.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Chaolin Rao, Qing Wu 0001, Pingqiang Zhou, Jingyi Yu, Yuyao Zhang, Xin Lou	An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Zerong He, Teng Tian, Qizhe Wu, Xi Jin 0002	FTW-GAT: An FPGA-Based Accelerator for Graph Attention Networks With Ternary Weights.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Kaihang Sun, Zhaofang Li, Yanghan Zheng, Hao-Wen Kuo, Kuan-Pei Lee, Kea-Tiong Tang	An Area-Efficient Accelerator for Non-Maximum Suppression.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Lei Kang, Xu Yang 0017, Chi Zhang, Shuangming Yu, Runjiang Dou, Wenchang Li, Cong Shi 0003, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Xianghong Hu, Xuejiao Liu, Yu Liu 0007, Haowei Zhang, Xijie Huang, Xihao Guan, Luhong Liang, Chi-Ying Tsui, Xiaoming Xiong, Kwang-Ting Cheng	A Tiny Accelerator for Mixed-Bit Sparse CNN Based on Efficient Fetch Method of SIMO SPad.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Piljoo Choi, Dong Kyue Kim	Lightweight Polynomial Multiplication Accelerator for NTRU Using Shared SRAM.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Long Chen, Cai Li, Tao Wang, Junyi Qian, Weiwei Shan	A 1.23μJ/Inference, All-Digital Shuffle-Type Group-CNN Accelerator in 28nm CMOS With 85.8% Accuracy on CIFAR-10.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Rizwan Tariq Syed, Marko S. Andjelkovic, Markus Ulbricht 0002, Milos Krstic	Towards Reconfigurable CNN Accelerator for FPGA Implementation.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Zhiwang Guo, Deyang Chen, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Yixuan Liu, Haidong Tian, Xiankui Xiong, Keji Zhou, Xiaoyong Xue, Qi Liu 0010, Xiaoyang Zeng	An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Quan Cheng, Liuyao Dai, Mingqiang Huang, Ao Shen, Wei Mao 0002, Masanori Hashimoto, Hao Yu 0001	A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Miao Sun, Yingjie Cao, Jian Qian, Jie Li, Sifan Zhou, Ziyu Zhao, Yifan Wu, Tao Xia, Yajie Qin, Lei Qiu 0002, Shunli Ma, Patrick Yin Chiang, Shenglong Zhuo	A 40nm 2TOPS/W Depth-Completion Neural Network Accelerator SoC With Efficient Depth Engine for Realtime LiDAR Systems.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Zejian Liu, Gang Li 0015, Jian Cheng 0001	Efficient Accelerator/Network Co-Search With Circular Greedy Reinforcement Learning.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Yudeng Lin, Jianshi Tang, Bin Gao 0006, Qi Qin, Qingtian Zhang, He Qian, Huaqiang Wu	A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Subin Ki, Juntae Park, Hyun Kim 0001	Dedicated FPGA Implementation of the Gaussian TinyYOLOv3 Accelerator.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Zhongyu Zhao, Rujian Cao, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins	An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Yaolei Li, Jinshan Yue, Jingyu Wang, Chen Tang, Yifan He, Wenbin Jia, Kaiwei Zou, Lu Zhang, Huazhong Yang, Yongpan Liu	A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini	Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Jinyu Bai, Wenlu Xue, Yunqian Fan, Sifan Sun, Wang Kang 0001	Partial Sum Quantization for Computing-In-Memory-Based Neural Network Accelerator.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Deyang Chen, Zhiwang Guo, Jinbei Fang, Chenyang Zhao, Jingwen Jiang, Keji Zhou, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng	A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Ye Liu, Kun Huang, Neng Zhao, Jingyuan Li, Shuang Hao, Zili Huang, Xiuyuan Qi, Xinghao Wang, Liang Zhou, Liang Chang 0002, Jun Zhou 0017	BOHA: A High Performance VSLAM Backend Optimization Hardware Accelerator Using Recursive Fine-Grain H-Matrix Decomposition and Early-Computing With Approximate Linear Solver.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Annus Zulfiqar, Ben Pfaff, William Tu, Gianni Antichi, Muhammad Shahbaz 0001	The Slow Path Needs an Accelerator Too!	Comput. Commun. Rev.	2023	DBLP DOI BibTeX RDF
10	Menelaos Skontranis, George Sarantoglou, Kostas Sozos, Thomas Kamalakis, Charis Mesaritakis, Adonis Bogris	Multimode Fabry-Perot laser as a reservoir computing and extreme learning machine photonic accelerator.	Neuromorph. Comput. Eng.	2023	DBLP DOI BibTeX RDF
10	Charles Eckert, Arun Subramaniyan 0001, Xiaowei Wang, Charles Augustine, Ravishankar Iyer 0001, Reetuparna Das	Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Myat Thu Linn Aung, Daniel Gerlinghoff, Chuping Qu, Liwei Yang, Tian Huang, Rick Siow Mong Goh, Tao Luo 0014, Weng-Fai Wong	DeepFire2: A Convolutional Spiking Neural Network Accelerator on FPGAs.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Ziying Ni, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu 0001	HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Qiang Liu 0011, Yuhui Hao, Weizhuang Liu, Bo Yu 0014, Yiming Gan, Jie Tang 0003, Shaoshan Liu, Yuhao Zhu 0001	An Energy Efficient and Runtime Reconfigurable Accelerator for Robotic Localization.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Kevin Kiningham, Philip Alexander Levis, Christopher Ré	GRIP: A Graph Neural Network Accelerator Architecture.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Edward Hanson, Shiyu Li, Xuehai Qian, Hai Helen Li, Yiran Chen 0001	DyNNamic: Dynamically Reshaping, High Data-Reuse Accelerator for Compact DNNs.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Jiaqi Zhang 0002, Xiangru Chen, Sandip Ray	AINNS: All-Inclusive Neural Network Scheduling Via Accelerator Formalization.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Zhendong Zhang, Peng Liu 0016, Weidong Wang, Yingtao Jiang	RUPA: A High Performance, Energy Efficient Accelerator for Rule-Based Password Generation in Heterogenous Password Recovery System.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Seock-Hwan Noh, Jahyun Koo 0002, Seunghyun Lee, Jongse Park, Jaeha Kung	FlexBlock: A Flexible DNN Training Accelerator With Multi-Mode Block Floating Point Support.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Dong Eun Kim, Aayush Ankit, Cheng Wang, Kaushik Roy 0001	SAMBA: Sparsity Aware In-Memory Computing Based Machine Learning Accelerator.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Francesco Restuccia 0002, Marco Pagani, Alessandro Biondi 0001, Mauro Marinoni, Giorgio C. Buttazzo	Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Jin-Yi Lin, Shu-Yen Lin	Temperature-Prediction Based Rate-Adjusted Time and Space Mapping Algorithm for 3D CNN Accelerator Systems.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
10	Tao Li, Li Shen	A sparse matrix vector multiplication accelerator based on high-bandwidth memory.	Comput. Electr. Eng.	2023	DBLP DOI BibTeX RDF
10	Fatima Hameed Khan, Muhammad Adeel Pasha, Shahid Masud	Towards designing a hardware accelerator for 3D convolutional neural networks.	Comput. Electr. Eng.	2023	DBLP DOI BibTeX RDF
10	Bingyi Zhang, Hanqing Zeng, Viktor K. Prasanna	GraphAGILE: An FPGA-Based Overlay Accelerator for Low-Latency GNN Inference.	IEEE Trans. Parallel Distributed Syst.	2023	DBLP DOI BibTeX RDF
10	Raúl Taranco, José-María Arnau, Antonio González 0001	LOCATOR: Low-power ORB accelerator for autonomous cars.	J. Parallel Distributed Comput.	2023	DBLP DOI BibTeX RDF
10	N. Renugadevi, Stheya Julakanti, Sai Charan Vemula, Somya Bhatnagar, Shirisha Thangallapally	Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux-Demux pair.	Secur. Priv.	2023	DBLP DOI BibTeX RDF
10	Ming Liu 0022, Changchun Zhou, Siyuan Qiu, Yifan He, Hailong Jiao	CNN Accelerator at the Edge With Adaptive Zero Skipping and Sparsity-Driven Data Flow.	IEEE Trans. Circuits Syst. Video Technol.	2023	DBLP DOI BibTeX RDF
10	Ali Siddique, Muhammad Azhar Iqbal, Muhammad Aleem, Muhammad Arshad Islam	A 218 GOPS neural network accelerator based on a novel cost-efficient surrogate gradient scheme for pattern classification.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
10	Alberto Marchisio, Federico Teodonio, Antonello Rizzi, Muhammad Shafique 0001	ISMatch: A real-time hardware accelerator for inexact string matching of DNA sequences on FPGA.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
10	Yingchao Cui, Qing Liu, Yingbiao Yao, Xiaorong Xu, Wei Wu, Xin Xu	An area-efficient and low-latency elliptic curve scalar multiplication accelerator over prime field.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
10	Yean-Ru Chen, Tzu-Fan Wang, Si-Han Chen, Yi-Chun Kao	Empirical study on security verification and assessment of neural network accelerator.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
10	Svein Anders Tunheim, Lei Jiao 0001, Rishad A. Shafik, Alex Yakovlev, Ole-Christoffer Granmo	Convolutional Tsetlin Machine-based Training and Inference Accelerator for 2-D Pattern Classification.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
10	Haiying Yuan, Zhiyong Zeng	A sparse convolution neural network accelerator with bandwidth-efficient data loopback structure.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
10	Tolulope A. Odetola, Adewale Adeyemo, Faiq Khalid, Syed Rafay Hasan	FM-ModComp: Feature Map Modification and Hardware-Software Co-Comparison for secure hardware accelerator-based CNN inference.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
10	Kaisheng Shi, Mingwei Wang, Xin Tan, Qianghua Li, Tao Lei	Efficient Dynamic Reconfigurable CNN Accelerator for Edge Intelligence Computing on FPGA.	Inf.	2023	DBLP DOI BibTeX RDF
10	Ruidong Wu, Bing Liu 0022, Ping Fu, Haolin Chen	A Resource Efficient CNN Accelerator for Sensor Signal Processing Based on FPGA.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
10	Hamidreza Bolhasani, Somayyeh Jafarali Jassbi, Arash Sharifi	DLA-H: A Deep Learning Accelerator for Histopathologic Image Classification.	J. Digit. Imaging	2023	DBLP DOI BibTeX RDF
10	Shiqing Li, Shuo Huai, Weichen Liu	An Efficient Gustavson-Based Sparse Matrix-Matrix Multiplication Accelerator on Embedded FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
10	Jianan Mu, Yi Ren, Wen Wang 0007, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye 0001, Yuan Cao 0003, Huawei Li 0001, Xiaowei Li 0001	Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
10	Shien Zhu, Luan H. K. Duong, Hui Chen 0016, Di Liu 0002, Weichen Liu	FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
10	Weixiong Jiang, Heng Yu 0001, Fupeng Chen, Yajun Ha	AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF