Search results for "floorplan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Azadeh Davoodi, Ankur Srivastava 0001	Power-driven simultaneous resource binding and floorplanning: a probabilistic approach.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
11	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Chung-Kuan Cheng, Jun Gu	Buffer planning as an Integral part of floorplanning with consideration of routing congestion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
11	Lei Cheng 0001, Liang Deng, Martin D. F. Wong	Floorplanning for 3-D VLSI design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
11	Jia Wang 0003, Hai Zhou 0001	Interconnect estimation without packing via ACG floorplans.	ASP-DAC	2005	DBLP DOI BibTeX RDF
11	Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong	Optimal redistribution of white space for wire length minimization.	ASP-DAC	2005	DBLP DOI BibTeX RDF
11	Tung-Chieh Chen, Yao-Wen Chang	Modern floorplanning based on fast simulated annealing.	ISPD	2005	DBLP DOI BibTeX RDF	simulated annealing, floorplanning
11	Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003, Hsin-Hsien Ho	Modem floorplanning with abutment and fixed-outline constraints.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
11	Song Chen 0001, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng	VLSI block placement with alignment constraints based on corner block list.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
11	Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani	A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
11	Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh	Floorplanning with clock tree estimation.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
11	Yunfeng Wang, Jinian Bian, Xianlong Hong	Interconnect delay optimization via high level re-synthesis after floorplanning.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
11	Dongku Kang, Yiran Chen 0001, Kaushik Roy 0001	Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis.	ISQED	2005	DBLP DOI BibTeX RDF
11	Jing Liu 0006, Weicai Zhong, Licheng Jiao	Moving Block Sequence and Organizational Evolutionary Algorithm for General Floorplanning.	CIS (1)	2005	DBLP DOI BibTeX RDF
11	S. A. Moghaddam, Nasser Masoumi, Caro Lucas	A Stochastic Power-Supply Noise Reduction Technique Using Max-Flow Algorithm and Decoupling Capacitance.	IWSOC	2005	DBLP DOI BibTeX RDF
11	Shinn-Ying Ho, Shinn-Jang Ho, Yi-Kuang Lin, W. C.-C. Chu	An orthogonal simulated annealing algorithm for large floorplanning problems.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
11	Hao Li, Wai-Kei Mak, Srinivas Katkoori	Force-Directed Performance-Driven Placement Algorithm for FPGAs.	ISVLSI	2004	DBLP DOI BibTeX RDF
11	Richard Auletta	Expert System Perimeter Block Placement Floorplanning.	DATE	2004	DBLP DOI BibTeX RDF
11	Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh	Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.	ASP-DAC	2004	DBLP DOI BibTeX RDF
11	Zion Cien Shen, Chris C. N. Chu	Accurate and efficient flow based congestion estimation in floorplanning.	ASP-DAC	2004	DBLP DOI BibTeX RDF
11	Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003	Robust fixed-outline floorplanning through evolutionary search.	ASP-DAC	2004	DBLP DOI BibTeX RDF
11	Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu 0001, Alexander Zelikovsky	Multi-project reticle floorplanning and wafer dicing.	ISPD	2004	DBLP DOI BibTeX RDF	multi-project wafers, reticle design, wafer dicing
11	Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov	Unification of partitioning, placement and floorplanning.	ICCAD	2004	DBLP DOI BibTeX RDF
11	Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava 0001, Miodrag Potkonjak	Wire-length prediction using statistical techniques.	ICCAD	2004	DBLP DOI BibTeX RDF
11	Yan Feng, Dinesh P. Mehta	Constrained Floorplanning with Whitespace.	VLSI Design	2004	DBLP DOI BibTeX RDF
11	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani	Integrated floorplanning with buffer/channel insertion for bus-based designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
11	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Yici Cai, Chung-Kuan Cheng, Jun Gu	An integrated floorplanning with an efficient buffer planning algorithm.	ISPD	2003	DBLP DOI BibTeX RDF	floorplanning, buffer insertion, routability
11	Yangdong Deng, Wojciech Maly	Physical Design of the "2.5D" Stacked System.	ICCD	2003	DBLP DOI BibTeX RDF
11	Song Chen 0001, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu	Evaluating a bounded slice-line grid assignment in O(nlogn) time.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
11	Terry Tao Ye, Giovanni De Micheli	Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics.	ASAP	2003	DBLP DOI BibTeX RDF
11	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Bounding the efforts on congestion optimization for physical synthesis.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	optimization, logic synthesis, physical design, technology mapping, routing congestion
11	Russell Tessier	Fast placement approaches for FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	field-programmable gate arrays, synthesis, layout, Computer-aided design of VLSI
11	Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin	An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees.	DATE	2002	DBLP DOI BibTeX RDF
11	Juan de Vicente, Juan Lanchares, Román Hermida	FPGA Placement by Thermodynamic Combinatorial Optimization.	DATE	2002	DBLP DOI BibTeX RDF
11	Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang	Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.	ISQED	2002	DBLP DOI BibTeX RDF	Interconnect-Driven Floorplanning, Performance Optimization
11	Stelian Alupoaei, Srinivas Katkoori	Net Clustering Based Macrocell Placement.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Macrocell placement, net clustering, net placement, net prioritization, force-directed placement, iterative improvement
11	Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita	Chip size estimation based on wiring area.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
11	Xiaoping Tang, D. F. Wong 0001	Floorplanning with alignment and performance constraints.	DAC	2002	DBLP DOI BibTeX RDF	floorplanning, longest common subsequence, sequence pair
11	I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong 0001	Integrated power supply planning and floorplanning.	ASP-DAC	2001	DBLP DOI BibTeX RDF
11	Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani	Consistent floorplanning with super hierarchical constraints.	ISPD	2001	DBLP DOI BibTeX RDF
11	Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu	ECBL: an extended corner block list with solution space including optimum placement.	ISPD	2001	DBLP DOI BibTeX RDF
11	Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Subhas C. Nandy	Area(number)-balanced hierarchy of staircase channels with minimum crossing nets.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
11	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang	Slicing floorplans with range constraint.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
11	Florin Balasa, Koen Lampaert	Symmetry within the sequence-pair representation in the context ofplacement for analog design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
11	Dinesh P. Mehta, Naveed A. Sherwani	On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	mixed block and cell designs, floorplanning, rectilinear polygons
11	Milan Vasilko, Graham Benyon-Tinker	Automatic Temporal Floorplanning with Guaranteed Solution Feasibility.	FPL	2000	DBLP DOI BibTeX RDF
11	Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu	B*-Trees: a new representation for non-slicing floorplans.	DAC	2000	DBLP DOI BibTeX RDF
11	Robert P. Dick, Niraj K. Jha	MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis.	DATE	1999	DBLP DOI BibTeX RDF
11	Fung Yu Young, D. F. Wong 0001	Slicing Floorplans with Boundary Constraint.	ASP-DAC	1999	DBLP DOI BibTeX RDF
11	Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh	3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	3-D floorplanning, Reconfigurable computing, floorplanning
11	Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik	FlexRAM: Toward an Advanced Intelligent Memory System.	ICCD	1999	DBLP DOI BibTeX RDF
11	Darren C. Cronquist, Chris Fisher, Miguel E. Figueroa, Paul Franklin, Carl Ebeling	Architecture Design of Reconfigurable Pipelined Datapaths.	ARVLSI	1999	DBLP DOI BibTeX RDF	High-speed computation, Pipelining, Signal processing, Reconfigurable architectures, Configurable computing
11	Jim E. Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran	An Incremental Floorplanner.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
11	Pradeep Prabhakaran, Prithviraj Banerjee, Jim E. Crenshaw, Majid Sarrafzadeh	Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization.	VLSI Design	1999	DBLP DOI BibTeX RDF
11	S. A. Senouci, Aadil Amoura, Helena Krupnova, Gabriele Saucier	Timing Driven Floorplanning on Programmable Hierarchical Targets.	FPGA	1998	DBLP DOI BibTeX RDF
11	Jürgen Koehl, Ulrich Baur, Thomas Ludwig 0004, Bernhard Kick, Thomas Pflueger	A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset.	DATE	1998	DBLP DOI BibTeX RDF
11	John Marty Emmert, Akash Randhar, Dinesh Bhatia	Fast Floorplanning for FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
11	Subhashis Majumder, Subhas C. Nandy, Bhargab B. Bhattacharya	Partitioning VLSI Floorplans by Staircase Channels for Global Routing.	VLSI Design	1998	DBLP DOI BibTeX RDF	maxflow-mincut, algorithms, complexity, partitioning, NP-completeness, Global routing
11	Zinaida V. Apanovich, Alexander G. Marchuk	Top-Down Approach to Technology Migration for Full-Custom Mask Layouts.	VLSI Design	1998	DBLP DOI BibTeX RDF	Technology migration, decomposition, compaction, rerouting
11	Jianzhong Shi, Akash Randhar, Dinesh Bhatia	Macro Block Based FPGA Floorplanning.	VLSI Design	1997	DBLP DOI BibTeX RDF	macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design
11	Cheng-Hsi Chen, Ioannis G. Tollis	An Omega(k2) lower bound for area optimization of spiral floorplans.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
11	Takayuki Yamanouchi, Kazuo Tamakashi, Takashi Kambe	Hybrid floorplanning based on partial clustering and module restructuring.	ICCAD	1996	DBLP DOI BibTeX RDF	slicing structure, clustering, placement, floorplanning
11	Morteza Saheb Zamani, Graham R. Hellestrand	A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs.	IWANN	1995	DBLP DOI BibTeX RDF
11	Thomas Lengauer, Rolf Müller	Robust and accurate hierarchical floorplanning with integrated global wiring.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
11	Oliver Collins, Sam Dolinar, Robert J. McEliece, Fabrizio Pollara	A VLSI Decomposition of the deBruijn Graph.	J. ACM	1992	DBLP DOI BibTeX RDF	deBruijn graphs, graph decomposition
11	Linda Kwai-Lin Lau, Rajeev Jain, Henry Samueli, Henry T. Nicholas III, Etan G. Cohen	DDFSGEN.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
11	Christian Masson, Denis Barbier, Remy Escassut, Daniel Winer, Gregory Chevallier, Pierre François Zeegers	CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISP.	EURO-DAC	1990	DBLP DOI BibTeX RDF
11	Noritake Yonezawa, Nobuyuki Nishiguchi, Atsushi Etani, Fumiaki Tsukuda, Ryuichi Hashishita	A VLSI floorplanner based on "balloon" expansion.	EURO-DAC	1990	DBLP DOI BibTeX RDF
11	Dwight D. Hill, Don Shugard	Global Routing Considerations in a Cell Synthesis System.	DAC	1990	DBLP DOI BibTeX RDF
11	Shmuel Wimer, Israel Koren, Israel Cederbaum	Optimal aspect ratios of building blocks in VLSI.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
11	John D. Gabbe, P. A. Subrahmanyam	A Note on Clustering Modules for Floorplanning.	DAC	1989	DBLP DOI BibTeX RDF
11	Shmuel Wimer, Israel Koren, Israel Cederbaum	Optimal Aspect Ratios of Building Blocks in VLSI.	DAC	1988	DBLP BibTeX RDF
11	Antoni A. Szepieniec	Integrated placement/routing in sliced layouts.	DAC	1986	DBLP DOI BibTeX RDF
11	Hiroyuki Watanabe, Bryan D. Ackland	Flute - a floorplanning agent for full custom VLSI design.	DAC	1986	DBLP DOI BibTeX RDF