Search results for "manycore"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Andreas Haas, Christoph M. Kirsch, Michael Lippautz, Hannes Payer	How FIFO is your concurrent FIFO queue?	RACES@SPLASH	2012	DBLP DOI BibTeX RDF
16	Lakshminarayanan Renganarayana, Vijayalakshmi Srinivasan, Ravi Nair, Daniel A. Prener	Programming with relaxed synchronization.	RACES@SPLASH	2012	DBLP DOI BibTeX RDF
16	Paul E. McKenney	Beyond expert-only parallel programming?	RACES@SPLASH	2012	DBLP DOI BibTeX RDF
16	Junbo Wang 0001, Zixue Cheng, Isao Nishiyama, Yinghui Zhou	Design of a Safety Confirmation System Integrating Wireless Sensor Network and Smart Phones for Disaster.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Akira Imakura, Tetsuya Sakurai, Kohsuke Sumiyoshi, Hideo Matsufuru	An Auto-Tuning Technique of the Weighted Jacobi-Type Iteration Used for Preconditioners of Krylov Subspace Methods.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Wenfeng Shen, Liang Wang, Jie Li, Weimin Xu, Daming Wei, Xin Zhu 0001	Load-Prediction Parallelization for Computer Simulation of Electrocardiogram Based on GPU.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Xiaoping Huang, Xiaoya Fan, Shengbing Zhang, Yuhui Chen	DLWAP-buffer: A Novel HW/SW Architecture to Alleviate the Cache Coherence on Streaming-like Data in CMP.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Zheng Zhou 0002, Junjun Gu, Gang Qu 0001	Scheduling for Multi-core Processor under Process and Temperature Variation.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Akram Ben Ahmed, Abderazek Ben Abdallah	LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Naohito Nakasato, Hiroshi Daisaka, Toshiyuki Fukushige, Atsushi Kawai, Junichiro Makino, Tadashi Ishikawa, Fukuko Yuasa	GRAPE-MPs: Implementation of an SIMD for Quadruple/Hexuple/Octuple-Precision Arithmetic Operation on a Structured ASIC and an FPGA.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Zhenhe Ma, Tao Xu, Linlin Du, Zhongdi Chu, Jiangtao Lv, Fengwen Wang	Early Stage Chick Embryonic Heart Outflow Tract Flow Measurement Using High Speed 4D Optical Coherence Tomography.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Yu-Hsin Kuo, Po-An Tsai, Hao-Ping Ho, En-Jui Chang, Hsien-Kai Hsin, An-Yeu Andy Wu	Path-Diversity-Aware Adaptive Routing in Network-on-Chip Systems.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Yicheng Guan, Cisse Ahmadou Dit Adi, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie, Tsutomu Yoshinaga	Throttling Control for Bufferless Routing in On-chip Networks.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Salita Sombatsiri, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	On-chip Communication Buffer Architecture Optimization Considering Bus Width.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Kunio Takaya	Transputer-like Multicore Digital Signal Processing on the Array of ARM Cortex-M0 Microprocessors.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki	Removing Context Memory from a Multi-context Dynamically Reconfigurable Processor.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Hiroshi Saito, Tomohiro Yoneda, Yuichi Nakamura 0002	An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Li Wang, Jing Liu, Jingtong Hu, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Optimal Assignment for Tree-Structure Task Graph on Heterogeneous Multicore Systems Considering Time Constraint.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Satoshi Ito, Satoshi Ohshima, Takahiro Katagiri	SSG-AT: An Auto-tuning Method of Sparse Matrix-vector Multiplicataion for Semi-structured Grids - An Adaptation to OpenFOAM.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Yaohung M. Tsai, Weichung Wang, Ray-Bing Chen	Tuning Block Size for QR Factorization on CPU-GPU Hybrid Systems.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Xiang Li, Xuanya Li	Accurate Coverage of Complex Targets in Three-Dimensional Mobile Sensor Networks.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Muhammad Adeel Tajammul, Muhammad Ali Shami, Ahmed Hemani	Segmented Bus Based Path Setup Scheme for a Distributed Memory Architecture.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Shizuka Ishikawa, Asuka Tanaka, Toshiaki Miyazaki	Hardware Accelerator for BLAST.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Takuya Otsuka, Takashi Aoki, Eiichi Hosoya, Akira Onozawa	An Image Recognition System for Multiple Video Inputs over a Multi-FPGA System.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Junko Tazawa, Yuichi Okuyama, Yuichi Yaguchi, Toshiaki Miyazaki, Ryuichi Oka, Kenichi Kuroda	Hardware Implementation of Accumulated Value Calculation for Two-Dimensional Continuous Dynamic Programming.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano	Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Kazuya Matsumoto, Naohito Nakasato, Stanislav G. Sedukhin	Implementing a Code Generator for Fast Matrix Multiplication in OpenCL on the GPU.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Hong Yao, Zheng Zhao, Huawei Huang, Lei Cong	A Novel Data Transfer Scheme of Smart Grid and DTN.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Weihua Sheng, Artur Wiebe, Anastasia Stulova, Rainer Leupers, Bart Kienhuis, Johan Walters, Gerd Ascheid	FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Nicola Caselli, Alessandro Strano, Daniele Ludovici, Davide Bertozzi	Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Xuanya Li, Linlin Ci, Minghua Yang, Hongyu Wei, Chengping Tian, Bin Cheng	Multi-decision Making Based PSO Optimization in Airborne Mobile Sensor Network Deployment.	MCSoC	2012	DBLP DOI BibTeX RDF
16	Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga	Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA.	MCSoC	2012	DBLP DOI BibTeX RDF
16		Manycore.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
16	Rui Machado, Carsten Lojewski, Salvador Abreu, Franz-Josef Pfreundt	Unbalanced tree search on a manycore system using the GPI programming model.	Comput. Sci. Res. Dev.	2011	DBLP DOI BibTeX RDF
16	Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan	A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM.	Trans. High Perform. Embed. Archit. Compil.	2011	DBLP DOI BibTeX RDF
16	Kamesh Madduri, Eun-Jin Im, Khaled Z. Ibrahim, Samuel Williams 0001, Stéphane Ethier, Leonid Oliker	Gyrokinetic particle-in-cell optimization on emerging multi- and manycore platforms.	Parallel Comput.	2011	DBLP DOI BibTeX RDF
16	Lawrence Cayton	Accelerating Nearest Neighbor Search on Manycore Systems	CoRR	2011	DBLP BibTeX RDF
16	Seunghwa Kang, David Ediger, David A. Bader	Algorithm Engineering Challenges in Multicore and Manycore Systems.	it Inf. Technol.	2011	DBLP DOI BibTeX RDF
16	Michael J. Anderson, Bryan Catanzaro, Jike Chong, Ekaterina Gonina, Kurt Keutzer, Chao-Yue Lai, Mark Murphy, Bor-Yiing Su, Narayanan Sundaram	PALLAS: Mapping Applications onto Manycore.	Multiprocessor System-on-Chip	2011	DBLP DOI BibTeX RDF
16	Andreas Herkersdorf, Andreas Lankes, Michael Meitinger, Rainer Ohlendorf, Stefan Wallentowitz, Thomas Wild, Johannes Zeppenfeld	Hardware Support for Efficient Resource Utilization in Manycore Processor Systems.	Multiprocessor System-on-Chip	2011	DBLP DOI BibTeX RDF
16	Carl Ramey	TILE-Gx100 ManyCore processor: Acceleration interfaces and architecture.	Hot Chips Symposium	2011	DBLP DOI BibTeX RDF
16	Yonggon Kim, Hyunseok Lee, John Kim	An Alternative Memory Access Scheduling in Manycore Accelerators.	PACT	2011	DBLP DOI BibTeX RDF
16	Stefan Wallentowitz, Marcel Meyer, Thomas Wild, Andreas Herkersdorf	Accelerating collective communication in message passing on manycore System-on-Chip.	ICSAMOS	2011	DBLP DOI BibTeX RDF
16	Kerem Par, Oguz Tosun	Parallelization of particle filter based localization and map matching algorithms on multicore/manycore architectures.	Intelligent Vehicles Symposium	2011	DBLP DOI BibTeX RDF
16	Stefan Marr, Mattias De Wael, Michael Haupt, Theo D'Hondt	Which problems does a multi-language virtual machine need to solve in the multicore/manycore era?	SPLASH Workshops	2011	DBLP DOI BibTeX RDF
16	S. Tucker Taft, Joshua J. Bloch, Robert Bocchino, Sebastian Burckhardt, Hassan Chafi, Russ Cox, Benedict R. Gaster, Guy L. Steele Jr., David M. Ungar	Multicore, manycore, and cloud computing: is a new programming language paradigm required?	OOPSLA Companion	2011	DBLP DOI BibTeX RDF
16	Przemyslaw Stpiczynski	Solving Linear Recurrences on Hybrid GPU Accelerated Manycore Systems.	FedCSIS	2011	DBLP BibTeX RDF
16	Rainer Leupers, Lieven Eeckhout, Grant Martin, Frank Schirrmeister, Nigel P. Topham, Xiaotao Chen	Virtual Manycore platforms: Moving towards 100+ processor cores.	DATE	2011	DBLP DOI BibTeX RDF
16	Woomin Hwang, Ki-Woong Park, Kyu Ho Park	MN-GEMS: A Timing-Aware Simulator for a Cloud Node with Manycore, DRAM, and Non-volatile Memories.	IEEE CLOUD	2011	DBLP DOI BibTeX RDF	NVRAM, hybrid main memory, simulator, scheduling, virtual machines, memory contention
16	Yonghong Yan 0001, Sanjay Chatterjee, Daniel A. Orozco, Elkin Garcia, Zoran Budimlic, Jun Shirako, Robert S. Pavel, Guang R. Gao, Vivek Sarkar	Hardware and Software Tradeoffs for Task Synchronization on Manycore Architectures.	Euro-Par (2)	2011	DBLP DOI BibTeX RDF
16	David R. C. Hill	Distribution of Random Streams in Stochastic Models in the Age of Multi-Core and Manycore Processors.	PADS	2011	DBLP DOI BibTeX RDF
16	Mamadou Diao, Chrysostomos Nicopoulos, Jongman Kim	Large-Scale Semantic Concept Detection on Manycore Platforms for Multimedia Mining.	IPDPS	2011	DBLP DOI BibTeX RDF
16	Junghee Lee, Chrysostomos Nicopoulos, Yongjae Lee, Hyung Gyu Lee, Jongman Kim	Hardware-Based Job Queue Management for Manycore Architectures and OpenMP Environments.	IPDPS	2011	DBLP DOI BibTeX RDF
16	Yinglong Xia, Viktor K. Prasanna	Self-Adaptive Evidence Propagation on Manycore Processors.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
16	Joel C. Adams, Kathy Hoobeboom, Jonathan Walz	A cluster for CS education in the manycore era.	SIGCSE	2011	DBLP DOI BibTeX RDF
16	Ananda Basu, Saddek Bensalem, Marius Bozga, Paraskevas Bourgos, Mayur Maheshwari, Joseph Sifakis	Component Assemblies in the Context of Manycore.	FMCO	2011	DBLP DOI BibTeX RDF
16	Christian Fabre, Iuliana Bacivarov, Ananda Basu, Martino Ruggiero, David Atienza, Eric Flamand, Jean-Pierre Krimm, Julien Mottin, Lars Schor, Pratyush Kumar, Hoeseok Yang, Devesh B. Chokshi, Lothar Thiele, Saddek Bensalem, Marius Bozga, Luca Benini, Mohamed M. Sabry, Yusuf Leblebici, Giovanni De Micheli, Diego Melpignano	PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status.	FMCO	2011	DBLP DOI BibTeX RDF
16	Karl-Filip Faxén, John Ardelius	Manycore work stealing.	Conf. Computing Frontiers	2011	DBLP DOI BibTeX RDF
16	Brandon Beresini, Scott Ricketts, Michael Bedford Taylor	Unifying manycore and FPGA processing with the RUSH architecture.	AHS	2011	DBLP DOI BibTeX RDF
16	Jie Meng, Chao Chen 0003, Ayse Kivilcim Coskun, Ajay Joshi	Run-time energy management of manycore systems through reconfigurable interconnects.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
16	Kamesh Madduri, Khaled Z. Ibrahim, Samuel Williams 0001, Eun-Jin Im, Stéphane Ethier, John Shalf, Leonid Oliker	Gyrokinetic toroidal simulations on leading multi- and manycore HPC systems.	SC	2011	DBLP DOI BibTeX RDF
16	Sivasankaran Rajamanickam, Erik G. Boman, Michael A. Heroux	Poster: a hybrid-hybrid solver for manycore platforms.	SC Companion	2011	DBLP DOI BibTeX RDF
16	Chao Chen 0003, Jie Meng, Ayse K. Coskun, Ajay Joshi	Express Virtual Channels with Taps (EVC-T): A Flow Control Technique for Network-on-Chip (NoC) in Manycore Systems.	Hot Interconnects	2011	DBLP DOI BibTeX RDF
16	Charly Bechara, Nicolas Ventroux, Daniel Etiemble	AHDAM: An Asymmetric Homogeneous with Dynamic Allocator Manycore Chip.	Facing the Multicore-Challenge	2011	DBLP DOI BibTeX RDF
16	Charly Bechara	Study and design of a manycore architecture with multithreaded processors for dynamic embedded applications. (Etude et mise en œuvre d'une architecture multiprocesseur constituée de ressources de calculs multitâches pour les systèmes embarqués).		2011	RDF
16	Xiongfei Liao	Network-on-chip based manycore systems		2011	DOI RDF
16	Ami Marowka	Pitfalls and Issues of Manycore Programming.	Adv. Comput.	2010	DBLP DOI BibTeX RDF
16	Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar	Hardware-Enabled Dynamic Resource Allocation for Manycore Systems Using Bidding-Based System Feedback.	EURASIP J. Embed. Syst.	2010	DBLP DOI BibTeX RDF
16	Joaquín Franco, Gregorio Bernabé, Juan Fernández 0001, Manuel Ujaldon	Parallel 3D fast wavelet transform on manycore GPUs and multicore CPUs.	ICCS	2010	DBLP DOI BibTeX RDF
16	Dirk Ribbrock, Markus Geveler, Dominik Göddeke, Stefan Turek	Performance and accuracy of Lattice-Boltzmann kernels on multi- and manycore architectures.	ICCS	2010	DBLP DOI BibTeX RDF
16	Shenggang Chen, Shuming Chen, Shuwei Sun	P3-CABAC: A Nonstandard Tri-Thread Parallel Evolution of CABAC in the Manycore Era.	IEEE Trans. Circuits Syst. Video Technol.	2010	DBLP DOI BibTeX RDF
16	Stanimire Tomov, Jack J. Dongarra, Marc Baboulin	Towards dense linear algebra for hybrid GPU accelerated manycore systems.	Parallel Comput.	2010	DBLP DOI BibTeX RDF
16	Lin Huang 0002, Qiang Xu 0001	Economic Analysis of Testing Homogeneous Manycore Chips.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
16	Michael Boyer, David Tarjan, Kevin Skadron	Federation: Boosting per-thread performance of throughput-oriented manycore architectures.	ACM Trans. Archit. Code Optim.	2010	DBLP DOI BibTeX RDF
16	Matthias Christen, Olaf Schenk, Esra Neufeld, Maarten M. Paulides, Helmar Burkhart	Manycore Stencil Computations in Hyperthermia Applications.	Scientific Computing with Multicore and Accelerators	2010	DBLP DOI BibTeX RDF
16	Shubhabrata Sengupta, Mark J. Harris, Michael Garland, John D. Owens	Efficient Parallel Scan Algorithms for Manycore GPUs.	Scientific Computing with Multicore and Accelerators	2010	DBLP DOI BibTeX RDF
16	Hisham El-Shishiny, Erven Rohou (eds.)	Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies, IFMT '10, Saint-Malo, France, June 19, 2010	IFMT	2010	DBLP DOI BibTeX RDF
16	Dorothea Kolossa, Jike Chong, Steffen Zeiler, Kurt Keutzer	Efficient manycore CHMM speech recognition for audiovisual and multistream data.	INTERSPEECH	2010	DBLP DOI BibTeX RDF
16	David M. Ungar, Sam S. Adams	Harnessing emergence for manycore programming: early experience integrating ensembles, adverbs, and object-based inheritance.	SPLASH/OOPSLA Companion	2010	DBLP DOI BibTeX RDF
16	Ali Bakhoda, John Kim, Tor M. Aamodt	Throughput-Effective On-Chip Networks for Manycore Accelerators.	MICRO	2010	DBLP DOI BibTeX RDF
16	Chen Chen, Joseph B. Manzano, Ge Gan, Guang R. Gao, Vivek Sarkar	A Study of a Software Cache Implementation of the OpenMP Memory Model for Multicore and Manycore Architectures.	Euro-Par (2)	2010	DBLP DOI BibTeX RDF
16	Beniamino Di Martino, Fabrizio Petrini, Siegfried Benkner, Kirk W. Cameron, Dieter Kranzlmüller, Jakub Kurzak, Davide Pasetto, Jesper Larsson Träff	Multicore and Manycore Programming.	Euro-Par (2)	2010	DBLP DOI BibTeX RDF
16	Lin Huang 0002, Qiang Xu 0001	Characterizing the lifetime reliability of manycore processors with core-level redundancy.	ICCAD	2010	DBLP DOI BibTeX RDF
16	François Pêcheux, Amer Habib	Towards High-Level Executable Specifications of Heterogeneous Systems with SystemC-AMS: Application to a Manycore PCR-CE Lab on Chip for DNA Sequencing.	FDL	2010	DBLP BibTeX RDF
16	Etienne Faure, Mounir Benabdenbi, François Pêcheux	Distributed online software monitoring of manycore architectures.	IOLTS	2010	DBLP DOI BibTeX RDF
16	Alécio Pedro Delazari Binotto, Bernardo M. V. Pedras, Marcelo Götz, Arjan Kuijper, Carlos Eduardo Pereira, André Stork, Dieter W. Fellner	Effective Dynamic Scheduling on Heterogeneous Multi/Manycore Desktop Platforms.	SBAC-PAD (Workshops)	2010	DBLP DOI BibTeX RDF
16	David Andrews	Reconfigurable computing in the heterogeneous manycore Era.	HPCS	2010	DBLP DOI BibTeX RDF
16	Amer Habib, François Pêcheux	Modeling and simulation of a manycore PCR-CE lab-on-chip for DNA sequencing using SystemC/SystemC-AMS.	BMAS	2010	DBLP DOI BibTeX RDF
16	Markus Geveler, Dirk Ribbrock, Dominik Göddeke, Stefan Turek	Lattice-Boltzmann Simulation of the Shallow-Water Equations with Fluid-Structure Interaction on Multi- and Manycore Processors.	Facing the Multicore-Challenge	2010	DBLP DOI BibTeX RDF
16	Yinglong Xia, Viktor K. Prasanna, James Li	Hierarchical Scheduling of DAG Structured Computations on Manycore Processors with Dynamic Thread Grouping.	JSSPP	2010	DBLP DOI BibTeX RDF
16	Jike Chong	Pattern-Oriented Application Frameworks for Domain Experts to Effectively Utilize Highly Parallel Manycore Microprocessors.		2010	RDF
16	Ahmed El-Mahdy 0002, Hisham El-Shishiny	Efficient parallel selective separable-kernel convolution on heterogeneous processors.	IFMT	2010	DBLP DOI BibTeX RDF
16	Augusto Vega, Alejandro Rico, Felipe Cabarcas, Alex Ramírez, Mateo Valero	Comparing last-level cache designs for CMP architectures.	IFMT	2010	DBLP DOI BibTeX RDF
16	Junli Gu, Rakesh Kumar 0002, Steven S. Lumetta, Yihe Sun	Accelerating data movement on future chip multi-processors.	IFMT	2010	DBLP DOI BibTeX RDF
16	Nicolas Ventroux, Raphaël David	SCMP architecture: an asymmetric multiprocessor system-on-chip for dynamic applications.	IFMT	2010	DBLP DOI BibTeX RDF
16	Kamil Kedzierski, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero	Power and performance aware reconfigurable cache for CMPs.	IFMT	2010	DBLP DOI BibTeX RDF
16	Abdullah Kayi, Tarek A. El-Ghazawi	An adaptive cache coherence protocol for chip multiprocessors.	IFMT	2010	DBLP DOI BibTeX RDF
16	Anurag Negi, M. M. Waliullah, Per Stenström	LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems.	IFMT	2010	DBLP DOI BibTeX RDF
16	István Lorentz, Mihaela Malita, Razvan Andonie	Fitting FFT onto an energy efficient massively parallel architecture.	IFMT	2010	DBLP DOI BibTeX RDF