Search results for "jitter"

Hits ?▲	Authors	Title	Venue	Year	Link
12	Hyman Shanan, Declan Dalton, Vamshi Chillara, Pablo Dato	A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time.	ISSCC	2022	DBLP DOI BibTeX RDF
12	Keita Yasutomi, Tatsuki Furuhashi, Koki Sagawa, Taishi Takasawa, Keiichiro Kagawa, Shoji Kawahito	A 38µm Range Precision Time-of-Flight CMOS Range Line Imager with Gating Driver Jitter Reduction Using Charge-Injection Pseudo Photocurrent Reference.	ISSCC	2022	DBLP DOI BibTeX RDF
12	Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino	A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching.	ISSCC	2022	DBLP DOI BibTeX RDF
12	Chanwoong Hwang, Hangi Park, Taeho Seong, Jaehyouk Choi	A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector.	ISSCC	2022	DBLP DOI BibTeX RDF
12	Sonam Sadhukhan, Pranav Kumar, Arpan Thakkar, Apoorva Bhatia, Saurabh Saxena	A Class-C Injection-Locked Tripler with 48 dB Sub-Harmonic Suppression and 15 fs Additive RMS Jitter in 0.13μm BiCMOS Process.	ISCAS	2022	DBLP DOI BibTeX RDF
12	Yu Zhao, Behzad Razavi	Phase Noise Integration Limits for Jitter Calculation.	ISCAS	2022	DBLP DOI BibTeX RDF
12	Xi Wang, Wei Wei 0030, Xiyi Weng, Danyang Wang, Jiawang Wei, Weilin Xie, Yi Dong	Elimination of the PMD Related Delay Jitter in an Ultra-Stable Microwave Signal Distribution System.	OFC	2022	DBLP BibTeX RDF
12	Prateek Agnihotri	An efficient analysis for True Random number generators using A Postprocessor, Jitter Metastability, Tree-Based Interleaver & CMOS inverter prototype technology.	iSES	2022	DBLP DOI BibTeX RDF
12	Yung-Chuan Su, Shi-Yu Huang	Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital Converter.	ISOCC	2022	DBLP DOI BibTeX RDF
12	Fern Nee Tan, Li Wern Chew, Ling Li Ong	Determining PCIe5 Jitter Margin using SIPI Co-Sim.	ISOCC	2022	DBLP DOI BibTeX RDF
12	Zhiyuan Cheng 0011, Zhiguo Li, Zhou Ji, Peipei Yan, Aili Xia	Quantitative atmospheric phase jitter simulating research of optic field imaging.	ICCIR	2022	DBLP DOI BibTeX RDF
12	Jithin Kallukalam Sojan, K. Haribabu 0001	Monitoring Jitter in Software Defined Networks.	AINA (2)	2022	DBLP DOI BibTeX RDF
12	Santunu Sarangi, Indranil Som, T. K. Bhattacharyya	A 10 Gb/s On-chip Jitter Measurement Circuit Based on Transition Region Scanning Method.	VLSID	2022	DBLP DOI BibTeX RDF
12	Moaaz Hudhud Mughrabi, Aunnoy K. Mutasim, Wolfgang Stuerzlinger, Anil Ufuk Batmaz	My Eyes Hurt: Effects of Jitter in 3D Gaze Tracking.	VR Workshops	2022	DBLP DOI BibTeX RDF
12	Dimitris Kriempardis, Panagiotis J. Gripeos, Efstratios C. Kapotis, Hector E. Nistazakis, Andreas D. Tsigopoulos, Christos K. Volos	Outage Performance of FSO Links with Chirped Gaussian Pulses and Truncated Modeled Time Jitter.	MOCAST	2022	DBLP DOI BibTeX RDF
12	Flavien Ronteix-Jacquet	Reducing latency and jitter in 5G radio access networks. (Réduction de la latence et de la gigue dans le réseau d'accès radio 5G).		2022	RDF
12	Long Quang Tran, Peter J. Radcliffe, Liuping Wang	Simulation is essential for embedded control systems with task jitter.	Des. Autom. Embed. Syst.	2021	DBLP DOI BibTeX RDF
12	Huici Wu, Hanjie Li, Zhiqing Wei, Ning Zhang 0007, Xiaofeng Tao	Secrecy Performance Analysis of Air-to-Ground Communication With UAV Jitter and Multiple Random Walking Eavesdroppers.	IEEE Trans. Veh. Technol.	2021	DBLP DOI BibTeX RDF
12	Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang Won Son, Thomas Byunghak Cho	A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
12	Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi	A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
12	Yusuf Cinar, Peter Pocta, Desmond Chambers, Hugh Melvin	Improved Jitter Buffer Management for WebRTC.	ACM Trans. Multim. Comput. Commun. Appl.	2021	DBLP DOI BibTeX RDF
12	Cheng Shi, Zhi-Kang Ni, Jun Pan, Zhijie Zheng, Shengbo Ye, Guangyou Fang	A Method for Reducing Timing Jitter's Impact in Through-Wall Human Detection by Ultra-Wideband Impulse Radar.	Remote. Sens.	2021	DBLP DOI BibTeX RDF
12	Jianing Song, Zhaoxiang Zhang 0002, Akira Iwasaki, Jihe Wang, Jun Sun, Yue Sun	An Augmented $H_\infty$ Filter for Satellite Jitter Estimation Based on ASTER/SWIR and Blurred Star Images.	IEEE Trans. Aerosp. Electron. Syst.	2021	DBLP DOI BibTeX RDF
12	Tianchi Wang, Haiyang Wang, Wei Chen, Tao Huang	Optimization of a Nanosecond Pre-Ionization Switch's Breakdown Jitter Characteristic Based on a Probability Distribution Model of Electron Avalanche's Initiation.	IEEE Access	2021	DBLP DOI BibTeX RDF
12	Jinoo Joung, Juhyeok Kwon	Zero Jitter for Deterministic Networks Without Time-Synchronization.	IEEE Access	2021	DBLP DOI BibTeX RDF
12	Yin Sun, Jongjoo Lee, Chulsoon Hwang	A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
12	Pierpaolo Palestri, Ahmed Elnaqib, Davide Menin, Klaid Shyti, Francesco Brandonisio, Andrea Bandiziol, Davide Rossi, Roberto Nonis	Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
12	Kazunori Takahashi, Roger Roberts, Zhen Jiang, Babak Memarzadeh	Statistical Evaluation of Signal-to-Noise Ratio and Timing Jitter in Equivalent-Time Sampling Signals.	IEEE Trans. Instrum. Meas.	2021	DBLP DOI BibTeX RDF
12	Sanaz Salem, Mohsen Saneei, Dariush Abbasi-Moghadam	Jitter Modeling in Digital CDR with Quantization Noise Analysis.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
12	Jun Pan 0001, Guo Ye, Ying Zhu 0002, Xiaolin Song, Fen Hu, Chi Zhang, Mi Wang	Jitter Detection and Image Restoration Based on Continue Dynamic Shooting Model for High-Resolution TDI CCD Satellite Images.	IEEE Trans. Geosci. Remote. Sens.	2021	DBLP DOI BibTeX RDF
12	Samuel Wagner, Brian M. Worthmann, Anh-Vu Pham	Minimizing Timing Jitter's Impact on Ground-Penetrating Radar Array Coupling Signals.	IEEE Trans. Geosci. Remote. Sens.	2021	DBLP DOI BibTeX RDF
12	Behzad Razavi	Jitter-Power Trade-Offs in PLLs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
12	Zunsong Yang, Yong Chen 0005, Pui-In Mak, Rui Paulo Martins	A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
12	Xinyu Wang, Huaguo Liang, Yanjie Wang, Liang Yao, Yang Guo, Maoxiang Yi, Zhengfeng Huang, Haochen Qi, Yingchun Lu	High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
12	Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina	Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
12	Shun-Chi Chang, Shen-Iuan Liu	A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
12	Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu	A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
12	Antonino Sferlazza, Sophie Tarbouriech, Luca Zaccarian	State observer with Round-Robin aperiodic sampled measurements with jitter.	Autom.	2021	DBLP DOI BibTeX RDF
12	Shahram Modanlou, Gholamreza Ardeshir, Mohammad Gholami	Analysis and design of a low jitter delay-locked loop using lock state detector.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
12	Hossein Yaghobi, Javad Tavakoli, Samad Sheikhaei	A 1.2 GHz jitter-peaking-free Integer-N PLL.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
12	Shahram Modanlou, Gholamreza Ardeshir, Mohammad Gholami	A low power and jitter delay cell with pulse width modulation for wide range delay lock loops.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
12	Zhicheng Cai, Chenglei Peng, Sidan Du	Jitter: Random Jittering Loss Function.	CoRR	2021	DBLP BibTeX RDF
12	Markku-Juhani O. Saarinen	On Entropy and Bit Patterns of Ring Oscillator Jitter.	CoRR	2021	DBLP BibTeX RDF
12	Megha Sahu, Snigdha Damle, Arzad Alam Kherani	End-to-end uplink delay jitter in LTE systems.	Wirel. Networks	2021	DBLP DOI BibTeX RDF
12	Markku-Juhani O. Saarinen	On Entropy and Bit Patterns of Ring Oscillator Jitter.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
12	Han Pu, Tianqiang Huang, Bin Weng 0001, Feng Ye, Chenbin Zhao	Overcome the Brightness and Jitter Noises in Video Inter-Frame Tampering Detection.	Sensors	2021	DBLP DOI BibTeX RDF
12	Daniel Gis, Nils Büscher, Christian Haubelt	Investigation of Timing Behavior and Jitter in a Smart Inertial Sensor Debugging Architecture.	Sensors	2021	DBLP DOI BibTeX RDF
12	Zilin Wang, Zhaoxiang Zhang 0002, Limin Dong, Guodong Xu	Jitter Detection and Image Restoration Based on Generative Adversarial Networks in Satellite Images.	Sensors	2021	DBLP DOI BibTeX RDF
12	Shi Zuo, Jianzhong Zhao, Yumei Zhou	A 0.8 V, 5.3-5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and -251.6 dB FoM.	Sensors	2021	DBLP DOI BibTeX RDF
12	Jiahao Chen, Haoming Li 0004, Tengjia Wang, Zhiyu Wang, Hua Chen 0003, Jiarui Liu 0001, Faxin Yu	A 92 fsrms jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control.	IEICE Electron. Express	2021	DBLP DOI BibTeX RDF
12	Nan Ren, Zaiming Fu, Dandan Zhou, Dexuan Kong, Hanglin Liu, Shulin Tian	Jitter Decomposition Meets Machine Learning: 1D-Convolutional Neural Network Approach.	IEEE Commun. Lett.	2021	DBLP DOI BibTeX RDF
12	Juan Manuel Miramont, Marcelo Alejandro Colominas, Gastón Schlotthauer	Voice Jitter Estimation Using High-Order Synchrosqueezing Operators.	IEEE ACM Trans. Audio Speech Lang. Process.	2021	DBLP DOI BibTeX RDF
12	Rémi Helleboid, Denis Rideau, Isobel Nicholson, Norbert Moussy, Olivier Saxod, Marie Basset, Jérémy Grebot, Antonin Zimmerman, Bastien Mamdy, Dominique Golanski, Megan Agnew, Sara Pellegrini, Mathieu Sicre	Comprehensive modeling and characterization of Photon Detection Efficiency and Jitter in advanced SPAD devices.	ESSDERC	2021	DBLP DOI BibTeX RDF
12	Flavien Ronteix-Jacquet	On Radio Access Network Uplink Latency and Jitter : Measurements and Analysis.	ITC	2021	DBLP BibTeX RDF
12	Rahul N. Gore, Elena Lisova, Johan Åkerberg, Mats Björkman	Delay and Jitter Analysis in Industrial Control Systems: A Paper Mill Case Study.	WFCS	2021	DBLP DOI BibTeX RDF
12	Therdpong Daengsi, Patsita Sirawongphatsara, Pongpisit Wuttidittachotti	Proposed QoE Models Associated with Delay and Jitter Using Subjective Approach and Applications for 4G and 5G Networks.	CommNet	2021	DBLP DOI BibTeX RDF
12	Yudong Huang, Shuo Wang 0006, Binwei Wu, Tao Huang 0005, Yunjie Liu 0001	TACQ: Enabling Zero-jitter for Cyclic-Queuing and Forwarding in Time-Sensitive Networks.	ICC	2021	DBLP DOI BibTeX RDF
12	Joana Fernandes, Pedro Henrique Borghi, Diamantino Silva Freitas, João Paulo Teixeira 0002	Optimization of Glottal Onset Peak Detection Algorithm for Accurate Jitter Measurement.	OL2A	2021	DBLP DOI BibTeX RDF
12	Marco Orna, Dominique Morche, Andrea Baschirotto, Emmanuel Allier, Patrick Arno	Quantitative Jitter Simulations and FIR-DAC sizing for Single-Bit Continuous Time Sigma Delta Modulators.	LASCAS	2021	DBLP DOI BibTeX RDF
12	Giulia Acconcia, Massimo Ghioni, Ivan Rech	4.3ps rms jitter time to amplitude converter in 350nm Si-Ge technology.	EBCCSP	2021	DBLP DOI BibTeX RDF
12	Alessio Di Pasquo, Enrico Monaco, Claudio Nani, Luca Fanucci	Delay-lines jitter modeling and efficiency analysis in FinFET technology.	ICECS	2021	DBLP DOI BibTeX RDF
12	Yan Zhang 0050, Chia-Jen Liang, Christopher Chen, Andrew Liu, Jason Woo, Sudhakar Pamarti, Chih-Kong Ken Yang, Mau-Chung Frank Chang	A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS.	ESSCIRC	2021	DBLP DOI BibTeX RDF
12	Muhamed F. Allam, Ahmed E. AbdelRahman, Hesham Omran, Sameh A. Ibrahim	Novel Decimation Topology with Improved Jitter Performance for Clock and Data Recovery Systems.	NEWCAS	2021	DBLP DOI BibTeX RDF
12	Puneet Arora, Jai Narayan Tripathi, Hitesh Shrimali	Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters due to Periodic Fluctuations.	NEWCAS	2021	DBLP DOI BibTeX RDF
12	Ahmed Elmallah, Junheng Zhu, Amr Khashaba, Karim M. Megawer, Ahmed Elkholy, Pavan Kumar Hanumolu	A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction.	CICC	2021	DBLP DOI BibTeX RDF
12	Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie	A 2.7mW 45fsrms-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications.	CICC	2021	DBLP DOI BibTeX RDF
12	Markku-Juhani O. Saarinen	On Entropy and Bit Patterns of Ring Oscillator Jitter.	AsianHOST	2021	DBLP DOI BibTeX RDF
12	Hangi Park, Chanwoong Hwang, Taeho Seong, Yongsun Lee, Jaehyouk Choi	A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM.	ISSCC	2021	DBLP DOI BibTeX RDF
12	Mario Mercandelli, Alessio Santiccioli, Simone Mattia Dartizio, Abanob Shehata, Francesco Tesolin, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea Leonardo Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino	A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.	ISSCC	2021	DBLP DOI BibTeX RDF
12	Edwin Thaller, Run Levinger, Evgeny Shumaker, Aryeh Farber, Sergey Bershansky, Nir Geron, Ashoke Ravi, Rotem Banin, Jasmin Kadry, Gil Horovitz, Christian Krassnitzer, Christoph Duller, Patrick Torta, Mark Elzinga, Kamran Azadet	A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS.	ISSCC	2021	DBLP DOI BibTeX RDF
12	Seyeon Yoo, Suneui Park, Seojin Choi, Yoonseo Cho, Heein Yoon, Chanwoong Hwang, Jaehyouk Choi	An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS.	ISSCC	2021	DBLP DOI BibTeX RDF
12	Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Pak-Kim Lau, Lei Chen, Sang Won Son, Thomas Byunghak Cho	32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels.	ISSCC	2021	DBLP DOI BibTeX RDF
12	Juyeop Kim, Yongwoo Jo, Younghyun Lim, Taeho Seong, Hangi Park, Seyeon Yoo, Yongsun Lee, Seojin Choi, Jaehyouk Choi	32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique.	ISSCC	2021	DBLP DOI BibTeX RDF
12	Alessio Santiccioli, Mario Mercandelli, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino	32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.	ISSCC	2021	DBLP DOI BibTeX RDF
12	Chun-Yu Lin 0002, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin	29.5 A 0.008mm2 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms Jitter Based on Replica-DTC-Free Background Calibration.	ISSCC	2021	DBLP DOI BibTeX RDF
12	Guanrong Hou, Behzad Razavi	A 56-Gb/s 8-mW PAM4 CDR/DMUX with High Jitter Tolerance.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
12	Yu Zhao, Behzad Razavi	A 19-GHz PLL with 20.3-fs Jitter.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
12	Panagiotis J. Gripeos, Hector E. Nistazakis, George K. Varotsos, Wilfried Gappmair, Andreas D. Tsigopoulos	3Time Jitter Influence on the Performance of PPM or PAM SIMO FSO Links over M-Turbulence Channels.	ConTEL	2021	DBLP DOI BibTeX RDF
12	Alhussain Almarhabi, Hatim Alhazmi, Abdullah Samarkandi, Mofadal Alymani, Mohsen H. Alhazmi, Yu-Dong Yao	QAM Signal Classification and Timing Jitter Identification Based on Eye Diagrams and Deep Learning.	WOCC	2021	DBLP DOI BibTeX RDF
12	Chia-Chen Chang, Yu-Tung Chin, Hossameldin A. Ibrahim, Kang-Yu Chang, Shyh-Jye Jou	A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO.	ISCAS	2021	DBLP DOI BibTeX RDF
12	Woorham Bae	State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey.	ISCAS	2021	DBLP DOI BibTeX RDF
12	Patrick Kurth, Kai Misselwitz, Urs Hecht, Friedel Gerfers	A 56 GHz 19 fs RMS-Jitter Sub-Sampling Phase-Locked Loop for 112 Gbit/s Transceivers.	ISCAS	2021	DBLP DOI BibTeX RDF
12	Auejin Ham, Junsu Lim, Sunjun Kim	Do We Need a Faster Mouse? Empirical Evaluation of Asynchronicity-Induced Jitter.	UIST	2021	DBLP DOI BibTeX RDF
12	Tao Liu, Fangxu Lv, Bin Liang, Heming Wang, Jianye Wang, Miaomiao Wu	An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits.	ASICON	2021	DBLP DOI BibTeX RDF
12	Junghoon Jin, Seungjun Kim, Sunguk Choi, Pil-Ho Lee, Sang-jae Rhee, Ki-hwan Choi, Jongsun Kim	A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL.	ISOCC	2021	DBLP DOI BibTeX RDF
12	Zhicheng Cai, Chenglei Peng, Sidan Du	Jitter: Random Jittering Loss Function.	IJCNN	2021	DBLP DOI BibTeX RDF
12	Toerless Eckert, Alexander Clemm, Stewart Bryant	gLBF: Per-Flow Stateless Packet Forwarding with Guaranteed Latency and Near-Synchronous Jitter.	CNSM	2021	DBLP DOI BibTeX RDF
12	Souradip Sen, Utkarsh Upadhyaya, Krishna Reddy Kondreddy, Arun Goyal, Sandeep Goyal, Shalabh Gupta	A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology.	VLSID	2021	DBLP DOI BibTeX RDF
12	Zhaoxiang Zhang 0002, Qing Zhou, Yuelei Xu, Linhua Ma, Akira Iwasaki	Remote Sensing Image Jitter Restoration Based on Deep Generative Adversarial Network.	IGARSS	2021	DBLP DOI BibTeX RDF
12	Dong-Hyun Yoon, Dong-Kyu Jung, Kiho Seong, Tae-Hyeok Eom, Jae-Soub Han, Ju Eon Kim, Tony Tae-Hyoung Kim, Kwang-Hyun Baek	A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement.	A-SSCC	2021	DBLP DOI BibTeX RDF
12	Khoi T. Phan, Yue Chao, Howard C. Luong	A 1.92GHz-3.84GHz 0.74ps-1.09ps-Jitter Inductor-less Injection-Locked Frequency Synthesizer with Automatic Frequency Selection and Timing Alignment.	A-SSCC	2021	DBLP DOI BibTeX RDF
12	Mario Mercandelli, Luca Bertulessi, Carlo Samori, Salvatore Levantino	A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter.	A-SSCC	2021	DBLP DOI BibTeX RDF
12	Thomas Hartley, Kirill A. Sidorov, Christopher Willis, A. David Marshall	Jitter-CAM: Improving the Spatial Resolution of CAM-Based Explanations.	BMVC	2021	DBLP BibTeX RDF
12	Jiahao Ma, Jiawei Zhang 0004, Jim Zou, Hao Yu 0013, Tarik Taleb, Yaojia Dong, Yuefeng Ji	Demonstration of Latency Control Label-Based Bounded-Jitter Scheduling in a Bridged Network for Industrial Internet.	ECOC	2021	DBLP DOI BibTeX RDF
12	Panagiotis J. Gripeos, Hector E. Nistazakis, Evgenia Roditi, George D. Roumelas, George S. Tombras, Christos K. Volos	On the BER Performance of OOK FSO Links with Receivers' Diversity and Time Jitter over Strong Turbulence Channels.	MOCAST	2021	DBLP DOI BibTeX RDF
12	Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon	A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
12	Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang	A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
12	Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Shahaboddin Moazzeni, Ralph Mason, Raleigh Smith	A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
12	Cheng-Hsueh Tsai, Zhiwei Zong, Federico Pepe, Giovanni Mangraviti, Jan Craninckx, Piet Wambacq	Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
12	Alessio Santiccioli, Mario Mercandelli, Luca Bertulessi, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino	A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF