Search results for "ARC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Fei Xia, Yong Dou, Jinbo Xu	Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension.	ARC	2008	DBLP DOI BibTeX RDF
1	Carlo Galuzzi, Koen Bertels	The Instruction-Set Extension Problem: A Survey.	ARC	2008	DBLP DOI BibTeX RDF
1	Vanderlei Bonato, Eduardo Marques, George A. Constantinides	A Parallel Hardware Architecture for Image Feature Detection.	ARC	2008	DBLP DOI BibTeX RDF
1	David B. Thomas, Wayne Luk, Michael Stumpf	Reconfigurable Hardware Acceleration of Canonical Graph Labelling.	ARC	2007	DBLP DOI BibTeX RDF
1	Mazen A. R. Saghir, Rawan Naous	A Configurable Multi-ported Register File Architecture for Soft Processor Cores.	ARC	2007	DBLP DOI BibTeX RDF
1	Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho	Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture.	ARC	2007	DBLP DOI BibTeX RDF	adaptive pipeline, processor, Asynchronous design
1	Jean-Luc Beuchat, Takanori Miyoshi, Yoshihito Oyama, Eiji Okamoto	Multiplication over Fpm on FPGA: A Survey.	ARC	2007	DBLP DOI BibTeX RDF
1	Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis	Designing Heterogeneous FPGAs with Multiple SBs.	ARC	2007	DBLP DOI BibTeX RDF
1	Jae Young Hur, Todor P. Stefanov, Stephan Wong, Stamatis Vassiliadis	Systematic Customization of On-Chip Crossbar Interconnects.	ARC	2007	DBLP DOI BibTeX RDF
1	Javier Díaz 0001, Eduardo Ros 0001, Sonia Mota, Richard R. Carrillo	Image Processing Architecture for Local Features Computation.	ARC	2007	DBLP DOI BibTeX RDF	quadrature filters, local image phase, orientation and energy, Real-time image processing, fixed point arithmetic
1	Yoshiki Yamaguchi, Kenji Kanazawa, Yoshiharu Ohke, Tsutomu Maruyama	An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma.	ARC	2007	DBLP DOI BibTeX RDF
1	Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi	Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping.	ARC	2007	DBLP DOI BibTeX RDF
1	César Torres-Huitzil, Bernard Girau, Adrien Gauffriau	Hardware/Software Codesign for Embedded Implementation of Neural Networks.	ARC	2007	DBLP DOI BibTeX RDF
1	Joonseok Park, Pedro C. Diniz	Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations.	ARC	2007	DBLP DOI BibTeX RDF	scalar replacement, loop splitting, loop interchange, Field Programmable Gate Arrays (FPGA), Reconfigurable Computing, data reuse
1	Carlos Raimundo Erig Lima, Heitor S. Lopes, Maiko R. Moroz, Ramon M. Menezes	Multiple Sequence Alignment Using Reconfigurable Computing.	ARC	2007	DBLP DOI BibTeX RDF
1	Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis	A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions.	ARC	2007	DBLP DOI BibTeX RDF
1	Yong-Min Lee, Chang-Seok Choi, Seung-Gon Hwang, Hyun Dong Kim, Chul Hong Min, Jaehyun Park 0003, Hanho Lee, Tae-Seon Kim, Chong Ho Lee	Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications.	ARC	2007	DBLP DOI BibTeX RDF
1	Edgar Ferrer, Dorothy Bollman, Oscar Moreno	A Fast Finite Field Multiplier.	ARC	2007	DBLP DOI BibTeX RDF
1	Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, João M. P. Cardoso (eds.)	Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007.	ARC	2007	DBLP DOI BibTeX RDF
1	Patrick Rocke, Brian McGinley, Fearghal Morgan, John Maher	Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller.	ARC	2007	DBLP DOI BibTeX RDF	Genetic Algorithm, Evolutionary Computation, Reconfigurable Hardware, Spiking Neural Networks, FPAA
1	Séamas McGettrick, Dermot Geraghty, Ciarán McElroy	Searching the Web with an FPGA Based Search Engine.	ARC	2007	DBLP DOI BibTeX RDF
1	Jae Young Hur, Stephan Wong, Stamatis Vassiliadis	Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs.	ARC	2007	DBLP DOI BibTeX RDF
1	Jae-Jin Lee, Dong-Guk Hwang, Gi-Yong Song	Design of a Reversible PLD Architecture.	ARC	2007	DBLP DOI BibTeX RDF
1	Francisco Rodríguez-Henríquez, Guillermo Morales-Luna, Nazar Abbas Saqib, Nareli Cruz Cortés	A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm.	ARC	2007	DBLP DOI BibTeX RDF
1	Matteo Tomasi, Javier Díaz 0001, Eduardo Ros 0001	Real Time Architectures for Moving-Objects Tracking.	ARC	2007	DBLP DOI BibTeX RDF	colour segmentation, motion estimation, object tracking, Real-time image processing
1	João Bispo, Ioannis Sourdis, João M. P. Cardoso, Stamatis Vassiliadis	Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues.	ARC	2007	DBLP DOI BibTeX RDF
1	Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev	Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array.	ARC	2007	DBLP DOI BibTeX RDF
1	Wagner Rodrigo Weinert, César Manuel Vargas Benítez, Heitor S. Lopes, Carlos Raimundo Erig Lima	Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing.	ARC	2007	DBLP DOI BibTeX RDF
1	Xiaodong Yang 0002, Shengmei Mou, Yong Dou	FPGA-Accelerated Molecular Dynamics Simulations: An Overview.	ARC	2007	DBLP DOI BibTeX RDF
1	Edson Pedro Ferlin, Heitor S. Lopes, Carlos Raimundo Erig Lima, Ederson Cichaczewski	Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits.	ARC	2007	DBLP DOI BibTeX RDF
1	Nicolas Hervé, Daniel Ménard, Olivier Sentieys	About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations.	ARC	2007	DBLP DOI BibTeX RDF
1	Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic	MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture.	ARC	2007	DBLP DOI BibTeX RDF
1	Nilton B. Armstrong, Heitor S. Lopes, Carlos Raimundo Erig Lima	Reconfigurable Computing for Accelerating Protein Folding Simulations.	ARC	2007	DBLP DOI BibTeX RDF
1	Sonia Mota, Eduardo Ros 0001, Javier Díaz 0001, Rafael Rodríguez-Gómez, Richard R. Carrillo	A Space Variant Mapping Architecture for Reliable Car Segmentation.	ARC	2007	DBLP DOI BibTeX RDF
1	Rainer Scholz	Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations.	ARC	2007	DBLP DOI BibTeX RDF
1	Yong Dou, Jinhui Xu 0002, Guiming Wu	The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining.	ARC	2007	DBLP DOI BibTeX RDF
1	Saar Drimer	Authentication of FPGA Bitstreams: Why and How.	ARC	2007	DBLP DOI BibTeX RDF
1	Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena	Switching Activity Models for Power Estimation in FPGA Multipliers.	ARC	2007	DBLP DOI BibTeX RDF
1	Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton	Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval.	ARC	2007	DBLP DOI BibTeX RDF
1	Yazhuo Dong, Yong Dou, Jie Zhou 0007	Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware.	ARC	2007	DBLP DOI BibTeX RDF
1	Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima	A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads.	ARC	2007	DBLP DOI BibTeX RDF
1	Günter Knittel	A Compact Shader for FPGA-Based Volume Rendering Accelerators.	ARC	2007	DBLP DOI BibTeX RDF
1	Jae-Jin Lee, Gi-Yong Song	High-Level Synthesis Using SPARK and Systolic Array.	ARC	2006	DBLP DOI BibTeX RDF
1	Rodrigo Piedade, Leonel Sousa	Configurable Embedded Core for Controlling Electro-Mechanical Systems.	ARC	2006	DBLP DOI BibTeX RDF
1	Jack Whitham, Neil C. Audsley	Integrating Custom Instruction Specifications into C Development Processes.	ARC	2006	DBLP DOI BibTeX RDF
1	Jie Guo 0007, Gleb Belov, Gerhard P. Fettweis	A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware.	ARC	2006	DBLP DOI BibTeX RDF
1	Bjorn De Sutter, Bingfeng Mei, T. Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim, Sukjin Kim	Hardware and a Tool Chain for ADRES.	ARC	2006	DBLP DOI BibTeX RDF
1	Eva M. Ortigosa, Antonio Cañas, Rafael Rodríguez-Gómez, Javier Díaz 0001, Sonia Mota	Towards an Optimal Implementation of MLP in FPGA.	ARC	2006	DBLP DOI BibTeX RDF
1	Rodrigo Agís, Javier Díaz 0001, Eduardo Ros 0001, Richard R. Carrillo, Eva M. Ortigosa	Event-Driven Simulation Engine for Spiking Neural Networks on a Chip.	ARC	2006	DBLP DOI BibTeX RDF
1	Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Koen De Bosschere, Wilfried Philips	Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture.	ARC	2006	DBLP DOI BibTeX RDF
1	Sara Román Navarro, Julio Septién, Hortensia Mecha, Daniel Mozos	Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
1	Kevin Dale, Jeremy W. Sheaffer, Vinu Vijay Kumar, David P. Luebke, Greg Humphreys, Kevin Skadron	Applications of Small-Scale Reconfigurability to Graphics Processors.	ARC	2006	DBLP DOI BibTeX RDF
1	Niklas Lepistö, Benny Thörnberg, Mattias O'Nils	Design Exploration of a Video Pre-processor for an FPGA Based SoC.	ARC	2006	DBLP DOI BibTeX RDF
1	Young-Ho Seo, Dong-Wook Kim	A New VLSI Architecture of Lifting-Based DWT.	ARC	2006	DBLP DOI BibTeX RDF
1	Jens Braunes, Rainer G. Spallek	A Compiler-Oriented Architecture Description for Reconfigurable Systems.	ARC	2006	DBLP DOI BibTeX RDF
1	Sherif Yusuf, Wayne Luk, M. K. N. Szeto, William George Osborne	UNITE: Uniform Hardware-Based Network Intrusion deTection Engine.	ARC	2006	DBLP DOI BibTeX RDF
1	Yeong-Jae Oh, Hanho Lee, Chong Ho Lee	Dynamic Partial Reconfigurable FIR Filter Design.	ARC	2006	DBLP DOI BibTeX RDF
1	Kwangsup So, Jin-Sang Kim, Won-Kyung Cho, Young Soo Kim, Doug Young Suh	Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array.	ARC	2006	DBLP DOI BibTeX RDF
1	Ignacio Bravo Muñoz, Pedro Jiménez, Manuel Mazo 0001, José Luis Lázaro, Ernesto Martín Gorostiza	Architecture Based on FPGA's for Real-Time Image Processing.	ARC	2006	DBLP DOI BibTeX RDF
1	Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano	Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor.	ARC	2006	DBLP DOI BibTeX RDF
1	Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking.	ARC	2006	DBLP DOI BibTeX RDF	exhaustive key search, cryptanalysis, hash-functions, FPGA implementation, time-memory trade-off, rainbow table
1	Rainer Scholz, Klaus Buchenrieder	Self Reconfiguring EPIC Soft Core Processors.	ARC	2006	DBLP DOI BibTeX RDF
1	Nikolay Kavaldjiev, Gerard J. M. Smit, Pascal T. Wolkotte, Pierre G. Jansen	Providing QoS Guarantees in a NoC by Virtual Channel Reservation.	ARC	2006	DBLP DOI BibTeX RDF
1	Guerric Meurice de Dormale, Jean-Jacques Quisquater	Iterative Modular Division over GF(2m): Novel Algorithm and Implementations on FPGA.	ARC	2006	DBLP DOI BibTeX RDF
1	Eduardo Ros Vidal, Javier Díaz 0001, Sonia Mota, F. Vargas-Martín, Maria Dolores Peláez-Coca	Real Time Image Processing on a Portable Aid Device for Low Vision Patients.	ARC	2006	DBLP DOI BibTeX RDF
1	Maurice Keller, Tim Kerins, Francis M. Crowe, William P. Marnane	FPGA Implementation of a GF(2m) Tate Pairing Architecture.	ARC	2006	DBLP DOI BibTeX RDF
1	Joong-ho Park, Bang-Hyun Sung, Seok-Yoon Kim	An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects.	ARC	2006	DBLP DOI BibTeX RDF
1	Sunil Shukla, Neil W. Bergmann, Jürgen Becker 0001	QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection.	ARC	2006	DBLP DOI BibTeX RDF
1	Mário P. Véstias, Horácio C. Neto	Area/Performance Improvement of NoC Architectures.	ARC	2006	DBLP DOI BibTeX RDF
1	Jae-Jin Lee, Gi-Yong Song	Super Semi-systolic Array-Based Application-Specific PLD Architecture.	ARC	2006	DBLP DOI BibTeX RDF
1	Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar	Automatic Compilation Framework for Bloom Filter Based Intrusion Detection.	ARC	2006	DBLP DOI BibTeX RDF
1	J. Gonzalez-Gomez, Iván González, Francisco J. Gomez-Arribas, Eduardo I. Boemo	Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors.	ARC	2006	DBLP DOI BibTeX RDF
1	Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner	Implementation of Realtime and Highspeed Phase Detector on FPGA.	ARC	2006	DBLP DOI BibTeX RDF
1	Betul Buyukkurt, Zhi Guo, Walid A. Najjar	Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
1	Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro	Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility.	ARC	2006	DBLP DOI BibTeX RDF
1	Milan Tichý, Jan Schier, David Gregg	Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA.	ARC	2006	DBLP DOI BibTeX RDF
1	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	A Reconfigurable Data Cache for Adaptive Processors.	ARC	2006	DBLP DOI BibTeX RDF
1	Hiren Joshi, S. S. Verma, G. K. Sharma 0001	Quality Driven Dynamic Low Power Reconfiguration of Handhelds.	ARC	2006	DBLP DOI BibTeX RDF
1	Marcelo Götz, Florian Dittmann 0001	Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server.	ARC	2006	DBLP DOI BibTeX RDF
1	Minoru Watanabe, Fuminori Kobayashi	A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.	ARC	2006	DBLP DOI BibTeX RDF
1	Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz	PISC: Polymorphic Instruction Set Computers.	ARC	2006	DBLP DOI BibTeX RDF
1	David Rodríguez 0001, Juan M. Sánchez, Arturo Duran	Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider.	ARC	2006	DBLP DOI BibTeX RDF
1	Daniel S. Poznanovic	The Emergence of Non-von Neumann Processors.	ARC	2006	DBLP DOI BibTeX RDF
1	Javier Díaz 0001, Eduardo Ros Vidal, Sonia Mota, Rafael Rodríguez-Gómez	Highly Paralellized Architecture for Image Motion Estimation.	ARC	2006	DBLP DOI BibTeX RDF
1	Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk	A Flexible Multi-port Caching Scheme for Reconfigurable Platforms.	ARC	2006	DBLP DOI BibTeX RDF
1	Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara	Generic Network Interfaces for Plug and Play NoC Based Architecture.	ARC	2006	DBLP DOI BibTeX RDF
1	Slawomir Cichon, Marek Gorgon, Miroslaw Pac	Handel-C Design Enhancement for FPGA-Based DV Decoder.	ARC	2006	DBLP DOI BibTeX RDF	video decompression, field programmable gate array, Parallel algorithm, high level languages
1	Gerd Van den Branden, Geert Braeckman, Abdellah Touhafi, Erik F. Dirkx	Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform.	ARC	2006	DBLP DOI BibTeX RDF
1	Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems.	ARC	2006	DBLP DOI BibTeX RDF	RSA, Elliptic Curve Cryptography (ECC), Public-Key Cryptography (PKC), Reconfigurable architecture, FPGA implementation
1	Manuel G. Gericota, Gustavo R. Alves, Luís F. Lemos, José M. Ferreira 0001	A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
1	Hui Qin, Tsutomu Sasao, Jon T. Butler	Implementation of LPM Address Generators on FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
1	Hongzhi Wang 0003, Pierre Leray, Jacques Palicot	A Reconfigurable Architecture for MIMO Square Root Decoder.	ARC	2006	DBLP DOI BibTeX RDF
1	Alex Ngouanga, Gilles Sassatelli, Lionel Torres, Thierry Gil, André Borin Suarez, Altamiro Amadeu Susin	Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform.	ARC	2006	DBLP DOI BibTeX RDF
1	Koen Bertels, João M. P. Cardoso, Stamatis Vassiliadis (eds.)	Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers	ARC	2006	DBLP DOI BibTeX RDF
1	Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis 0001	Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support.	ARC	2006	DBLP DOI BibTeX RDF
1	François-Xavier Standaert, François Macé, Eric Peeters, Jean-Jacques Quisquater	Updates on the Security of FPGAs Against Power Analysis Attacks.	ARC	2006	DBLP DOI BibTeX RDF
1	Francisco Fons, Mariano Fons, Enrique Cantó, Mariano López	Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip.	ARC	2006	DBLP DOI BibTeX RDF
1	Vanderlei Bonato, José A. M. de Holanda, Eduardo Marques	An Embedded Multi-camera System for Simultaneous Localization and Mapping.	ARC	2006	DBLP DOI BibTeX RDF
1	Sonia Mota, Eduardo Ros Vidal, Javier Díaz 0001, Francisco de Toro	General Purpose Real-Time Image Segmentation System.	ARC	2006	DBLP DOI BibTeX RDF

Publications at "ARC"( http://dblp.L3S.de/Venues/ARC )