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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 857 occurrences of 424 keywords
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Results
Found 792 publication records. Showing 792 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
9 | Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk 0001 |
Optimizing shared cache behavior of chip multiprocessors. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser |
Multiple clock and voltage domains for chip multi processors. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
clock domains, voltage domain, power management, DVFS, chip multi processor |
9 | Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt |
Coordinated control of multiple prefetchers in multi-core systems. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
prefetching, multi-core, feedback control, memory systems |
9 | Moinuddin K. Qureshi |
Adaptive Spill-Receive for robust high-performance caching in CMPs. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen 0002, Haihua Shen, Pengyu Wang, Hong Pan |
Fast complete memory consistency verification. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Yi Xu, Yu Du, Bo Zhao 0007, Xiuyi Zhou, Youtao Zhang, Jun Yang 0002 |
A low-radix and low-diameter 3D interconnection network design. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Andrew DeOrio, Ilya Wagner, Valeria Bertacco |
Dacota: Post-silicon validation of the memory subsystem in multi-core designs. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Chris R. Jesshope, Mike Lankamp, Li Zhang 0034 |
Evaluating CMPs and Their Memory Architecture. |
ARCS |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Magnus Jahre, Marius Grannæs, Lasse Natvig |
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures. |
HPCC |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Fabrizio Boldini, Maria Rita Bracchini, Philippos Pouyioutas, Emilios Solomou, Christina Ioannou |
The EUCLIDES Enhancing the Use of Cooperative Learning to Increase DEvelopment of Science Studies Project - An On-Line Learning Portal Utilizing Problem-Based Learning. |
ICWL |
2009 |
DBLP DOI BibTeX RDF |
Web 2.0 tools, Collaborative Learning, Problem-Based Learning |
9 | Liqiang He, Cha Narisu |
A Fast Scheme to Investigate Thermal-Aware Scheduling Policy for Multicore Processors. |
APPT |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Degui Feng, Guanjun Jiang, Tiefei Zhang, Wei Hu 0001, Tianzhou Chen, Mingteng Cao |
SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework. |
APPT |
2009 |
DBLP DOI BibTeX RDF |
synchronization, Chip multiprocessor, transactional memory, scratchpad memory |
9 | Ahmed Abousamra, Rami G. Melhem, Daniel Mossé |
Minimizing expected energy consumption for streaming applications with linear dependencies on chip multiprocessors. |
SIES |
2009 |
DBLP DOI BibTeX RDF |
|
9 | JaeWoong Chung, Woongki Baek, Christos Kozyrakis |
Fast memory snapshot for concurrent programmingwithout synchronization. |
ICS |
2009 |
DBLP DOI BibTeX RDF |
transactional memory, snapshot |
9 | Magnus Jahre, Lasse Natvig |
A light-weight fairness mechanism for chip multiprocessor memory systems. |
Conf. Computing Frontiers |
2009 |
DBLP DOI BibTeX RDF |
dynamic miss handling architecture, miss status holding register, fairness, chip multiprocessor, interference, mechanism |
9 | Zheng Chen, Yin-Liang Zhao, Xiao-Yu Pan, Zhao-Yu Dong, Bing Gao, Zhi-Wen Zhong |
An Overview of Prophet. |
ICA3PP |
2009 |
DBLP DOI BibTeX RDF |
Thread partitioning, Pre-computation slice, Speculative Multithreading Architecture, Thread level parallelism, Speculative multithreading |
9 | Basab Datta, Wayne P. Burleson |
On temperature planarization effect of copper dummy fills in deep nanometer technology. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Lei Shi, Jun Pang 0001, Lei Yang, Tiejun Zhang, Donghui Wang |
Fair-Priority-Expression-Based burst scheduling to enhance performance and fairness of shared dram systems. |
CCECE |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Bernard Courtois, Kholdoun Torki, Sophie Dumont, Sylvaine Eyraud, Jean-François Paillotin, Gregory di Pendina |
Infrastructures for Education, Research and Industry in Microelectronics A Look Worldwide and a Look at India. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi |
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Yang Ding, Mahmut T. Kandemir, Mary Jane Irwin, Padma Raghavan |
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors. |
HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Major Bhadauria, Vincent M. Weaver, Sally A. McKee |
Accomodating Diversity in CMPs with Heterogeneous Frequencies. |
HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Abhishek Bhattacharjee, Margaret Martonosi |
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors. |
ISCA |
2009 |
DBLP DOI BibTeX RDF |
intel tbb, thread criticality prediction, parallel processing, caches, dvfs |
9 | Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph |
Process variation characterization of chip-level multiprocessors. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
software, process variation, characterization |
9 | Simone Campanoni, Giovanni Agosta, Stefano Crespi-Reghizzi |
A parallel dynamic compiler for CIL bytecode. |
ACM SIGPLAN Notices |
2008 |
DBLP DOI BibTeX RDF |
virtual execution system, parallel virtual machine, dynamic compilation |
9 | Milos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero |
Nebelung: Execution Environment for Transactional OpenMP. |
Int. J. Parallel Program. |
2008 |
DBLP DOI BibTeX RDF |
Compiler, OpenMP, Software Transactional Memory, Runtime system |
9 | Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Russ Joseph |
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Engin Ipek, Sally A. McKee, Karan Singh, Rich Caruana, Bronis R. de Supinski, Martin Schulz 0001 |
Efficient architectural design space exploration via predictive modeling. |
ACM Trans. Archit. Code Optim. |
2008 |
DBLP DOI BibTeX RDF |
sensitivity studies, Artificial neural networks, performance prediction, design space exploration |
9 | Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis |
Comparative evaluation of memory models for chip multiprocessors. |
ACM Trans. Archit. Code Optim. |
2008 |
DBLP DOI BibTeX RDF |
streaming memory, parallel programming, Chip multiprocessors, cache coherence, locality optimizations |
9 | Gadi Lifshitz, Ayelet Kroskin, Yael Dubinsky |
The Story of Transition to Agile Software Development. |
XP |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Wei Hu 0001, Tianzhou Chen, Qingsong Shi |
Exploring multicore computing education in China by model curriculum construction. |
Summit on Computing Education in China |
2008 |
DBLP DOI BibTeX RDF |
model curriculum, programming, multicore |
9 | Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti |
Circuit-Switched Coherence. |
NOCS |
2008 |
DBLP DOI BibTeX RDF |
Interconnection network, multiprocessor systems, cache coherence |
9 | Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio |
Reducing the Interconnection Network Cost of Chip Multiprocessors. |
NOCS |
2008 |
DBLP DOI BibTeX RDF |
Chip Multiprocessors, Deadlock, Router Design |
9 | Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger |
Multitasking workload scheduling on flexible-core chip multiprocessors. |
PACT |
2008 |
DBLP DOI BibTeX RDF |
flexible cores, multitask scheduling, multicore architectures |
9 | Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003 |
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. |
PACT |
2008 |
DBLP DOI BibTeX RDF |
ia32, on-chip integration, chip multiprocessor, heterogeneous |
9 | Andrés Ortiz 0001, Julio Ortega Lopera, Antonio F. Díaz, Alberto Prieto |
Comparison of Onloading and Offloading Strategies to Improve Network Interfaces. |
PDP |
2008 |
DBLP DOI BibTeX RDF |
|
9 | José L. Abellán, Juan Fernández 0001, Manuel E. Acacio |
CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE. |
PDP |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Ramazan Bitirgen, Engin Ipek, José F. Martínez |
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Nidhi Aggarwal, James E. Smith 0001, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan |
Implementing high availability memory with a duplication cache. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Yuho Jin, Ki Hwan Yum, Eun Jung Kim 0001 |
Adaptive data compression for high-performance low-power on-chip networks. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Paul Gratz, Boris Grot, Stephen W. Keckler |
Regional congestion awareness for load balance in networks-on-chip. |
HPCA |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Christian Fensch, Marcelo Cintra |
An OS-based alternative to full hardware coherence on tiled CMPs. |
HPCA |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato |
Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs. |
HiPC |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Sridhar Varadan, Janet Meiling Wang, Jiang Hu |
Handling partial correlations in yield prediction. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi |
Shared reconfigurable architectures for CMPS. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Jiaxin Li, Ning Deng 0002, Caixia Liu, Mengxiao Liu, Zuo Wang, Qi Zuo |
FG-NC: A Schedule Algorithm of Designing Concurrent Multi-direction Data Switch Structure. |
ICYCS |
2008 |
DBLP DOI BibTeX RDF |
|
9 | M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman |
RF interconnects for communications on-chip. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
RF-interconnect, network-on-chip, chip multiprocessors |
9 | Andrew B. Kahng |
How to get real mad. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
design-aware manufacturing, integrated circuit physical design, manufacturing-aware design, performance analysis, design for manufacturability |
9 | Qi Zhang, Yurong Chen 0001, Yimin Zhang 0002, Yinlong Xu |
SIFT implementation and optimization for multi-core systems. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Michel Dubois 0001, Hyunyoung Lee |
STAMP: A universal algorithmic model for next-generation multithreaded machines and systems. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Hongbo Zeng, Jun Wang, Ge Zhang 0007, Weiwu Hu |
An interconnect-aware power efficient cache coherence protocol for CMPs. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Farshad Khunjush, Nikitas J. Dimopoulos |
Extended characterization of DMA transfers on the Cell BE processor. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Mustafa Karaköy, Mary Jane Irwin |
Integrated code and data placement in two-dimensional mesh based chip multiprocessors. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala |
Parameterized transient thermal behavioral modeling for chip multiprocessors. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
9 | José L. Abellán, Juan Fernández 0001, Manuel E. Acacio |
Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades. |
ICCS (1) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Marius Grannæs, Magnus Jahre, Lasse Natvig |
Low-cost open-page prefetch scheduling in chip multiprocessors. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Jason Zebchuk, Srihari Makineni, Donald Newell |
Re-examining cache replacement policies. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Michele Petracca, Keren Bergman, Luca P. Carloni |
Photonic networks-on-chip: Opportunities and challenges. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Hao Feng, Eric Q. Li, Yurong Chen 0001, Yimin Zhang 0002 |
Parallelization and characterization of SIFT on multi-core systems. |
IISWC |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Yintian Liu, Yingming Liu, Tao Zeng, Kaikuo Xu, Sunjun Liu |
Sub-frequent Patterns Mining Based on SFP-Tree. |
FSKD (5) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Wangyuan Zhang, Tao Li 0006 |
Managing multi-core soft-error reliability through utility-driven cross domain optimization. |
ASAP |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Like Yan, Qingsong Shi, Tianzhou Chen, Guobing Chen |
An On-chip Communication Mechanism Design in the Embedded Heterogeneous Multi-core Architecture. |
ICNSC |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Yi-Neng Lin, Ying-Dar Lin, Yuan-Cheng Lai |
Thread Allocation in Chip Multiprocessor Based Multithreaded Network Processors. |
AINA |
2008 |
DBLP DOI BibTeX RDF |
thread allocation, simulation, modeling, Petri net, chip multiprocessor |
9 | Zuzana Kukelova, Martin Bujnak, Tomás Pajdla |
Automatic Generator of Minimal Problem Solvers. |
ECCV (3) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Mahmut T. Kandemir, Feihui Li, Mary Jane Irwin, Seung Woo Son 0001 |
A novel migration-based NUCA design for chip multiprocessors. |
SC |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Xiaoye Sherry Li |
Evaluation of Sparse LU Factorization and Triangular Solution on Multicore Platforms. |
VECPAR |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Sean Rul, Hans Vandierendonck, Koen De Bosschere |
Extracting coarse-grain parallelism in general-purpose programs. |
PPoPP |
2008 |
DBLP DOI BibTeX RDF |
do-across, thread-level parallelism, coarse-grain parallelism |
9 | Guilherme Ottoni, David I. August |
Communication optimizations for global multi-threaded instruction scheduling. |
ASPLOS |
2008 |
DBLP DOI BibTeX RDF |
graph min-cut, communication, synchronization, data-flow analysis, multi-threading, instruction scheduling |
9 | Yaron Weinsberg, Danny Dolev, Tal Anker, Muli Ben-Yehuda, Pete Wyckoff |
Tapping into the fountain of CPUs: on operating system support for programmable devices. |
ASPLOS |
2008 |
DBLP DOI BibTeX RDF |
operating systems, programming model, offloading |
9 | Sebastian Herbert, Diana Marculescu |
Characterizing chip-multiprocessor variability-tolerance. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
frequency islands, chip-multiprocessor, process variability |
9 | Yintian Liu, Yingming Liu, Tao Zeng, Kaikuo Xu, Rong Tang |
Mining Supplemental Frequent Patterns. |
ADMA |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Chen-Yong Cher, Michael Gschwind |
Cell GC: using the cell synergistic processor as a garbage collection coprocessor. |
VEE |
2008 |
DBLP DOI BibTeX RDF |
BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep |
9 | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero |
Explaining Dynamic Cache Partitioning Speed Ups. |
IEEE Comput. Archit. Lett. |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser |
Nahalal: Cache Organization for Chip Multiprocessors. |
IEEE Comput. Archit. Lett. |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Pat Conway, Bill Hughes |
The AMD Opteron Northbridge Architecture. |
IEEE Micro |
2007 |
DBLP DOI BibTeX RDF |
system topology, northbridge, scalability, microarchitecture, point-to-point networking |
9 | Mainak Chaudhuri, Mark A. Heinrich |
Integrated Memory Controllers with Parallel Coherence Streams. |
IEEE Trans. Parallel Distributed Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Ruchira Sasanka, Man-Lap Li, Sarita V. Adve, Yen-Kuang Chen, Eric Debes |
ALP: Efficient support for all levels of parallelism for complex media applications. |
ACM Trans. Archit. Code Optim. |
2007 |
DBLP DOI BibTeX RDF |
media applications, multimedia, Parallelism, SIMD, vector, TLP, DLP, data-level parallelism |
9 | Kyueun Yi, Jean-Luc Gaudiot |
Architectural Implications of Cache Coherence Protocols with Network Applications on Chip MultiProcessors. |
NPC |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero |
MLP-Aware Dynamic Cache Partitioning. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Alexandra Fedorova, Margo I. Seltzer, Michael D. Smith 0001 |
Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Kostas Papadopoulos, Kyriakos Stavrou, Pedro Trancoso |
HelperCore_DB: Exploiting Multicore Technology for Databases. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Milos Milovanovic, Roger Ferrer, Osman S. Unsal, Adrián Cristal, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero |
Transactional Memory and OpenMP. |
IWOMP |
2007 |
DBLP DOI BibTeX RDF |
STM Library, Compiler, OpenMP, Software Transaction Memory |
9 | Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun |
ATLAS: a chip-multiprocessor with transactional memory support. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Karin Strauss, Xiaowei Shen, Josep Torrellas |
Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler |
Composable Lightweight Processors. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Cheng Wang 0013, Ho-Seop Kim, Youfeng Wu, Victor Ying |
Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection. |
CGO |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Alaa R. Alameldeen, David A. Wood 0001 |
Interactions Between Compression and Prefetching in Chip Multiprocessors. |
HPCA |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Jörg-Christian Niemann, Christian Liß, Mario Porrmann, Ulrich Rückert 0001 |
A Multiprocessor Cache for Massively Parallel SoC Architectures. |
ARCS |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Vineet Agarwal, Jin Sun 0006, Alexander V. Mitev, Janet Meiling Wang |
Delay Uncertainty Reduction by Interconnect and Gate Splitting. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang 0001 |
Coupling-aware Dummy Metal Insertion for Lithography. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
coupling-aware dummy metal insertion, integrated circuits manufacturing technology, resolution enhancement techniques, off-axis illumination, forbidden pitches, printability improvement, invisible dummy metal segments, lithography cost minimization, optimal algorithm, chemical mechanical polish |
9 | Shuming Chen, Pengyong Ma |
FROCM: A Fair and Low-Overhead Method in SMT Processor. |
HPCC |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Lu Peng 0001, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-Kuang Chen, David M. Koppelman |
Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study. |
IPCCC |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark A. Heinrich |
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
active memory cluster, directory protocol thread, active memory address remapping, parallel reduction, coherence protocol extension, software protocol, multi-threaded node, dual-core node, active memory architecture, distributed shared memory, multiprocessor architecture, memory controller, matrix transpose |
9 | Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque |
Adaptive L2 Cache for Chip Multiprocessors. |
Euro-Par Workshops |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Li Zhang 0034, Chris R. Jesshope |
On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores. |
Euro-Par Workshops |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Michel Dubois 0001, Hyunyoung Lee, Lan Lin |
STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Srinivas Vadlamani, Stephen F. Jenks |
Architectural Considerations for Efficient Software Execution on Parallel Microprocessors. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Suresh Jagannathan |
Weaving Atomicity Through Dynamic Dependence Tracking. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Yan Solihin, Fei Guo, Seongbeom Kim, Fang Liu |
Supporting Quality of Service in High-Performance Servers. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez |
A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
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