Search results for "DFT"

Hits ?▲	Authors	Title	Venue	Year	Link
27	Jorge Luis Lagos-Benites, Michelangelo Grosso, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini, V. A. Avantaggiati	An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems.	DFT	2011	DBLP DOI BibTeX RDF
27	Erik MacLean, Vijay K. Jain	A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect Tolerance.	DFT	2011	DBLP DOI BibTeX RDF
27	Chandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis	A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate.	DFT	2011	DBLP DOI BibTeX RDF
27	Mehran Mozaffari Kermani, Arash Reyhani-Masoleh	Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform.	DFT	2011	DBLP DOI BibTeX RDF
27	Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch	On the Modeling of Gate Delay Faults by Means of Transition Delay Faults.	DFT	2011	DBLP DOI BibTeX RDF
27	Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Alireza Nojeh	A Unified Error Control Coding Scheme to Enhance the Reliability of a Hybrid Wireless Network-on-Chip.	DFT	2011	DBLP DOI BibTeX RDF
27	Rudrajit Datta, Nur A. Touba	X-Stacking - A Method for Reducing Control Data for Output Compaction.	DFT	2011	DBLP DOI BibTeX RDF
27	Hiroshi Kutami, Yusuke Fukushima, Masaru Fukushi, Ikuko Eguchi Yairi, Takeshi Hattori	Route-Aware Task Mapping Method for Fault-Tolerant 2D-Mesh Network-on-Chips.	DFT	2011	DBLP DOI BibTeX RDF
27	Masato Inoue, Haruhiko Kaneko	Deletion/Insertion/Reversal Error Correcting Codes for Bit-Patterned Media Recording.	DFT	2011	DBLP DOI BibTeX RDF
27	Masoud Zamani, Hossein Pedram, Fabrizio Lombardi	Templated-Based Asynchronous Design for Testable and Fail-Safe Operation.	DFT	2011	DBLP DOI BibTeX RDF
27	Shuai Wang	Characterizing System-Level Vulnerability for Instruction Caches against Soft Errors.	DFT	2011	DBLP DOI BibTeX RDF
27	Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga	A Soft Error Tolerance Estimation Method for Sequential Circuits.	DFT	2011	DBLP DOI BibTeX RDF
27	Ahmed Awad, Abdallatif S. Abu-Issa, Said Hamdioui	Reducing Test Power for Embedded Memories.	DFT	2011	DBLP DOI BibTeX RDF
27	Vijay K. Jain, Glenn H. Chapman	Enhanced Defect Tolerance through Matrixed Deployment of Intelligent Sensors for the Smart Power Grid.	DFT	2011	DBLP DOI BibTeX RDF
27	Dan Alexandrescu, Enrico Costenaro, Michael Nicolaidis	A Practical Approach to Single Event Transients Analysis for Highly Complex Designs.	DFT	2011	DBLP DOI BibTeX RDF
27	Daniele Giaffreda, Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition.	DFT	2011	DBLP DOI BibTeX RDF
27	Daniel B. Limbrick, Suge Yue, William H. Robinson, Bharat L. Bhuva	Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits.	DFT	2011	DBLP DOI BibTeX RDF
27	Geunho Cho, Fabrizio Lombardi	On the Delay Analysis of Defective CNTFETs with Undeposited CNTs.	DFT	2011	DBLP DOI BibTeX RDF
27	Sreenivas Gangadhar, Spyros Tragoudas	A Probabilistic Approach to Diagnose SETs.	DFT	2011	DBLP DOI BibTeX RDF
27	Glenn H. Chapman, Jenny Leung, Ana I. L. Namburete, Israel Koren, Zahava Koren	Predicting Pixel Defect Rates Based on Image Sensor Parameters.	DFT	2011	DBLP DOI BibTeX RDF
27		25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010	DFT	2010	DBLP BibTeX RDF
27	Irith Pomeranz, Sudhakar M. Reddy	Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs.	DFT	2010	DBLP DOI BibTeX RDF
27	Kazuteru Namba, Hideo Ito	Soft Error Tolerant BILBO FF.	DFT	2010	DBLP DOI BibTeX RDF
27	Marc Hunger, Sybille Hellebrand	The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.	DFT	2010	DBLP DOI BibTeX RDF
27	Salvatore Campagna, Moazzam Hussain, Massimo Violante	Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space Applications.	DFT	2010	DBLP DOI BibTeX RDF
27	Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz	Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration.	DFT	2010	DBLP DOI BibTeX RDF
27	Cristiana Bolchini, Antonio Miele	Reliability-Driven System-Level Synthesis of Embedded Systems.	DFT	2010	DBLP DOI BibTeX RDF
27	Bishnu Prasad Das, Hidetoshi Onodera	Warning Prediction Sequential for Transient Error Prevention.	DFT	2010	DBLP DOI BibTeX RDF
27	Daniele Rossi 0001, Martin Omaña 0001, Cecilia Metra	Transient Fault and Soft Error On-die Monitoring Scheme.	DFT	2010	DBLP DOI BibTeX RDF
27	Cristiana Bolchini, Luca Fossati, David Merodio Codinachs, Antonio Miele, Chiara Sandionigi	A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms.	DFT	2010	DBLP DOI BibTeX RDF
27	Yoshiyuki Nakamura, Masashi Tanaka	A Multi-dimensional Iddq Testing Method Using Mahalanobis Distance.	DFT	2010	DBLP DOI BibTeX RDF
27	Vijay K. Jain, Glenn H. Chapman	Massively Deployable Intelligent Sensors for the Smart Power Grid.	DFT	2010	DBLP DOI BibTeX RDF
27	Yusuke Fukushima, Masaru Fukushi, Ikuko Eguchi Yairi, Takeshi Hattori	A Hardware-Oriented Fault-Tolerant Routing Algorithm for Irregular 2D-Mesh Network-on-Chip without Virtual Channels.	DFT	2010	DBLP DOI BibTeX RDF
27	Nor Zaidi Haron, Said Hamdioui	High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories.	DFT	2010	DBLP DOI BibTeX RDF
27	Nor Azura Zakaria, Edward V. Bautista Jr., Suhaimi Bahisham Jusoh, Weng Fook Lee, Xiaoqing Wen	Case Studies on Transition Fault Test Generation for At-speed Scan Testing.	DFT	2010	DBLP DOI BibTeX RDF
27	Hassan Ebrahimi, Morteza Saheb Zamani, Seyyed Ahmad Razavi	A Switch Box Architecture to Mitigate Bridging and Short Faults in SRAM-Based FPGAs.	DFT	2010	DBLP DOI BibTeX RDF
27	Bijan Ansari, Ingrid Verbauwhede	A Hybrid Scheme for Concurrent Error Detection of Multiplication over Finite Fields.	DFT	2010	DBLP DOI BibTeX RDF
27	Lizhen Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang, Xiaoqing Wen	Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs.	DFT	2010	DBLP DOI BibTeX RDF
27	Kunihiro Asada, Makoto Ikeda, Benjamin Stefan Devlin, Taku Sogabe	Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging.	DFT	2010	DBLP DOI BibTeX RDF
27	Ming Zhu, Liyi Xiao, Shuhao Li, Yanjing Zhang	Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in Memory.	DFT	2010	DBLP DOI BibTeX RDF
27	Zahra Mashreghian Arani, Masoud Hashempour, Fabrizio Lombardi	An Analytical Error Model for Pattern Clipping in DNA Self-Assembly.	DFT	2010	DBLP DOI BibTeX RDF
27	Kensuke Tai, Masato Kitakami	Prolongation of Lifetime and the Evaluation Method of Dependable SSD.	DFT	2010	DBLP DOI BibTeX RDF
27	Luca Amati, Cristiana Bolchini, Fabio Salice	Test Selection Policies for Faster Incremental Fault Detection.	DFT	2010	DBLP DOI BibTeX RDF
27	Navaneeth Rameshan, Vijay Laxmi, Manoj Singh Gaur, Mushtaq Ahmed, Krishan Kumar Paliwal	Minimal Path, Fault Tolerant, QoS Aware Routing with Node and Link Failure in 2-D Mesh NoC.	DFT	2010	DBLP DOI BibTeX RDF
27	Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang	Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.	DFT	2010	DBLP DOI BibTeX RDF
27	Daisaku Seto, Minoru Watanabe	Recovery Method for a Laser Array Failure on Dynamic Optically Reconfigurable Gate Arrays.	DFT	2010	DBLP DOI BibTeX RDF
27	Geunho Cho, Fabrizio Lombardi, Yong-Bin Kim	Modelling a CNTFET with Undeposited CNT Defects.	DFT	2010	DBLP DOI BibTeX RDF
27	Tatsuya Suto, Kenji Ichijo, Yoshio Yoshioka	Design and Evaluation of Burst-Mode Asynchronous 8-Bit Microprocessor Using Standard FPGA Development System.	DFT	2010	DBLP DOI BibTeX RDF
27	Nobuyasu Kanekawa	Industrial Approach for Dependability.	DFT	2010	DBLP DOI BibTeX RDF
27	Yasuo Sato	Circuit Failure Prediction by Field Test - A New Task of Testing.	DFT	2010	DBLP DOI BibTeX RDF
27	Pilin Junsangsri, Fabrizio Lombardi	Time/Temperature Degradation of Solar Cells under the Single Diode Model.	DFT	2010	DBLP DOI BibTeX RDF
27	Takashi Aikyo	Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-Clouseau.	DFT	2010	DBLP DOI BibTeX RDF
27	Tomoyuki Nagase, Kenji Ichijo, Akiko Narita, Yoshio Yoshioka	CFBLT: A Closed Feed Back Loop Type Queuing System; Modeling and Analysis.	DFT	2010	DBLP DOI BibTeX RDF
27	NurQamarina MohdNoor, Azilah Saparon, Yusrina Yusof	Programmable MBIST Merging FSM and Microcode Techniques Using Macro Commands.	DFT	2010	DBLP DOI BibTeX RDF
27	Eduardo Luis Rhod, Luca Sterpone, Luigi Carro	A New Soft-Error Resilient Voltage-Mode Quaternary Latch.	DFT	2010	DBLP DOI BibTeX RDF
27	Kunihito Yamamori, Keisuke Tashiro, Masamichi Kusano, Ikuo Yoshihara	A Design of Self-Defect-Compensatable Hardware Neuron for Multi-layer Neural Networks.	DFT	2010	DBLP DOI BibTeX RDF
27	Payman Zarkesh-Ha, Ali Arabi M. Shahi	Logic Gate Failure Characterization for Nanoelectronic EDA Tools.	DFT	2010	DBLP DOI BibTeX RDF
27	Anant Narayan Hariharan, Salvatore Pontarelli, Marco Ottavi, Fabrizio Lombardi	Modeling Open Defects in Nanometric Scale CMOS.	DFT	2010	DBLP DOI BibTeX RDF
27	Mario Schölzel, Sebastian Müller 0005	Combining Hardware- and Software-Based Self-Repair Methods for Statically Scheduled Data Paths.	DFT	2010	DBLP DOI BibTeX RDF
27	Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang	AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.	DFT	2010	DBLP DOI BibTeX RDF
27	Chun-Lung Hsu, Chen-Wei Lan, Yu-Chih Lo, Yu-Sheng Huang	Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications.	DFT	2010	DBLP DOI BibTeX RDF
27	Dan Zhu, Tun Li, Sikun Li	An Approximate Soft Error Reliability Sorting Approach Based on State Analysis of Sequential Circuits.	DFT	2010	DBLP DOI BibTeX RDF
27	Martin Omaña 0001, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam 0001, Asifur Rahman	On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter.	DFT	2010	DBLP DOI BibTeX RDF
27	Kazuteru Namba, Masatoshi Sakata, Hideo Ito	Single Event Induced Double Node Upset Tolerant Latch.	DFT	2010	DBLP DOI BibTeX RDF
27	Noriaki Takagi	A Study of eSRAM Testability.	DFT	2010	DBLP DOI BibTeX RDF
27	Xiaoqing Wen	Low-Power Testing for Low-Power Devices.	DFT	2010	DBLP DOI BibTeX RDF
27	Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz	Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance.	DFT	2010	DBLP DOI BibTeX RDF
27	Mahroo Zandrahimi, Alireza Zarei, Hamid R. Zarandi	A Probabilistic Method to Detect Anomalies in Embedded Systems.	DFT	2010	DBLP DOI BibTeX RDF
27	Min-Ju Chan, Chun-Lung Hsu	A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip.	DFT	2010	DBLP DOI BibTeX RDF
27	Salvatore Pontarelli, Marco Ottavi, Adelio Salsano	Error Detection and Correction in Content Addressable Memories.	DFT	2010	DBLP DOI BibTeX RDF
27	Srikanth V. Devarapalli, Payman Zarkesh-Ha, Steven C. Suddarth	SEU-Hardened Dual Data Rate Flip-Flop Using C-Elements.	DFT	2010	DBLP DOI BibTeX RDF
27	Erik MacLean, Vijay K. Jain	Analog Design for a Power Transmission Line Sensing and Analysis VLSI Chip.	DFT	2010	DBLP DOI BibTeX RDF
27	Glenn H. Chapman, Jenny Leung, Israel Koren, Zahava Koren	Tradeoffs in Imager Design with Respect to Pixel Defect Rates.	DFT	2010	DBLP DOI BibTeX RDF
27	Navid Farazmand, Masoud Zamani, Mehdi Baradaran Tahoori	Online Multiple Fault Detection in Reversible Circuits.	DFT	2010	DBLP DOI BibTeX RDF
27	Osnat Keren, Ilya Levin, Mark G. Karpovsky	Duplication Based One-to-Many Coding for Trojan HW Detection.	DFT	2010	DBLP DOI BibTeX RDF
27	Dimitris Gizopoulos, Susumu Horiguchi, Spyros Tragoudas, Mohammad Tehranipoor (eds.)	24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009	DFT	2009	DBLP BibTeX RDF
27	Naveed A. Sherwani	Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs.	DFT	2009	DBLP DOI BibTeX RDF
27	Sybille Hellebrand, Marc Hunger	Are Robust Circuits Really Robust?	DFT	2009	DBLP DOI BibTeX RDF
27	Li-C. Wang	Data Learning Techniques for Functional/System Fmax Prediction.	DFT	2009	DBLP DOI BibTeX RDF
27	Marcelo Lubaszewski	Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?	DFT	2009	DBLP DOI BibTeX RDF
27	Irith Pomeranz, Sudhakar M. Reddy	On-chip Generation of the Second Primary Input Vectors of Broadside Tests.	DFT	2009	DBLP DOI BibTeX RDF
27	Norman P. Jouppi	Resilience Challenges for Exascale Systems.	DFT	2009	DBLP DOI BibTeX RDF
27	Snehal Udar, Dimitri Kagaris	Minimizing Observation Points for Fault Location.	DFT	2009	DBLP DOI BibTeX RDF
27	Shih-Hsin Hu, Tung-Yeh Wu, Jacob A. Abraham	SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000.	DFT	2009	DBLP DOI BibTeX RDF
27	Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabrizio Lombardi	Errors in DNA Self-Assembly by Synthesized Tile Sets.	DFT	2009	DBLP DOI BibTeX RDF
27	D. M. H. Walker	Challenges in Delay Testing of Integrated Circuits.	DFT	2009	DBLP DOI BibTeX RDF
27	Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin	Reduced Precision Checking for a Floating Point Adder.	DFT	2009	DBLP DOI BibTeX RDF
27	Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis 0001	An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs.	DFT	2009	DBLP DOI BibTeX RDF
27	Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi	Optimizing Parametric BIST Using Bio-inspired Computing Algorithms.	DFT	2009	DBLP DOI BibTeX RDF
27	Sheng Lin 0006, Yong-Bin Kim, Fabrizio Lombardi	A Novel Hardened Design of a CMOS Memory Cell at 32nm.	DFT	2009	DBLP DOI BibTeX RDF
27	Luca Amati, Cristiana Bolchini, Laura Frigerio, Fabio Salice, William Eklow, Arnold Suvatne, Eugenio Brambilla, Federico Franzoso, Michele Martin	An Incremental Approach to Functional Diagnosis.	DFT	2009	DBLP DOI BibTeX RDF
27	Irith Pomeranz, Sudhakar M. Reddy	Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences.	DFT	2009	DBLP DOI BibTeX RDF
27	David Wolpert 0001, Paul Ampadu	A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits.	DFT	2009	DBLP DOI BibTeX RDF
27	Yueran Gao, Haibo Wang 0005	A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault Tolerance.	DFT	2009	DBLP DOI BibTeX RDF
27	Yehua Su, Wenjing Rao	Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis.	DFT	2009	DBLP DOI BibTeX RDF
27	Qiaoyan Yu, Paul Ampadu	Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip.	DFT	2009	DBLP DOI BibTeX RDF
27	Jianwei Dai, Lei Wang 0003	A Study of Side-Channel Effects in Reliability-Enhancing Techniques.	DFT	2009	DBLP DOI BibTeX RDF
27	Takumi Hoshi, Kazuteru Namba, Hideo Ito	Testing of Switch Blocks in Three-Dimensional FPGA.	DFT	2009	DBLP DOI BibTeX RDF
27	Stelios Neophytou, Maria K. Michael, Kyriakos Christou	Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning.	DFT	2009	DBLP DOI BibTeX RDF
27	Aaron Dingler, M. Jafar Siddiq, Michael T. Niemier, Xiaobo Sharon Hu, M. Tanvir Alam, Gary H. Bernstein, Wolfgang Porod	Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power.	DFT	2009	DBLP DOI BibTeX RDF