Search results for "DFT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Yoonjae Huh, Yoon-Hwa Choi	Module Grouping for Defect Tolerance in Nanoscale Memory.	DFT	2008	DBLP DOI BibTeX RDF
1	Andrey V. Zykov, Gustavo de Veciana	Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?.	DFT	2008	DBLP DOI BibTeX RDF
1	Oscar Kuiken, Xiao Zhang 0002, Hans G. Kerkhoff	Built-in-Self-Diagnostics for a NoC-Based Reconfigurable IC for Dependable Beamforming Applications.	DFT	2008	DBLP DOI BibTeX RDF
1	Kartik Mohanram	Error Detection and Tolerance for Scaled Electronic Technologies.	DFT	2008	DBLP DOI BibTeX RDF
1	Glenn H. Chapman, Vijay K. Jain	Defect Tolerance for a Capacitance Based Nanoscale Biosensor.	DFT	2008	DBLP DOI BibTeX RDF
1	Syed Zafar Shazli, Mehdi Baradaran Tahoori	Obtaining Microprocessor Vulnerability Factor Using Formal Methods.	DFT	2008	DBLP DOI BibTeX RDF
1	Phil Nigh	The Evolving Role of Test ... it is now a "Value Add" Operation.	DFT	2008	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	A-Diagnosis: A Complement to Z-Diagnosis.	DFT	2007	DBLP DOI BibTeX RDF
1	Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas 0001, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations.	DFT	2007	DBLP DOI BibTeX RDF
1	Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, Sandro Pastore, Giacomo R. Sechi, Roland Weigand	Evaluation of Single Event Upset Mitigation Schemes for SRAM Based FPGAs Using the FLIPPER Fault Injection Platform.	DFT	2007	DBLP DOI BibTeX RDF
1	Haruhiko Kaneko, Eiji Fujiwara	Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks.	DFT	2007	DBLP DOI BibTeX RDF
1	Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube	A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.	DFT	2007	DBLP DOI BibTeX RDF
1	Young Bok Kim, Yong-Bin Kim	Fault Tolerant Source Routing for Network-on-Chip.	DFT	2007	DBLP DOI BibTeX RDF
1	Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Riccardo Mariani	A Functional Verification Based Fault Injection Environment.	DFT	2007	DBLP DOI BibTeX RDF
1	Michele Favalli, Marcello Dalpasso	High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations.	DFT	2007	DBLP DOI BibTeX RDF
1	Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi	Error Tolerance of DNA Self-Healing Assemblies by Puncturing.	DFT	2007	DBLP DOI BibTeX RDF
1	Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume	Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.	DFT	2007	DBLP DOI BibTeX RDF
1	Mehdi Kamal, Somayyeh Koohi, Shaahin Hessabi	Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs.	DFT	2007	DBLP DOI BibTeX RDF
1	Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky	Reduction of Fault Latency in Sequential Circuits by using Decomposition.	DFT	2007	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio	TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs.	DFT	2007	DBLP DOI BibTeX RDF
1	Michele Favalli	Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth.	DFT	2007	DBLP DOI BibTeX RDF
1	Swapnil Bahl	A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema.	DFT	2007	DBLP DOI BibTeX RDF
1	Laura Frigerio, Fabio Salice	RAM-Based Fault Tolerant State Machines for FPGAs.	DFT	2007	DBLP DOI BibTeX RDF
1	Jing Huang 0001, Xiaojun Ma, Cecilia Metra, Fabrizio Lombardi	Testing Reversible One-Dimensional QCA Arrays for Multiple Faults.	DFT	2007	DBLP DOI BibTeX RDF
1	Erik Schüler, Adão Antônio de Souza Jr., Luigi Carro	Spare Parts in Analog Circuits: A Filter Example.	DFT	2007	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba (eds.)	22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy.	DFT	2007	DBLP BibTeX RDF
1	Helia Naeimi, André DeHon	Fault Secure Encoder and Decoder for Memory Applications.	DFT	2007	DBLP DOI BibTeX RDF
1	Stelios Neophytou, Maria K. Michael	Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits.	DFT	2007	DBLP DOI BibTeX RDF
1	Marco Ottavi, Hamidreza Hashempour, Vamsi Vankamamidi, Faizal Karim, Konrad Walus, André Ivanov	On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.	DFT	2007	DBLP DOI BibTeX RDF
1	Mojtaba Valinataj, Saeed Safari	Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction.	DFT	2007	DBLP DOI BibTeX RDF
1	Weidong Kuang, Casto Manuel Ibarra, Peiyi Zhao	Soft Error Hardening for Asynchronous Circuits.	DFT	2007	DBLP DOI BibTeX RDF
1	Abhijit Jas, Srinivas Patil	Analysis of Specified Bit Handling Capability of Combinational Expander Networks.	DFT	2007	DBLP DOI BibTeX RDF
1	Andrea Manuzzato, Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Luca Sterpone, Massimo Violante	Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs.	DFT	2007	DBLP DOI BibTeX RDF
1	Jozsef Dudas, Michelle L. La Haye, Jenny Leung, Glenn H. Chapman	A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot Pixel Defects.	DFT	2007	DBLP DOI BibTeX RDF
1	Ravi Bonam, Yong-Bin Kim, Minsu Choi	Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture.	DFT	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits.	DFT	2007	DBLP DOI BibTeX RDF
1	Avijit Dutta, Nur A. Touba	Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code.	DFT	2007	DBLP DOI BibTeX RDF
1	Michele Portolan, Régis Leveugle	Effective Checkpoint and Rollback Using Hardware/OS Collaboration.	DFT	2007	DBLP DOI BibTeX RDF
1	Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante	Optimization of Self Checking FIR filters by means of Fault Injection Analysis.	DFT	2007	DBLP DOI BibTeX RDF
1	Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren	Quantitative Analysis of In-Field Defects in Image Sensor Arrays.	DFT	2007	DBLP DOI BibTeX RDF
1	Martin Straka, Jiri Tobola, Zdenek Kotásek	Checker Design for On-line Testing of Xilinx FPGA Communication Protocols.	DFT	2007	DBLP DOI BibTeX RDF
1	Jorge Luis Lagos-Benites, Davide Appello, Paolo Bernardi, Michelangelo Grosso, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda	An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains.	DFT	2007	DBLP DOI BibTeX RDF
1	Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu	Timing-Aware Diagnosis for Small Delay Defects.	DFT	2007	DBLP DOI BibTeX RDF
1	Rani S. Ghaida, Payman Zarkesh-Ha	Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model.	DFT	2007	DBLP DOI BibTeX RDF
1	Piotr Zajac, Jacques Henri Collet	Production Yield and Self-Configuration in the Future Massively Defective Nanochips.	DFT	2007	DBLP DOI BibTeX RDF
1	Anjela Yu. Matrosova, Ekaterina Loukovnikova, Sergei Ostanin, Alexandra Zinchuk, Ekaterina Nikolaeva	Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs.	DFT	2007	DBLP DOI BibTeX RDF
1	Yoon-Hwa Choi, Myeong-Hyeon Lee	A Defect-Tolerant Molecular-Based Memory Architecture.	DFT	2007	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Kentaroh Katoh, Hideo Ito	Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability.	DFT	2007	DBLP DOI BibTeX RDF
1	Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle	Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections.	DFT	2007	DBLP DOI BibTeX RDF
1	Giovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele, Donatella Sciuto	A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip.	DFT	2007	DBLP DOI BibTeX RDF
1	Francesco Regazzoni 0001, Thomas Eisenbarth 0001, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar	Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits.	DFT	2007	DBLP DOI BibTeX RDF
1	Timothy J. Dysart, Peter M. Kogge	Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder.	DFT	2007	DBLP DOI BibTeX RDF
1	Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena	SET Emulation Under a Quantized Delay Model.	DFT	2007	DBLP DOI BibTeX RDF
1	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors.	DFT	2007	DBLP DOI BibTeX RDF
1	Waleed K. Al-Assadi, Sindhu Kakarla	Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Design.	DFT	2007	DBLP DOI BibTeX RDF
1	Takashi Ikeda, Kazuteru Namba, Hideo Ito	Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing.	DFT	2007	DBLP DOI BibTeX RDF
1	Masaru Fukushi, Susumu Horiguchi, Luke Demoracski, Fabrizio Lombardi	A Scalable Framework for Defect Isolation of DNA Self-assemlbled Networks.	DFT	2007	DBLP DOI BibTeX RDF
1	Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan	Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories.	DFT	2007	DBLP DOI BibTeX RDF
1	Hossein Asadi 0001, Mehdi Baradaran Tahoori, Chandra Tirumurti	Estimating Error Propagation Probabilities with Bounded Variances.	DFT	2007	DBLP DOI BibTeX RDF
1	Riccardo Mariani, Peter Fuhrmann	Comparing fail-safe microcontroller architectures in light of IEC 61508.	DFT	2007	DBLP DOI BibTeX RDF
1	Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin	Lazy Error Detection for Microprocessor Functional Units.	DFT	2007	DBLP DOI BibTeX RDF
1	Mandar V. Joshi, Waleed Al-Assadi	Nanofabric PLA architecture with Redundancy Enhancement.	DFT	2007	DBLP DOI BibTeX RDF
1	Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Safety Evaluation of NanoFabrics.	DFT	2007	DBLP DOI BibTeX RDF
1	Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi	Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode.	DFT	2007	DBLP DOI BibTeX RDF
1	Valeriu Beiu, Walid Ibrahim, Y. A. Alkhawwar, Mawahib H. Sulieman	Gate Failures Effectively Shape Multiplexing.	DFT	2006	DBLP DOI BibTeX RDF
1	Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský	Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead.	DFT	2006	DBLP DOI BibTeX RDF
1	Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li 0001	A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy.	DFT	2006	DBLP DOI BibTeX RDF
1	Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto	Combined software and hardware techniques for the design of reliable IP processors.	DFT	2006	DBLP DOI BibTeX RDF
1	Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz	Selecting High-Quality Delay Tests for Manufacturing Test and Debug.	DFT	2006	DBLP DOI BibTeX RDF
1	Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty	An Approach to Minimizing Functional Constraints.	DFT	2006	DBLP DOI BibTeX RDF
1	Tian Xia, Stephen Wyatt, Rupert Ho	Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration.	DFT	2006	DBLP DOI BibTeX RDF
1	Avijit Dutta, Nur A. Touba	Synthesis of Efficient Linear Test Pattern Generators.	DFT	2006	DBLP DOI BibTeX RDF
1	André V. Fidalgo, Gustavo R. Alves, José M. Ferreira 0001	Real Time Fault Injection Using Enhanced OCD -- A Performance Analysis.	DFT	2006	DBLP DOI BibTeX RDF
1	Ilia Polian, Bernd Becker 0001, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara	Low-Cost Hardening of Image Processing Applications Against Soft Errors.	DFT	2006	DBLP DOI BibTeX RDF
1	Di Mu, Tian Xia, Hao Zheng 0001	Data Dependent Jitter Characterization Based on Fourier Analysis.	DFT	2006	DBLP DOI BibTeX RDF
1	Akhil Garg 0001, Prashant Dubey	Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost.	DFT	2006	DBLP DOI BibTeX RDF	Compression and Yield, Memory, Repair, Fuse
1	Partha Pratim Pande, Amlan Ganguly, Brett Feero, Benjamin Belzer, Cristian Grecu	Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding.	DFT	2006	DBLP DOI BibTeX RDF
1	Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpill Park	Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design.	DFT	2006	DBLP DOI BibTeX RDF
1	Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato	Effective Post-BIST Fault Diagnosis for Multiple Faults.	DFT	2006	DBLP DOI BibTeX RDF
1	Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, Fabrizio Lombardi	Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations.	DFT	2006	DBLP DOI BibTeX RDF
1	Krishnendu Chakrabarty	Reconfiguration-Based Defect Tolerance for Microfluidic Biochips.	DFT	2006	DBLP BibTeX RDF
1	Hiroyuki Ohde, Haruhiko Kaneko, Eiji Fujiwara	Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems.	DFT	2006	DBLP DOI BibTeX RDF
1	Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka	Adaptive Design for Performance-Optimized Robustness.	DFT	2006	DBLP DOI BibTeX RDF
1	Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi	Error Tolerance of DNA Self-Assembly by Monomer Concentration Control.	DFT	2006	DBLP DOI BibTeX RDF
1	Jozsef Dudas, Cory Jung, Linda Wu, Glenn H. Chapman, Israel Koren, Zahava Koren	On-Line Mapping of In-Field Defects in Image Sensor Arrays.	DFT	2006	DBLP DOI BibTeX RDF
1	Hamidreza Hashempour, Fabrizio Lombardi	A Novel Methodology for Functional Test Data Compression.	DFT	2006	DBLP DOI BibTeX RDF
1	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor.	DFT	2006	DBLP DOI BibTeX RDF
1	Xiaojun Ma, Jing Huang 0001, Cecilia Metra, Fabrizio Lombardi	Testing Reversible 1D Arrays for Molecular QCA.	DFT	2006	DBLP DOI BibTeX RDF	emerging technologies, Reversible computing, QCA
1	Sanghoan Chang, Gwan Choi	Timing Failure Analysis of Commercial CPUs Under Operating Stress.	DFT	2006	DBLP DOI BibTeX RDF
1	Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas	A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates.	DFT	2006	DBLP DOI BibTeX RDF
1	Chuen-Song Chen, Jien-Chung Lo, Tian Xia	Equivalent IDDQ Tests for Systems with Regulated Power Supply.	DFT	2006	DBLP DOI BibTeX RDF
1	Markus Ferringer, Gottfried Fuchs, Andreas Steininger, Gerald Kempf	VLSI Implementation of a Fault-Tolerant Distributed Clock Generation.	DFT	2006	DBLP DOI BibTeX RDF
1	Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante	Online hardening of programs against SEUs and SETs.	DFT	2006	DBLP DOI BibTeX RDF
1	Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz	Test Generation for Open Defects in CMOS Circuits.	DFT	2006	DBLP DOI BibTeX RDF
1	Zhiyuan He 0002, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi	Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.	DFT	2006	DBLP DOI BibTeX RDF
1	Mehran Mozaffari Kermani, Arash Reyhani-Masoleh	Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard.	DFT	2006	DBLP DOI BibTeX RDF
1	Kristian Granhaug, Snorre Aunet	Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates.	DFT	2006	DBLP DOI BibTeX RDF
1	Vijay K. Jain, Glenn H. Chapman	Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC.	DFT	2006	DBLP DOI BibTeX RDF	3D Heterogeneous sensor, redundancy and reconfiguration, energy economization, heterogeneous SOC, J-platform, defect tolerance
1	Álisson Michels, Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro	SET Fault Tolerant Combinational Circuits Based on Majority Logic.	DFT	2006	DBLP DOI BibTeX RDF
1	Geewhun Seok, Il-soo Lee, Tony Ambler, Baxter F. Womack	An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint.	DFT	2006	DBLP DOI BibTeX RDF

Publications at "DFT"( http://dblp.L3S.de/Venues/DFT )