Search results for "FCCM"

Hits ?▲	Authors	Title	Venue	Year	Link
1	James J. Davis 0001, Peter Y. K. Cheung	Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration.	FCCM	2014	DBLP DOI BibTeX RDF
1	Peng Li 0031, Thomas Page, Guojie Luo, Wentai Zhang 0001, Pei Wang, Peng Zhang 0007, Peter Maass, Ming Jiang 0001, Jason Cong	FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation.	FCCM	2014	DBLP DOI BibTeX RDF
1	Saad Arrabi, D. Moore, L. Wang, Kevin Skadron, Benton H. Calhoun, John C. Lach, Brett H. Meyer	Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems.	FCCM	2014	DBLP DOI BibTeX RDF
1	B. Sharat Chandra Varma 0001, Kolin Paul, M. Balakrishnan, Dominique Lavenier	FAssem: FPGA Based Acceleration of De Novo Genome Assembly.	FCCM	2013	DBLP DOI BibTeX RDF
1	Rohit Kumar, Ann Gordon-Ross	PRML: A Modeling Language for Rapid Design Exploration of Partially Reconfigurable FPGAs.	FCCM	2013	DBLP DOI BibTeX RDF
1	Cheng Liu, Colin Yu Lin, Hayden Kwok-Hay So	A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency.	FCCM	2013	DBLP DOI BibTeX RDF
1	Frederico Pratas, Diego Oriato, Oliver Pell, Ricardo A. Mata, Leonel Sousa	Accelerating the Computation of Induced Dipoles for Molecular Mechanics with Dataflow Engines.	FCCM	2013	DBLP DOI BibTeX RDF
1	Nandhini Chandramoorthy, Siddharth Advani, Kevin M. Irick, Vijaykrishnan Narayanan	A Configurable Architecture for a Visual Saliency System and Its Application in Retail.	FCCM	2013	DBLP DOI BibTeX RDF
1	Louis Woods, Gustavo Alonso, Jens Teubner	Parallel Computation of Skyline Queries.	FCCM	2013	DBLP DOI BibTeX RDF
1	Zheming Jin, Jason D. Bakos	Memory Access Scheduling on the Convey HC-1.	FCCM	2013	DBLP DOI BibTeX RDF
1	David B. Thomas	Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard Transform.	FCCM	2013	DBLP DOI BibTeX RDF
1	Arup De, Maya B. Gokhale, Rajesh Gupta 0001, Steven Swanson	Minerva: Accelerating Data Analysis in Next-Generation SSDs.	FCCM	2013	DBLP DOI BibTeX RDF
1	Martin Langhammer, Bogdan Pasca 0001	Elementary Function Implementation with Optimized Sub Range Polynomial Evaluation.	FCCM	2013	DBLP DOI BibTeX RDF
1	Marc-André Daigneault, Jean-Pierre David	High-Level Description and Synthesis of Floating-Point Accumulators on FPGA.	FCCM	2013	DBLP DOI BibTeX RDF
1	Kalin Ovtcharov, Ilian Tili, J. Gregory Steffan	A Multithreaded VLIW Soft Processor Family.	FCCM	2013	DBLP DOI BibTeX RDF
1	Robert J. Halstead, Bharat Sukhwani, Hong Min, Mathew Thoennes, Parijat Dube, Sameh W. Asaad, Balakrishna Iyer	Accelerating Join Operation for Relational Databases with FPGAs.	FCCM	2013	DBLP DOI BibTeX RDF
1	Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang 0002, Wei Xue, Guangwen Yang	Global Atmospheric Simulation on a Reconfigurable Platform.	FCCM	2013	DBLP DOI BibTeX RDF
1	Kizheppatt Vipin, Suhaib A. Fahmy	An Approach to a Fully Automated Partial Reconfiguration Design Flow.	FCCM	2013	DBLP DOI BibTeX RDF
1	Grigorios Mingas, Farhan Rahman, Christos-Savvas Bouganis	On Optimizing the Arithmetic Precision of MCMC Algorithms.	FCCM	2013	DBLP DOI BibTeX RDF
1	Thomas Schweizer, Dustin Peterson, Johannes Maximilian Kühn, Tommy Kuhn, Wolfgang Rosenstiel	A Fast and Accurate FPGA-Based Fault Injection System.	FCCM	2013	DBLP DOI BibTeX RDF
1	Asif Khan 0005, Nirav Dave	Enabling Hardware Exploration in Software-Defined Networking: A Flexible, Portable OpenFlow Switch.	FCCM	2013	DBLP DOI BibTeX RDF
1	Eric S. Chung, Doug Burger, Mike Butts, Jan Gray, Chuck Thacker, Kees A. Vissers, John Wawrzynek	Reconfigurable computing in the era of post-silicon scaling [panel discussion].	FCCM	2013	DBLP DOI BibTeX RDF
1	Kan Shi, David Boland, George A. Constantinides	Accuracy-Performance Tradeoffs on an FPGA through Overclocking.	FCCM	2013	DBLP DOI BibTeX RDF
1	Zhi Ping Ang, Akash Kumar 0001, Yajun Ha	High Speed Video Processing Using Fine-Grained Processing on FPGA Platform.	FCCM	2013	DBLP DOI BibTeX RDF
1	Eric S. Chung, Michael Papamichael	ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects.	FCCM	2013	DBLP DOI BibTeX RDF
1	Zain-ul-Abdin, Bertil Svensson	An Evaluation of High-Performance Embedded Processing on MPPAs.	FCCM	2013	DBLP DOI BibTeX RDF
1	Marco Ceriani, Gianluca Palermo, Simone Secchi, Antonino Tumeo, Oreste Villa	Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping.	FCCM	2013	DBLP DOI BibTeX RDF
1	Nachiket Kapre	Exploiting Input Parameter Uncertainty for Reducing Datapath Precision of SPICE Device Models.	FCCM	2013	DBLP DOI BibTeX RDF
1	Roger Moussalli, Walid A. Najjar, Xi Luo, Amna Khan	A High Throughput No-Stall Golomb-Rice Hardware Decoder.	FCCM	2013	DBLP DOI BibTeX RDF
1	Madhura Purnaprajna, Paolo Ienne	A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers.	FCCM	2013	DBLP DOI BibTeX RDF
1	Jiliang Zhang 0002, Yaping Lin, Yongqiang Lu 0001, Ray C. C. Cheung, Wenjie Che, Qiang Zhou 0001, Jinian Bian	Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits.	FCCM	2013	DBLP DOI BibTeX RDF
1	Shanyuan Gao, Bin Huang, Ron Sass	The Impact of Hardware Communication on a Heterogeneous Computing System.	FCCM	2013	DBLP DOI BibTeX RDF
1	Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu 0011	Automating Elimination of Idle Functions by Run-Time Reconfiguration.	FCCM	2013	DBLP DOI BibTeX RDF
1		21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2013, Seattle, WA, USA, April 28-30, 2013	FCCM	2013	DBLP BibTeX RDF
1	Simin Xu, Suhaib A. Fahmy, Ian Vince McLoughlin	Efficient Large Integer Squarers on FPGA.	FCCM	2013	DBLP DOI BibTeX RDF
1	Christopher Dennl, Daniel Ziener, Jürgen Teich	Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration.	FCCM	2013	DBLP DOI BibTeX RDF
1	James Arram, Kuen Hung Tsoi, Wayne Luk, Peiyong Jiang	Reconfigurable Acceleration of Short Read Mapping.	FCCM	2013	DBLP DOI BibTeX RDF
1	Abid Rafique, Nachiket Kapre, George A. Constantinides	Application Composition and Communication Optimization in Iterative Solvers Using FPGAs.	FCCM	2013	DBLP DOI BibTeX RDF
1	Qijing Huang 0001, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Dean Brown, Jason Helge Anderson	The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs.	FCCM	2013	DBLP DOI BibTeX RDF
1	Scott Buscemi, William V. Kritikos, Ron Sass	A Range and Scaling Study of an FPGA-Based Digital Wireless Channel Emulator.	FCCM	2013	DBLP DOI BibTeX RDF
1	Gonzalo Carvajal, Miguel E. Figueroa, Robert Trausmuth, Sebastian Fischmeister	Atacama: An Open FPGA-Based Platform for Mixed-Criticality Communication in Multi-segmented Ethernet Networks.	FCCM	2013	DBLP DOI BibTeX RDF
1	Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton	Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices.	FCCM	2013	DBLP DOI BibTeX RDF
1	Richard Neil Pittman, Alessandro Forin, Antonio Criminisi, Jamie Shotton, Atabak Mahram	Image Segmentation Using Hardware Forest Classifiers.	FCCM	2013	DBLP DOI BibTeX RDF
1	Yingjie Cao, Yongxin Zhu 0001, Xu Wang 0010, Jiang Jiang, Meikang Qiu	An FPGA Based PCI-E Root Complex Architecture for Standalone SOPCs.	FCCM	2013	DBLP DOI BibTeX RDF
1	Ritesh Kumar Soni, Neil Steiner, Matthew French	Open-Source Bitstream Generation.	FCCM	2013	DBLP DOI BibTeX RDF
1	Aurelio Morales-Villanueva, Ann Gordon-Ross	On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs.	FCCM	2013	DBLP DOI BibTeX RDF
1	Shuo Li 0002, Nasim Farahini, Ahmed Hemani	Global Control and Storage Synthesis for a System Level Synthesis Approach.	FCCM	2013	DBLP DOI BibTeX RDF
1	Ranko Sredojevic, Andrew Wright, Vladimir Stojanovic	Hardware-Software Codesign for Embedded Numerical Acceleration.	FCCM	2013	DBLP DOI BibTeX RDF
1	Yu Bai 0004, Abigail Fuentes-Rivera, Michael Riera, Mohammed Alawad, Mingjie Lin	Boosting Memory Performance of Many-Core FPGA Device through Dynamic Precedence Graph.	FCCM	2013	DBLP DOI BibTeX RDF
1	Miaoqing Huang, Shiming Li	A Delay-based PUF Design Using Multiplexers on FPGA.	FCCM	2013	DBLP DOI BibTeX RDF
1	Qing Sun 0002, Jiang Jiang, Yongxin Zhu 0001, Yuzhuo Fu	A Reconfigurable Architecture for 1-D and 2-D Discrete Wavelet Transform.	FCCM	2013	DBLP DOI BibTeX RDF
1	Abdulazim Amouri, Hussam Amrouch, Thomas Ebi, Jörg Henkel, Mehdi Baradaran Tahoori	Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped Circuits.	FCCM	2013	DBLP DOI BibTeX RDF
1	Trevor Bunker, Steven Swanson	Latency-Optimized Networks for Clustering FPGAs.	FCCM	2013	DBLP DOI BibTeX RDF
1	Jason Cong, Hugh T. Blair, Di Wu 0010	FPGA Simulation Engine for Customized Construction of Neural Microcircuit.	FCCM	2013	DBLP DOI BibTeX RDF
1	Huabin Ruan, Xiaomeng Huang, Haohuan Fu, Guangwen Yang, Wayne Luk, Sébastien Racanière, Oliver Pell, Wenjing Han	An FPGA-Based Data Flow Engine for Gaussian Copula Model.	FCCM	2013	DBLP DOI BibTeX RDF
1	Alexander Brant, Ameer Abdelhadi, Douglas H. H. Sim, Shao Lin Tang, Michael Xi Yue, Guy G. F. Lemieux	Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor.	FCCM	2013	DBLP DOI BibTeX RDF
1	Moritz Schmid, Frank Hannig, Jürgen Teich	Power Management Strategies for Serial RapidIO Endpoints in FPGAs.	FCCM	2012	DBLP DOI BibTeX RDF
1	Yamuna Rajasekhar, Rahul R. Sharma, Ron Sass	An Extensible and Portable Tool Suite for Managing Multi-Node FPGA Systems.	FCCM	2012	DBLP DOI BibTeX RDF
1	Mihalis Psarakis, Aggelos Pikrakis, Giannis Dendrinos	FPGA-based Acceleration for Tracking Audio Effects in Movies.	FCCM	2012	DBLP DOI BibTeX RDF
1	Lars Bauer, Artjom Grudnitsky, Muhammad Shafique 0001, Jörg Henkel	PATS: A Performance Aware Task Scheduler for Runtime Reconfigurable Processors.	FCCM	2012	DBLP DOI BibTeX RDF
1	Berkin Akin, Peter A. Milder, Franz Franchetti, James C. Hoe	Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes.	FCCM	2012	DBLP DOI BibTeX RDF
1	Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung	Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling.	FCCM	2012	DBLP DOI BibTeX RDF
1	Matthew Jacobsen, Yoav Freund, Ryan Kastner	RIFFA: A Reusable Integration Framework for FPGA Accelerators.	FCCM	2012	DBLP DOI BibTeX RDF
1	Shaoyi Cheng, Mingjie Lin, Hao Jun Liu, Simon Scott, John Wawrzynek	Exploiting Memory-Level Parallelism in Reconfigurable Accelerators.	FCCM	2012	DBLP DOI BibTeX RDF
1	George Eichinger, Kaushik R. Chowdhury, Miriam Leeser	Cognitive Radio Universal Software Hardware.	FCCM	2012	DBLP DOI BibTeX RDF
1	Andreas Ehliar	EBRAM - Extending the BlockRAMs in FPGAs to Support Caches and Hash Tables in an Efficient Manner.	FCCM	2012	DBLP DOI BibTeX RDF
1	Grigorios Mingas, Christos-Savvas Bouganis	A Custom Precision Based Architecture for Accelerating Parallel Tempering MCMC on FPGAs without Introducing Sampling Error.	FCCM	2012	DBLP DOI BibTeX RDF
1	Oriol Arcas, Philipp Kirchhofer, Nehir Sönmez, Martin Schindewolf, Osman S. Unsal, Wolfgang Karl, Adrián Cristal	A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory.	FCCM	2012	DBLP DOI BibTeX RDF
1	Christopher Dennl, Daniel Ziener, Jürgen Teich	On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library.	FCCM	2012	DBLP DOI BibTeX RDF
1	Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan	Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing.	FCCM	2012	DBLP DOI BibTeX RDF
1	Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Dimitrios Tsaliagkos, Manolis Katevenis, Dionisios N. Pnevmatikatos, Dimitrios S. Nikolopoulos	Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures.	FCCM	2012	DBLP DOI BibTeX RDF
1	Louis Woods, Ken Eguro	Groundhog - A Serial ATA Host Bus Adapter (HBA) for FPGAs.	FCCM	2012	DBLP DOI BibTeX RDF
1	Srinidhi Kestur, John D. Davis, Eric S. Chung	Towards a Universal FPGA Matrix-Vector Multiplication Architecture.	FCCM	2012	DBLP DOI BibTeX RDF
1	Christian Beckhoff, Dirk Koch, Jim Tørresen	Go Ahead: A Partial Reconfiguration Framework.	FCCM	2012	DBLP DOI BibTeX RDF
1	Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski	Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems.	FCCM	2012	DBLP DOI BibTeX RDF
1	Jing Yan, Zhanxiang Zhao, Ning-Yi Xu, Xi Jin, Lin-Tao Zhang, Feng-Hsiung Hsu	Efficient Query Processing for Web Search Engine with FPGAs.	FCCM	2012	DBLP DOI BibTeX RDF
1	João M. P. Cardoso, João Teixeira, José C. Alves, Ricardo Nobre, Pedro C. Diniz, José Gabriel F. Coutinho, Wayne Luk	Specifying Compiler Strategies for FPGA-based Systems.	FCCM	2012	DBLP DOI BibTeX RDF
1	Hélène Martorell, Nachiket Kapre	FX-SCORE: A Framework for Fixed-Point Compilation of SPICE Device Models Using Gappa++.	FCCM	2012	DBLP DOI BibTeX RDF
1	Rémi Busseuil, Luciano Ost, Rafael Garibotti, Gilles Sassatelli, Michel Robert	Remote Execution in Distributed Memory MPSoC.	FCCM	2012	DBLP DOI BibTeX RDF
1	Simon W. Moore, Paul James Fox, Steven J. T. Marsh, A. Theodore Markettos, Alan Mujumdar	Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation.	FCCM	2012	DBLP DOI BibTeX RDF
1	Gary C. T. Chow, Wayne Luk, Philip Heng Wai Leong	A Mixed Precision Methodology for Mathematical Optimisation.	FCCM	2012	DBLP DOI BibTeX RDF
1	Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi	Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams.	FCCM	2012	DBLP DOI BibTeX RDF
1	Gabriel L. Nazar, Luigi Carro	Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs.	FCCM	2012	DBLP DOI BibTeX RDF
1	Isaac Liu, Edward A. Lee, Matthew Viele, Guoqiang Wang, Hugo A. Andrade	A Heterogeneous Architecture for Evaluating Real-Time One-Dimensional Computational Fluid Dynamics on FPGAs.	FCCM	2012	DBLP DOI BibTeX RDF
1	Xiaolin Chen, Andreas Minwegen, Yahia Hassan, David Kammler, Shuai Li, Torsten Kempf, Anupam Chattopadhyay, Gerd Ascheid	FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP.	FCCM	2012	DBLP DOI BibTeX RDF
1	Wen Tang, Wendi Wang, Bo Duan, Chunming Zhang, Guangming Tan, Peiheng Zhang, Ninghui Sun	Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA Accelerator.	FCCM	2012	DBLP DOI BibTeX RDF
1	Aaron Severance, Guy Lemieux	VENICE: A Compact Vector Processor for FPGA Applications.	FCCM	2012	DBLP DOI BibTeX RDF
1	Alexander Brant, Guy G. F. Lemieux	ZUMA: An Open FPGA Overlay Architecture.	FCCM	2012	DBLP DOI BibTeX RDF
1	Mary Ellen Tie, Miriam Leeser	Implementing Murf: Accelerating Large State Space Exploration on FPGAs.	FCCM	2012	DBLP DOI BibTeX RDF
1	Gabriel Falcão 0001, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne	Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case.	FCCM	2012	DBLP DOI BibTeX RDF
1	Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek	Short-Read Mapping by a Systolic Custom FPGA Computation.	FCCM	2012	DBLP DOI BibTeX RDF
1	Pascal Cotret, Jérémie Crenne, Guy Gogniat, Jean-Philippe Diguet	Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative.	FCCM	2012	DBLP DOI BibTeX RDF
1	Joseph G. Wingbermuehle, Roger D. Chamberlain, Ron K. Cytron	ScalaPipe: A Streaming Application Generator.	FCCM	2012	DBLP DOI BibTeX RDF
1		2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012, 29 April - 1 May 2012, Toronto, Ontario, Canada	FCCM	2012	DBLP BibTeX RDF
1	Eduardo Gudis, Gooitzen S. van der Wal, Sujit Kuthirummal, Sek M. Chai	Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA.	FCCM	2012	DBLP DOI BibTeX RDF
1	Kumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda	Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators.	FCCM	2012	DBLP DOI BibTeX RDF
1	Atabak Mahram, Martin C. Herbordt	FMSA: FPGA-Accelerated ClustalW-Based Multiple Sequence Alignment through Pipelined Prefiltering.	FCCM	2012	DBLP DOI BibTeX RDF
1	Brian Van Essen, Chris Macaraeg, Maya B. Gokhale, Ryan Prenger	Accelerating a Random Forest Classifier: Multi-Core, GP-GPU, or FPGA?	FCCM	2012	DBLP DOI BibTeX RDF
1	Manish Kumar Jaiswal, Ray C. C. Cheung	Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers.	FCCM	2012	DBLP DOI BibTeX RDF
1	Corey B. Olson, Maria Kim, Cooper Clauson, Boris Kogon, Carl Ebeling, Scott Hauck, Walter L. Ruzzo	Hardware Acceleration of Short Read Mapping.	FCCM	2012	DBLP DOI BibTeX RDF

Publications at "FCCM"( http://dblp.L3S.de/Venues/FCCM )