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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1086 occurrences of 496 keywords
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Results
Found 1618 publication records. Showing 1618 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Hongyuan Ding, Miaoqing Huang |
An Automatic Design Flow for Hybrid Parallel Computing on MPSoCs (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Gerardo Soria García, Adrian Pedroza de-la-Crúz, Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Eduardo Bayro-Corrochano |
A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory Arrays (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica |
System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura |
Sequence-based In-Circuit Breakpoints for Post-Silicon Debug (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zhilei Chai, Jin Yu, Zhibin Wang, Jie Zhang, Haojie Zhou |
An Embedded FPGA Operating System Optimized for Vision Computing (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Joseph G. Wingbermuehle, Ron K. Cytron, Roger D. Chamberlain |
Superoptimized Memory Subsystems for Streaming Applications. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache |
A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | George A. Constantinides, Deming Chen (eds.) |
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015 |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Seung Yeol Baik, Seokjin Jeong, Hyeong-Cheol Oh |
Design of a Loeffler DCT using Xilinx Vivado HLS (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Aaron Severance, Joe Edwards, Guy G. F. Lemieux |
Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Marko Jacovic, James Chacko, Doug Pfeil, Nagarajan Kandasamy, Kapil R. Dandekar |
FPGA Implementation of Trained Coarse Carrier Frequency Offset Estimation and Correction for OFDM Signals (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Naoto Nojiri, Lin Meng, Katsuhiro Yamazaki |
FPGA-based BLOB Detection Using Dual-pipelining (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Xianjian Zheng, Fan Zhang, Lei Chen 0010, Zhiping Wen 0001, Yuanfu Zhao, Xuewu Li |
A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Gorker Alp Malazgirt, Nehir Sönmez, Arda Yurdakul, Osman S. Unsal, Adrián Cristal |
Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Bo Wang 0023, Leibo Liu |
REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Harald Homulle, Francesco Regazzoni 0001, Edoardo Charbon |
200 MS/s ADC implemented in a FPGA employing TDCs. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Umer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar |
MedianPipes: An FPGA based Highly Pipelined and Scalable Technique for Median Filtering (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene |
Technology Mapping into General Programmable Cells. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Edin Kadric, David Lakata, André DeHon |
Impact of Memory Architecture on FPGA Energy Consumption. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Tomasz S. Czajkowski |
Silicon Verification using High-Level Design Tools (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yutaro Ishigaki, Ning Li, Yoichi Tomioka, Akihiko Miyazaki, Hitoshi Kitazawa |
An FPGA-Based Accelerator for the 2D Implicit FDM and Its Application to Heat Conduction Simulations (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings |
RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Makoto Miyamura, Toshitsugu Sakamoto, Yukihide Tsuji, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada |
0.5-V Highly Power-Efficient Programmable Logic using Nonvolatile Configuration Switch in BEOL. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Wentai Zhang 0001, Li Shen, Thomas Page, Guojie Luo, Peng Li 0031, Peter Maaß, Ming Jiang 0001, Jason Cong |
FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Alban Bourge, Olivier Muller, Frédéric Rousseau 0001 |
A Novel Method for Enabling FPGA Context-Switch (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Chen Zhang 0001, Peng Li 0031, Guangyu Sun 0003, Yijin Guan, Bingjun Xiao, Jason Cong |
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Danyal Mohammadi, Said Ahmed-Zaid, Nader Rafla 0001 |
Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ephrem Wu, Inkeun Cho |
Physical Design Space Exploration. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Chao Wang 0003, Xi Li 0003, Qi Guo, Xuehai Zhou |
RapidPath: Accelerating Constrained Shortest Path Finding in Graphs on FPGA (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Peng Li 0031, Peng Zhang 0007, Louis-Noël Pouchet, Jason Cong |
Resource-Aware Throughput Optimization for High-Level Synthesis. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Charles Mutigwe, Johnson Kinyua, Farhad Aghdasi |
FiT: An Automated Toolkit for Matching Processor Architecture to Applications (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | James Arram, Wayne Luk, Peiyong Jiang |
Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ren Chen, Sruja Siriyal, Viktor K. Prasanna |
Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev |
An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mohammed Alawad, Mingjie Lin |
Energy-Efficient High-Order FIR Filtering through Reconfigurable Stochastic Processing (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Martin Langhammer, Bogdan Pasca 0001 |
Floating-Point DSP Block Architecture for FPGAs. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Xu Bai, Yukihide Tsuji, Ayuka Morioka, Makoto Miyamura, Toshi Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada |
Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mingxing Tan, Steve Dai, Udit Gupta, Zhiru Zhang |
Mapping-Aware Constrained Scheduling for LUT-Based FPGAs. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Masahiro Fujita |
On Implementation of LUT with Large Numbers of Inputs (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sanmukh R. Kuppannagari, Viktor K. Prasanna |
Efficient Generation of Energy and Performance Pareto Front for FPGA Designs (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ryota Takasu, Yoichi Tomioka, Takashi Aoki, Hitoshi Kitazawa |
An FPGA Implementation of Multi-stream Tracking Hardware using 2D SIMD Array (Abstract Only). |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Myron King, Jamey Hicks, John Ankcorn |
Software-Driven Hardware Development. |
FPGA |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Alessandro Antonio Nacci, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto |
Improving the security and the scalability of the AES algorithm (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Hanyang Xu, Jian Wang 0036, Meilai Jin |
A FPGA prototype design emphasis on low power technique. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | André DeHon |
Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne |
Revisiting and-inverter cones. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Farnaz Gharibian, Lesley Shannon, Peter Jamieson |
A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Kevin E. Murray, Vaughn Betz |
Quantifying the cost and benefit of latency insensitive communication on FPGAs. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Hao Liang 0003, Yi-Chung Chen, Wei Zhang 0012, Hai Li 0001 |
Hierarchical library-based power estimator for versatile FPGAs (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Fubing Mao, Yi-Chung Chen, Wei Zhang 0012, Hai Li 0001 |
BMP: a fast B*-tree based modular placer for FPGAs (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Tao Ai, Mir Adnan Ali, J. Gregory Steffan, Kalin Ovtcharov, Sarmad Zulfiqar, Steve Mann 0001 |
Producing high-quality real-time HDR video system with FPGA (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Lei Li, Jian Wang 0036, Jinmei Lai |
Novel FPGA clock network with low latency and skew (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Matthias Hinkfoth, Ralf Joost, Ralf Salomon |
Exploring duty cycle distortions along signal paths in FPGAs (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Rui Policarpo Duarte, Christos-Savvas Bouganis |
Pushing the performance boundary of linear projection designs through device specific optimisations (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Zhibin Wang, Wenmin Yang, Jin Yu, Zhilei Chai |
Implementing FPGA-based energy-efficient dense optical flow computation with high portability in C (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Sen Ma, David Andrews 0001 |
On energy efficiency and amdahl's law in FPGA based chip heterogeneous multiprocessor systems (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Artjom Grudnitsky, Lars Bauer, Jörg Henkel |
MORP: makespan optimization for processors with an embedded reconfigurable fabric. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Jason Cong, Muhuan Huang, Peng Zhang 0007 |
Combining computation and communication optimizations in system synthesis for streaming applications. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | James Lamberti, Devu Manikantan Shila, Vivek Venugopal |
xDEFENSE: an extended DEFENSE for mitigating next generation intrusions (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Aaron Severance, Joe Edwards, Hossein Omidian, Guy Lemieux |
Soft vector processors with streaming pipelines. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Richard Dorrance, Fengbo Ren, Dejan Markovic |
A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Nick Ni |
Methodology to generate multi-dimensional systolic arrays for FPGAs using openCL (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue |
Memory block based scan-BIST architecture for application-dependent FPGA testing. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Aitzan Sari, Dimitris Agiakatsikas, Mihalis Psarakis |
A soft error vulnerability analysis framework for Xilinx FPGAs. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Christoforos Kachris, Georgios Ch. Sirakoulis, Dimitrios Soudris |
A configurable mapreduce accelerator for multi-core FPGAs (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Safeen Huda, Jason Helge Anderson, Hirotaka Tamura |
Optimizing effective interconnect capacitance for FPGA power reduction. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Chao Wang 0003, Xi Li 0003, Xuehai Zhou, Yunji Chen, Ray C. C. Cheung |
Big data genome sequencing on Zynq based clusters (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen |
Fast and effective placement and routing directed high-level synthesis for FPGAs. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Lee W. Lerner, Zane R. Franklin, William T. Baumann, Cameron D. Patterson |
Using high-level synthesis and formal analysis to predict and preempt attacks on industrial control systems. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Yanzi Zhu, Peiran Suo, Kia Bazargan |
Binary stochastic implementation of digital logic. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Simin Xu, Suhaib A. Fahmy, Ian Vince McLoughlin |
Square-rich fixed point polynomial evaluation on FPGAs. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado |
A power-efficient adaptive heapsort for fpga-based image coding application (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Yuliang Sun, Zilong Wang, Sitao Huang, Lanjun Wang, Yu Wang 0002, Rong Luo, Huazhong Yang |
Accelerating frequent item counting with FPGA. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | André Hahn Pereira, Vaughn Betz |
Cad and routing architecture for interposer-based multi-FPGA systems. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Jasmina Vasiljevic, Paul Chow |
MPack: global memory optimization for stream applications in high-level synthesis. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Vaughn Betz, George A. Constantinides (eds.) |
The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, USA - February 26 - 28, 2014 |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Jian Gong, Jiahua Chen, Haoyang Wu, Fan Ye 0003, Songwu Lu, Jason Cong, Tao Wang 0004 |
EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Yu Wang 0136, Donghoon Yeo, Muhammad Sohail 0003, Hyunchul Shin |
Control signal aware slice-level window based legalization method for FPGA placement (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Viktor Pus, Lukas Kekely, Tomás Závodník |
Using DSP blocks to compute CRC hash in FPGA (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Georgios Smaragdos, Sebastián Isaza, Martijn F. van Eijk, Ioannis Sourdis, Christos Strydis |
FPGA-based biophysically-meaningful modeling of olivocerebellar neurons. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung |
Dynamic voltage & frequency scaling with online slack measurement. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Fan Zhang, Lei Chen 0010, Wenyao Xu, Yuanfu Zhao, Zhiping Wen 0001 |
Coordinating routing resources for hex pips test in island-style FPGAs (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Lin Meng, Keisuke Matsuyama, Naoto Nojiri, Tomonori Izumi, Katsuhiro Yamazaki |
Pipelining FPPGA-based defect detction in FPDs (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Jason Luu, Jonathan Rose, Jason Helge Anderson |
Towards interconnect-adaptive packing for FPGAs. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Yu Bai 0004, Mohammed Alawad, Mingjie Lin |
Optimally mitigating BTI-induced FPGA device aging with discriminative voltage scaling (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Qian Zhang 0020, Chenfei Ma, Qiang Xu 0001 |
On hybrid memory allocation for FPGA behavioral synthesis (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Bernhard Schmidt, Daniel Ziener, Jürgen Teich |
An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Devu Manikantan Shila, Vivek Venugopal |
Design, implementation and security analysis of hardware trojan threats in FPGA (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Yuxin Wang, Peng Li 0031, Jason Cong |
Theory and algorithm for generalized memory partitioning in high-level synthesis. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Santhosh Kumar Rethinagiri |
APMC: advanced pattern based memory controller (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Jared Casper, Kunle Olukotun |
Hardware acceleration of database operations. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Chunming Zhang, Wen Tang, Guangming Tan |
Accelerating massive short reads mapping for next generation sequencing (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young |
A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Monther Abusultan, Sunil P. Khatri |
FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Giovanni De Micheli |
A new basic logic structure for data-path computation (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Ce Guo, Wayne Luk |
Accelerating parameter estimation for multivariate self-exciting point processes. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache |
Redefining the role of FPGAs in the next generation avionic systems (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Antonio Filgueras, Eduard Gil, Daniel Jiménez-González, Carlos Álvarez 0001, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers |
OmpSs@Zynq all-programmable SoC ecosystem. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Sang Woo Jun, Ming Liu, Kermin Elliott Fleming, Arvind |
Scalable multi-access flash store for big data analytics. |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
|
1 | Chao Wang 0003, Xi Li 0003, Xuehai Zhou, Yunji Chen, Koen Bertels |
Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs (abstract only). |
FPGA |
2014 |
DBLP DOI BibTeX RDF |
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