Search results for "ISQED"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Hao Zheng 0001, Yuting Cao, Sandip Ray, Jin Yang 0006	Protocol-guided analysis of post-silicon traces under limited observability.	ISQED	2016	DBLP DOI BibTeX RDF
1	Venkata Yaswanth Raparti, Sudeep Pasricha	Memory-aware circuit overlay NoCs for latency optimized GPGPU architectures.	ISQED	2016	DBLP DOI BibTeX RDF
1	Sukru Burc Eryilmaz, Siddharth Joshi, Emre Neftci, Weier Wan, Gert Cauwenberghs, H.-S. Philip Wong	Neuromorphic architectures with electronic synapses.	ISQED	2016	DBLP DOI BibTeX RDF
1	Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Arnaud Virazel, Leonardo Bonet Zordan	An effective BIST architecture for power-gating mechanisms in low-power SRAMs.	ISQED	2016	DBLP DOI BibTeX RDF
1	Peter Sarson	Very low supply voltage room temperature test to screen low temperature soft blown fuse fails which result in a resistive bridge.	ISQED	2016	DBLP DOI BibTeX RDF
1	Tan Chee Phang, Mohammad Harris Mokhtar, Mohd Nazim Mokhtar, Fakhrul Zaman Rokhani	Time-division multiple access based intra-body communication for wearable health tracker.	ISQED	2016	DBLP DOI BibTeX RDF
1	Dan Christiani, Cory E. Merkel, Dhireesha Kudithipudi	Invited: Towards a scalable neuromorphic hardware for classification and prediction with stochastic No-Prop algorithms.	ISQED	2016	DBLP DOI BibTeX RDF
1	Hua Xiang 0001, Lakshmi N. Reddy, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu	Gate movement for timing improvement on row based Dual-VDD designs.	ISQED	2016	DBLP DOI BibTeX RDF
1	Victor Moroz, Joanne Huang, Reza Arghavani	Transistor design for 5nm and beyond: Slowing down electrons to speed up transistors.	ISQED	2016	DBLP DOI BibTeX RDF
1	Victor Huang, Chenyun Pan, Dmitry Yakimets, Praveen Raghavan, Azad Naeemi	Device/system performance modeling of stacked lateral NWFET logic.	ISQED	2016	DBLP DOI BibTeX RDF
1	Hari Shanker Gupta, Satyajit Mohapatra, Nihar R. Mohapatra, Dinesh Kumar Sharma	Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array.	ISQED	2016	DBLP DOI BibTeX RDF
1	Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu	On testing physically unclonable functions for uniqueness.	ISQED	2016	DBLP DOI BibTeX RDF
1	Theodore Winograd, Hassan Salmani, Hamid Mahmoodi, Houman Homayoun	Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates.	ISQED	2016	DBLP DOI BibTeX RDF
1	Ji Li 0006, Yanzhi Wang, Xue Lin, Shahin Nazarian, Massoud Pedram	Negotiation-based resource provisioning and task scheduling algorithm for cloud systems.	ISQED	2016	DBLP DOI BibTeX RDF
1	Kareem Madkour, Sarah Mohamed, Dina Tantawy, Mohab Anis	Hotspot detection using machine learning.	ISQED	2016	DBLP DOI BibTeX RDF
1	Tiansong Cui, Ji Li 0006, Alireza Shafaei, Shahin Nazarian, Massoud Pedram	An efficient timing analysis model for 6T FinFET SRAM using current-based method.	ISQED	2016	DBLP DOI BibTeX RDF
1	Jizhe Zhang, Sandeep K. Gupta 0001	Yield estimation and statistical design of memristor cross-point memory systems.	ISQED	2016	DBLP DOI BibTeX RDF
1	Sriram Balasubramanian, Ninad Pimparkar, Mangesh Kushare, Vinayak Mahajan, Juhi Bansal, Takashi Shimizu, Vivek Joshi, Kun Qian, Arunima Dasgupta, Karthik Chandrasekaran, Chad Weintraub, Ali Icel	Near-threshold circuit variability in 14nm FinFETs for ultra-low power applications.	ISQED	2016	DBLP DOI BibTeX RDF
1	A. Asenov, Yangang Wang, Binjie Cheng, Xingsheng Wang, Plamen Asenov, Talib Al-Ameri, Vihar P. Georgiev	Nanowire transistor solutions for 5nm and beyond.	ISQED	2016	DBLP DOI BibTeX RDF
1	Jinyoung Lee, Sunghee Yun, Jeongha Kim, Dongsoo Kang, Jeongyeol Kim, Sanghoon Lee	Multiple shift-vector importance sampling method using support vector machine and clustering for high-density DRAM designs.	ISQED	2016	DBLP DOI BibTeX RDF
1	Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu	Preventing integrated circuit piracy via custom encoding of hardware instruction set.	ISQED	2016	DBLP DOI BibTeX RDF
1	Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa	A delay variation and floorplan aware high-level synthesis algorithm with body biasing.	ISQED	2016	DBLP DOI BibTeX RDF
1	Ming Fan, Rong Rong, Xinwei Niu	On-line harmonic-aware partitioned scheduling for real-time multi-core systems under RMS.	ISQED	2016	DBLP DOI BibTeX RDF
1	Javaneh Mohseni, Chenyun Pan, Azad Naeemi	Performance modeling and optimization for on-chip interconnects in 3D memory arrays.	ISQED	2016	DBLP DOI BibTeX RDF
1	Sheng-En David Lin, Partha Pratim Pande, Dae Hyun Kim 0004	Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs.	ISQED	2016	DBLP DOI BibTeX RDF
1	Jiqin Zhou, Weigong Zhang, Keni Qiu, Xiaoyan Zhu	UM-BUS: An online fault-tolerant bus for embedded systems.	ISQED	2016	DBLP DOI BibTeX RDF
1	Shuang Zhu, Jingyi Song, Balaji Chellappa, Ali Enteshari, Tuo Shan, Mengxun He, Yun Chiu	A smart ECG sensor with in-situ adaptive motion-artifact compensation for dry-contact wearable healthcare devices.	ISQED	2016	DBLP DOI BibTeX RDF
1	Hemanta Kumar Mondal, Sri Harsha Gade, Raghav Kishore, Shashwat Kaushik, Sujay Deb	Power efficient router architecture for wireless Network-on-Chip.	ISQED	2016	DBLP DOI BibTeX RDF
1	Divya Prasad, Chenyun Pan, Azad Naeemi	Impact of interconnect variability on circuit performance in advanced technology nodes.	ISQED	2016	DBLP DOI BibTeX RDF
1	Hengyu Zhao, Hongbin Sun 0001, Qiang Yang, Tai Min, Nanning Zheng 0001	Exploring the use of volatile STT-RAM for energy efficient video processing.	ISQED	2016	DBLP DOI BibTeX RDF
1	Tianhong Ye, Kuan W. A. Chee	Ruggedness evaluation and design improvement of automotive power MOSFETs.	ISQED	2016	DBLP DOI BibTeX RDF
1	Luca Bochi Saldanha, Christophe Bobda	Sparsely connected neural networks in FPGA for handwritten digit recognition.	ISQED	2016	DBLP DOI BibTeX RDF
1	Brian Cline, Saibal Mukhopadhyay, Peter J. Wright, Hai Li, Vinod Viswanath, Paul Wesling, Gang Qu 0001, Ali Iranmanesh	Welcome.	ISQED	2016	DBLP DOI BibTeX RDF
1	Yuanwen Huang, Prabhat Mishra 0001	Reliability and energy-aware cache reconfiguration for embedded systems.	ISQED	2016	DBLP DOI BibTeX RDF
1	Harsh N. Patel, Farah B. Yahya, Benton H. Calhoun	Optimizing SRAM bitcell reliability and energy for IoT applications.	ISQED	2016	DBLP DOI BibTeX RDF
1	Tiantao Lu, Zhiyuan Yang 0001, Ankur Srivastava 0001	Electromigration-aware placement for 3D-ICs.	ISQED	2016	DBLP DOI BibTeX RDF
1	Mohsen Imani, Shruti Patil, Tajana Simunic Rosing	Low power data-aware STT-RAM based hybrid cache architecture.	ISQED	2016	DBLP DOI BibTeX RDF
1	Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel	Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications.	ISQED	2016	DBLP DOI BibTeX RDF
1	Amey M. Kulkarni, Youngok K. Pino, Tinoosh Mohsenin	SVM-based real-time hardware Trojan detection for many-core platform.	ISQED	2016	DBLP DOI BibTeX RDF
1	Seogoo Lee, Dongwook Lee, Kyungtae Han, Emily Shriver, Lizy K. John, Andreas Gerstlauer	Statistical quality modeling of approximate hardware.	ISQED	2016	DBLP DOI BibTeX RDF
1	Anteneh Gebregiorgis, Fabian Oboril, Mehdi Baradaran Tahoori, Said Hamdioui	Instruction cache aging mitigation through Instruction Set Encoding.	ISQED	2016	DBLP DOI BibTeX RDF
1	Siddharth S. Bhargav, Andrew Kolb, Young H. Cho	Accelerating physical level sub-component power simulation by online power partitioning.	ISQED	2016	DBLP DOI BibTeX RDF
1	Nga Dang, Zana Ghaderi, Moonju Park, Eli Bozorgzadeh	Harvesting-aware adaptive energy management in solar-powered embedded systems.	ISQED	2016	DBLP DOI BibTeX RDF
1	Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa	In-situ Trojan authentication for invalidating hardware-Trojan functions.	ISQED	2016	DBLP DOI BibTeX RDF
1	Fatih Karabacak, Ümit Y. Ogras, Sule Ozev	Detection of malicious hardware components in mobile platforms.	ISQED	2016	DBLP DOI BibTeX RDF
1	Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim	Monolithic 3D IC design: Power, performance, and area impact at 7nm.	ISQED	2016	DBLP DOI BibTeX RDF
1	Toru Nakura, Kunihiro Asada	Fully automated PLL compiler generating final GDS from specification.	ISQED	2016	DBLP DOI BibTeX RDF
1	Ayushparth Sharma, Kusum Lata	Low-leakage and process-variation-tolerant write-read disturb-free 9T SRA cell using CMOS and FinFETs.	ISQED	2016	DBLP DOI BibTeX RDF
1	Miao Hu, John Paul Strachan, Zhiyong Li, R. Stanley Williams	Dot-product engine as computing memory to accelerate machine learning algorithms.	ISQED	2016	DBLP DOI BibTeX RDF
1	Eman El Mandouh, Amr G. Wassal	Covgen: A framework for automatic extraction of functional coverage models.	ISQED	2016	DBLP DOI BibTeX RDF
1	Song Bian 0001, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato	Nonlinear delay-table approach for full-chip NBTI degradation prediction.	ISQED	2016	DBLP DOI BibTeX RDF
1	Deepak-Kumar Arora, Darayus Adil Patel, Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto Bosio	Analysis of setup and hold margins inside silicon for advanced technology nodes.	ISQED	2016	DBLP DOI BibTeX RDF
1	Navid Khoshavi, Xunchao Chen, Jun Wang 0001, Ronald F. DeMara	Bit-Upset Vulnerability Factor for eDRAM Last Level Cache immunity analysis.	ISQED	2016	DBLP DOI BibTeX RDF
1	Meng-Yen Wu, Meng-Hsueh Chiang	Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes.	ISQED	2016	DBLP DOI BibTeX RDF
1	M. Amimul Ehsan, Hongyu An, Zhen Zhou, Yang Yi 0002	Design challenges and methodologies in 3D integration for neuromorphic computing systems.	ISQED	2016	DBLP DOI BibTeX RDF
1	Mohamed Baker Alawieh, Fa Wang, Rouwaida Kanj, Xin Li 0001, Rajiv V. Joshi	Efficient analog circuit optimization using sparse regression and error margining.	ISQED	2016	DBLP DOI BibTeX RDF
1	Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula	Digital IP protection using threshold voltage control.	ISQED	2016	DBLP DOI BibTeX RDF
1	Fazal Hameed, Mehdi Baradaran Tahoori	Architecting STT Last-Level-Cache for performance and energy improvement.	ISQED	2016	DBLP DOI BibTeX RDF
1	Zheyu Liu, Fei Qiao, Qi Wei 0001, Xinghua Yang, Yi Li, Huazhong Yang	An ultra-fast and low-power design of analog circuit network for DoG pyramid construction of SIFT algorithm.	ISQED	2016	DBLP DOI BibTeX RDF
1	Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera	Variability- and correlation-aware logical effort for near-threshold circuit design.	ISQED	2016	DBLP DOI BibTeX RDF
1	Alireza Shafaei, Yanzhi Wang, Lizhong Chen, Shuang Chen 0001, Massoud Pedram	Maximizing the performance of NoC-based MPSoCs under total power and power density constraints.	ISQED	2016	DBLP DOI BibTeX RDF
1	Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee	Trojan detection in digital systems using current sensing of pulse propagation in logic gates.	ISQED	2016	DBLP DOI BibTeX RDF
1	Abhishek Roy 0002, Peter J. Grossmann, Steven A. Vitale, Benton H. Calhoun	A 1.3µW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications.	ISQED	2016	DBLP DOI BibTeX RDF
1	Seyed Alireza Pourbakhsh, Xiaowei Chen, Dongliang Chen, Xin Wang, Na Gong, Jinhui Wang	Sizing-priority based low-power embedded memory for mobile video applications.	ISQED	2016	DBLP DOI BibTeX RDF
1	Noha Gamal, Hossam A. H. Fahmy, Yehea I. Ismail, Hassan Mostafa	Design guidelines for embeded NoCs on FPGAs.	ISQED	2016	DBLP DOI BibTeX RDF
1	Zhong Guan, Malgorzata Marek-Sadowska	AFD-based method for signal line EM reliability evaluation.	ISQED	2016	DBLP DOI BibTeX RDF
1	Shilpa Pendyala, Srinivas Katkoori	State encoding based NBTI optimization in finite state machines.	ISQED	2016	DBLP DOI BibTeX RDF
1	Fatih Karabacak, Uwadiae Obahiagbon, Ümit Y. Ogras, Sule Ozev, Jennifer Blain Christen	Making unreliable Chem-FET sensors smart via soft calibration.	ISQED	2016	DBLP DOI BibTeX RDF
1	Khaja Ahmad Shaik, Kiyoo Itoh 0002, Amara Amara	0.5-V 50-mV-swing 1.2-GHz 28-nm-FD-SOI 32-bit dynamic bus architecture with dummy bus.	ISQED	2016	DBLP DOI BibTeX RDF
1		17th International Symposium on Quality Electronic Design, ISQED 2016, Santa Clara, CA, USA, March 15-16, 2016	ISQED	2016	DBLP BibTeX RDF
1	Masahiro Kano, Toru Nakura, Kunihiro Asada	Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise.	ISQED	2016	DBLP DOI BibTeX RDF
1	Steven Paley, Tamzidul Hoque, Swarup Bhunia	Active protection against PCB physical tampering.	ISQED	2016	DBLP DOI BibTeX RDF
1	Lang Zhang, Hai Wang 0002, Sheldon X.-D. Tan	Fast stress analysis for runtime reliability enhancement of 3D IC using artificial neural network.	ISQED	2016	DBLP DOI BibTeX RDF
1	Anirban Sengupta, Saumya Bhadauria	User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis.	ISQED	2015	DBLP DOI BibTeX RDF
1	Zhen Meng, Song Chen 0001, Lu Huang	Irregularly shaped voltage islands generation with hazard and heal strategy.	ISQED	2015	DBLP DOI BibTeX RDF
1	Gustavo K. Contreras, Yang Zhao, Nisar Ahmed, LeRoy Winemberg, Mohammad Tehranipoor	LBIST pattern reduction by learning ATPG test cube properties.	ISQED	2015	DBLP DOI BibTeX RDF
1	Azzedin D. Es-Sakhi, Masud H. Chowdhury	Partially depleted silicon-on-ferroelectric insulator field effect transistor (PD-SOFFET).	ISQED	2015	DBLP DOI BibTeX RDF
1	Mohammad Saber Golanbari, Saman Kiamehr, Mehdi Baradaran Tahoori, Sani R. Nassif	Analysis and optimization of flip-flops under process and runtime variations.	ISQED	2015	DBLP DOI BibTeX RDF
1	Chao Deng, Yici Cai, Qiang Zhou 0001	Fast synthesis of low power clock trees based on register clustering.	ISQED	2015	DBLP DOI BibTeX RDF
1	Marco P. Stefani, Thais Webber, Ramon Fernandes, Rodrigo Cataldo, Leticia B. Poehls, César A. M. Marcon	Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs.	ISQED	2015	DBLP DOI BibTeX RDF
1	Subramanian Chebiyam, Anshuman Chandra, Rohit Kapur	Designing effective scan compression solutions for industrial circuits.	ISQED	2015	DBLP DOI BibTeX RDF
1	George Gonzalez, Murari Mani, Mahesh Sharma	Large-scale multi-corner leakage optimization under the sign-off timing environment.	ISQED	2015	DBLP DOI BibTeX RDF
1	Govardhana Rao Talluri, K. K. Rakesh, Maryam Shojaei Baghini	A 4-14 Gbps inductor-less adaptive linear equalizer using hybrid filter in 65 nm CMOS technology.	ISQED	2015	DBLP DOI BibTeX RDF
1	Yanbo Niu, Anping Jiang	The low power design of SM4 cipher with resistance to differential power analysis.	ISQED	2015	DBLP DOI BibTeX RDF
1	Lan Wu, Wei Zhang 0002	Cache-aware SPM allocation algorithms for hybrid SPM-cache architectures.	ISQED	2015	DBLP DOI BibTeX RDF
1	Woosung Lee, Keewon Cho, Jooyoung Kim, Sungho Kang	Near optimal repair rate built-in redundancy analysis with very small hardware overhead.	ISQED	2015	DBLP DOI BibTeX RDF
1	Miroslav N. Velev, Chaoqiang Zhang, Ping Gao 0002, Alex David Groce	Exploiting abstraction, learning from random simulation, and SVM classification for efficient dynamic prediction of software health problems.	ISQED	2015	DBLP DOI BibTeX RDF
1	Alireza Shafaei, Yanzhi Wang, Antonio Petraglia, Massoud Pedram	Design optimization of sense amplifiers using deeply-scaled FinFET devices.	ISQED	2015	DBLP DOI BibTeX RDF
1	Yucai Wang, Vamsy P. Chodavarapu	Design of a sigma-delta modulator in standard CMOS process for wide-temperature applications.	ISQED	2015	DBLP DOI BibTeX RDF
1	Ya-Chi Huang, Meng-Hsueh Chiang, Wei-Chou Hsu, Shiou-Ying Cheng	6-T SRAM performance assessment with stacked silicon nanowire MOSFETs.	ISQED	2015	DBLP DOI BibTeX RDF
1	Kaushik Mazumdar, Steven Bartling, Sudhanshu Khanna, Mircea R. Stan	A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU.	ISQED	2015	DBLP DOI BibTeX RDF
1	Nga Dang, Hossein Tajik, Nikil D. Dutt, Nalini Venkatasubramanian, Eli Bozorgzadeh	Orchestrated application quality and energy storage management in solar-powered embedded systems.	ISQED	2015	DBLP DOI BibTeX RDF
1	Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov	Circuit design perspectives for Ge FinFET at 10nm and beyond.	ISQED	2015	DBLP DOI BibTeX RDF
1	Shen Feng, Chris Driscoll, Jerediah R. Fevold, Hao Jiang, Gunar Schirner	Rapid heterogeneous prototyping from Simulink.	ISQED	2015	DBLP DOI BibTeX RDF
1	Sharad Bagri, Kelson Gent, Michael S. Hsiao	Signal domain based reachability analysis in RTL circuits.	ISQED	2015	DBLP DOI BibTeX RDF
1	Dharanidhar Dang, Biplab Patra, Rabi N. Mahapatra	A 2-layer laser multiplexed photonic network-on-chip.	ISQED	2015	DBLP DOI BibTeX RDF
1	Chenyun Pan, Praveen Raghavan, Francky Catthoor, Zsolt Tokei, Azad Naeemi	Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.	ISQED	2015	DBLP DOI BibTeX RDF
1	Rajat Chauhan, Prajkta Vyavahare, Siva Kothamasu	Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system power.	ISQED	2015	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan Mishchenko	Incremental ATPG methods for multiple faults under multiple fault models.	ISQED	2015	DBLP DOI BibTeX RDF
1	Spandana Rachamalla, Arun Joseph, Rahul M. Rao, Diwesh Pandey	Virtual logic netlist: Enabling efficient RTL analysis.	ISQED	2015	DBLP DOI BibTeX RDF

Publications at "ISQED"( http://dblp.L3S.de/Venues/ISQED )