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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 79 occurrences of 73 keywords
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Results
Found 1930 publication records. Showing 1930 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Shuyu Kong, Jie Gu 0001, Hai Zhou 0001 |
Memristor-Based Clock Design and Optimization with In-Situ Tunability.  |
ISVLSI  |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitrios Balobas, Nikos Konofaos |
High-Performance and Energy-Efficient 256-Bit CMOS Priority Encoder. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Amr M. S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei |
Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Deliang Fan, Shaahin Angizi, Zhezhi He |
In-Memory Computing with Spintronic Devices. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tannu Sharma, Kenneth S. Stevens |
Physical Design Variation in Relative Timed Asynchronous Circuits. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Vasilios I. Kelefouras, Georgios Keramidas, Nikolaos S. Voros |
Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumit Khalapure, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha |
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Friedrichs, Attila Kinali |
Efficient Metastability-Containing Multiplexers. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys |
NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Taylor J. L. Whitaker, Christophe Bobda |
CAPSL: The Component Authentication Process for Sandboxed Layouts. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Marcelo Ruaro, Henrique Martins Medina, Fernando Gehm Moraes |
SDN-Based Circuit-Switching for Many-Cores. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hua Fan 0001, Franco Maloberti, Dagang Li, Daqian Hu, Yuanjun Cen, Hadi Heidari |
Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Lakshmi Bhamidipati, Bhoopal Gunna, Houman Homayoun, Avesta Sasan |
A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sam Gianelli, Tosiron Adegbija |
PACT: Priority-Aware Phase-Based Cache Tuning for Embedded Systems. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Georgios Keramidas, Nikolaos S. Voros, Christos P. Antonopoulos, Fynn Schwiegelshohn, Philipp Wehner, Diana Göhringer, Evaggelinos P. Mariatos |
Profile-Driven Power Optimizations for AAL Robots: Maximizing Robots Idle Time by Offloading Monitoring Workload to Dedicated Hardware Components. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Alex Pappachen James, Olga Krestinskaya, Joshin John Mathew |
Unified Model for Contrast Enhancement and Denoising. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha |
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Leonel Acunha Guimaraes, Rodrigo Possamai Bastos, Laurent Fesquet |
Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Shvan Karim, Jim Harkin, Liam McDaid, Bryan Gardiner, Junxiu Liu, David M. Halliday, Andy M. Tyrrell, Jon Timmis, Alan G. Millard, Anju P. Johnson |
Assessing Self-Repair on FPGAs with Biologically Realistic Astrocyte-Neuron Networks. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rakshit Pathak, Saurav Dash, Anand Kumar Mukhopadhyay, Arindam Basu, Mrigank Sharad |
Low Power Implantable Spike Sorting Scheme Based on Neuromorphic Classifier with Supervised Training Engine. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jens Rettkowski, Diana Göhringer |
Data Stream Processing in Networks-on-Chip. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Keunyeol Park, Ohoon Kwon, Hyunseob Noh, Minhyun Jin, Minkyu Song |
Design of an Asynchronous Detector with Priority Encoding Technique. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Liu, Quentin L. Meunier, Alain Greiner |
Decoupling Translation Lookaside Buffer Coherence from Cache Coherence. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh |
Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Fawaz, Farid N. Najm |
Parallel Simulation-Based Verification of RC Power Grids. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ziyad Almohaimeed, Mihai Sima |
Secured-by-Design FPGA against Early Evaluation. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xingyuan Tong, Kangkang Wei |
A Fully Integrated Fast-Response LDO Voltage Regulator with Adaptive Transient Current Distribution. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hela Belhadj Amor, Hamed Sheibanyrad, Frédéric Pétrot |
A Meta-Routing Method to Create Multiple Virtual Logical Networks on a Single Hardware NoC. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Brice Colombier, Lilian Bossuet, David Hély |
Centrality Indicators for Efficient and Scalable Logic Masking. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | |
2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017 |
ISVLSI |
2017 |
DBLP BibTeX RDF |
|
| 1 | Tung Thanh Le, Dan Zhao 0001, Magdy A. Bayoumi |
Efficient Reconfigurable Global Network-on-Chip Designs towards Heterogeneous CPU-GPU Systems: An Application-Aware Approach. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi |
Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai |
Minimizing Critical Access Time for 3D Data Bus Based on Inserted Bus Switches and Repeaters. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sri Harsha Gade, Sakshi Garg 0002, Sujay Deb |
OFDM Based High Data Rate, Fading Resilient Transceiver for Wireless Networks-on-Chip. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaige Jia, Zheyu Liu, Fei Qiao, Xinjun Liu, Qi Wei 0001, Huazhong Yang |
AICNN: Implementing Typical CNN Algorithms with Analog-to-Information Conversion Architecture. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Oana Boncalo, Alexandru Amaricai |
Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Saru Vig, Tan Yng Tzer, Guiyuan Jiang, Siew-Kei Lam |
Customizing Skewed Trees for Fast Memory Integrity Verification in Embedded Systems. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Farhana Parveen, Zhezhi He, Shaahin Angizi, Deliang Fan |
Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tiankai Su, Cunxi Yu, Atif Yasin, Maciej J. Ciesielski |
Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Static Compaction by Merging of Seeds for LFSR-Based Test Generation. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Scott Lerner, Baris Taskin |
WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Xie 0005, Hoang Anh Du Nguyen, Jintao Yu, Ali Kaichouhi, Mottaqiallah Taouil, Mohammad AlFailakawi, Said Hamdioui |
Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomás Grimm, Djones Lettnin, Michael Hübner 0001 |
Semiformal Verification of Software-Controlled Connections. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Himanshu Thapliyal, T. S. S. Varun, S. Dinesh Kumar |
Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Yan, Yici Cai, Chenguang Wang 0003, Qiang Zhou 0001 |
An Effective Power Grid Optimization Approach for the Electromigration Reliability. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Garrett S. Rose, Md. Badruddoja Majumder, Mesbah Uddin |
Exploiting Memristive Crossbar Memories as Dual-Use Security Primitives in IoT Devices. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammed Al Kadi, Benedikt Janßen, Michael Hübner 0001 |
Floating-Point Arithmetic Using GPGPU on FPGAs. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangamesh Kodge, Himanshu Chaudhary, Mrigank Sharad |
Low Power Image Acquisition Scheme Using On-Pixel Event Driven Halftoning. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Subha Koley, Prasun Ghosal |
An IoT Enabled Real-Time Communication and Location Tracking System for Vehicular Emergency. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuo Li, Xiaolin Xu, Wayne P. Burleson |
CCATDC: A Configurable Compact Algorithmic Time-to-Digital Converter. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Greeshma R, Anoop V. K, B. Venkataramani |
A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS Technology. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tino Flenker, Jan Malburg, Görschwin Fey, Serhiy Avramenko, Massimo Violante, Matteo Sonza Reorda |
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mayukh Sarkar, Prasun Ghosal |
Performing Mathematics Using DNA: Complex Number Arithmetic Using Sticker Model. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Van Leussen, Jos Huisken, Lei Wang, Hailong Jiao, José Pineda de Gyvez |
Reconfigurable Support Vector Machine Classifier with Approximate Computing. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaahin Angizi, Zhezhi He, Farhana Parveen, Deliang Fan |
RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Melanie Brocard, Benoît Mathieu, Jean-Philippe Colonna, Cristiano Santos, Claire Fenouillet-Béranger, Cao-Minh Vincent Lu, Gerald Cibrario, Laurent Brunet, Perrine Batude, François Andrieu, Sébastien Thuries, Olivier Billoint |
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Edgard Muñoz-Coreas, Himanshu Thapliyal |
Design of Quantum Circuits for Galois Field Squaring and Exponentiation. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Shirshendu Das, Hemangee K. Kapoor |
Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhou Zhao, Xinlu Chen, Ashok Srivastava, Lu Peng 0001, Saraju P. Mohanty |
Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rakhi R., Abhijeet D. Taralkar, M. H. Vasantha, Kumar Y. B. Nithin |
A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Shang-Rong Fang, Cheng-Wei Tai, Rung-Bin Lin |
On Benchmarking Pin Access for Nanotechnology Standard Cells. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Raghava Katreepalli, Themistoklis Haniotakis |
High Speed Power Efficient Carry Select Adder Design. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra |
Analysis of Side-Channel Attack AES Hardware Trojan Benchmarks against Countermeasures. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Vasil Pano, Yuqiao Liu 0001, Isikcan Yilmaz, Ankit More, Baris Taskin, Kapil R. Dandekar |
Wireless NoCs Using Directional and Substrate Propagation Antennas. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Yu Huang, Ren-Yuan Huang, Ro-Min Weng |
A 0.3V Low Cost Low Power 24 GHz Low Noise Amplifier with Body Bias Technology. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Süleyman Savas, Erik Hertz, Tomas Nordström, Zain Ul-Abdin |
Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic Synthesis. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sparsh Mittal, Rajendra Bishnoi, Fabian Oboril, Haonan Wang, Mehdi Baradaran Tahoori, Adwait Jog, Jeffrey S. Vetter |
Architecting SOT-RAM Based GPU Register File. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamzeh Ahangari, Ihsen Alouani, Özcan Özturk 0001, Smaïl Niar |
Reconfigurable Hardened Latch and Flip-Flop for FPGAs. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin Kreißig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Guillaume Prenat |
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh |
Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security Based on DL-FET. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler |
BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunmin Kim, Seokhie Hong, Bart Preneel, Ingrid Verbauwhede |
STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tong Zhang, Daniel G. Saab, Jacob A. Abraham |
Automatic Assertion Generation for Simulation, Formal Verification and Emulation. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl |
Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas |
An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali H. Hassan, Esraa M. Hamed, Eman Badr, Omar Elsharqawy, Tawfik Ismail, S. R. I. Gabran, Yehea Ismail, Hassan Mostafa |
A VCO-Based MPPT Circuit for Low-Voltage Energy Harvesters. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zipeng Li, Kelvin Yi-Tse Lai, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee |
Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Shafique 0001, Rehan Hafiz, Muhammad Usama Javed, Sarmad Abbas, Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek |
Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco Rabozzi, Rolando Brondolin, Giuseppe Natale, Emanuele Del Sozzo, Michael Hübner 0001, Andreas Brokalakis, Catalin Bogdan Ciobanu, Dirk Stroobandt, Marco Domenico Santambrogio |
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Chen 0014, Emil Matús, Gerhard P. Fettweis |
Combined TDM and SDM Circuit Switching NoCs with Dedicated Connection Allocator. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarah Azimi, Luca Sterpone |
Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Lucas Machado, Antoni Roca Perez, Jordi Cortadella |
Voltage Noise Analysis with Ring Oscillator Clocks. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Lita Yang, Boris Murmann |
Approximate SRAM for Energy-Efficient, Privacy-Preserving Convolutional Neural Networks. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamed Hossein-Talaee, Ali Jahanian 0001 |
Layout Vulnerability Reduction against Trojan Insertion Using Security-Aware White Space Distribution. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuba Ayhan, Firat Kula, Mustafa Altun |
A Power Efficient System Design Methodology Employing Approximate Arithmetic Units. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Cremona, William Fornaciari, Andrea Marchese, Michele Zanella, Davide Zoni |
DENA: A DVFS-Capable Heterogeneous NoC Architecture. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Dan Cristian Turicu, Octavian Cret, Lucia Vacariu |
Serial ATA Commands Logger for Security Monitoring on FPGA Devices. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Haider Alrudainy, Andrey Mokhov, Fei Xia, Alex Yakovlev |
Ultra-Low Energy Data Driven Computing Using Asynchronous Micropipelines and Nano-Electro-Mechanical Relays. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Magnus Sundal, Ricardo Chaves |
Efficient FPGA Implementation of the SHA-3 Hash Function. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ankur Limaye, Tosiron Adegbija |
A Workload Characterization for the Internet of Medical Things (IoMT). |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruizhe Zhao, Wayne Luk, Xinyu Niu, Huifeng Shi, Haitao Wang |
Hardware Acceleration for Machine Learning. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohd. Tasleem Khan, Shaik Rafi Ahamed |
A New High Performance VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh |
Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable Function. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | George Lentaris, Ioannis Stratakos, Ioannis Stamoulias, Konstantinos Maragos 0001, Dimitrios Soudris, Manolis I. A. Lourakis, Xenophon Zabulis, David González Arjona |
Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Chenxi Dai, Tosiron Adegbija |
Exploiting Configurability as a Defense against Cache Side Channel Attacks. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yimai Peng, Haobo Zhao, Xun Sun, Chen Sun |
A Side-Channel Attack Resistant AES with 500Mbps, 1.92pJ/Bit PVT Variation Tolerant True Random Number Generator. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Salmen Mraihi, El Mehdi Boujamaa, Cyrille Dray, Jacques-Olivier Klein |
Offset Analysis and Design Optimization of a Dynamic Sense Amplifier for Resistive Memories. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Srivatsa Rangachar Srinivasa, Karthik Mohan, Wei-Hao Chen, Kuo-Hsinag Hsu, Xueqing Li, Meng-Fan Chang, Sumeet Kumar Gupta, John Sampson, Vijaykrishnan Narayanan |
Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rengarajan Ragavan, Cédric Killian, Olivier Sentieys |
Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | B. G. Sileshi, Joan Oliver, Carles Ferrer 0001 |
Accelerating Particle Filter on FPGA. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
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