Search results for "Integr."

Hits ?▲	Authors	Title	Venue	Year	Link
1	Trio Adiono, Khilda Afifah, Suksmandhira Harimurti, Prasetiyo, Amy Hamidah Salman	Fully integrated transceiver module with a temperature compensation for high bit rate contactless smart card.	Integr.	2019	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Kuan-Ting Yeh, Katherine Shu-Min Li	Exploiting distribution of unknown values in test responses to optimize test output compactors.	Integr.	2019	DBLP DOI BibTeX RDF
1	Stavroula Kapoulea, Costas Psychalinos, Ahmed S. Elwakil	Realizations of simple fractional-order capacitor emulators with electronically-tunable capacitance.	Integr.	2019	DBLP DOI BibTeX RDF
1	R. S. S. M. R. Krishna, Ashis Kumar Mal, Rajat Mahapatra	All MOS noise-shaped time-mode temperature sensor.	Integr.	2019	DBLP DOI BibTeX RDF
1	Shady M. Soliman, Mohammed A. Jaela, Abdelrhman M. Abotaleb, Youssef Hassan, Mohamed Abdelghany, Amr T. Abdel-Hamid, Khaled N. Salama, Hassan Mostafa	FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping.	Integr.	2019	DBLP DOI BibTeX RDF
1	George Floros 0002, Nestoras E. Evmorfopoulos, Georgios I. Stamoulis	Efficient IC hotspot thermal analysis via low-rank Model Order Reduction.	Integr.	2019	DBLP DOI BibTeX RDF
1	Jiming Xu, Howard M. Heys	Kernel-based template attacks of cryptographic circuits using static power.	Integr.	2019	DBLP DOI BibTeX RDF
1	Yuan Cheng, Chao Wang, Hai-Bao Chen, Hao Yu 0001	A large-scale in-memory computing for deep neural network with trained quantization.	Integr.	2019	DBLP DOI BibTeX RDF
1	Amitkumar S. Khade, Vibha S. Vyas, Mukul S. Sutaone	Performance enhancement of advanced recycling folded cascode operational transconductance amplifier using an unbalanced biased input stage.	Integr.	2019	DBLP DOI BibTeX RDF
1	Engin Afacan, Günhan Dündar	A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization.	Integr.	2019	DBLP DOI BibTeX RDF
1	Adrian Wheeldon, Jordan Morris, Danil Sokolov, Alex Yakovlev	Self-timed, minimum latency circuits for the internet of things.	Integr.	2019	DBLP DOI BibTeX RDF
1	Sri Harsha Gade, Shobha Sundar Ram, Sujay Deb	Millimeter wave wireless interconnects in deep submicron chips: Challenges and opportunities.	Integr.	2019	DBLP DOI BibTeX RDF
1	Rasoul Moradi, Ebrahim Farshidi, Mohammad Soroosh	A low power passive-active ΔΣ modulator with high-resolution employing an integrator with open-loop unity-gain buffer.	Integr.	2019	DBLP DOI BibTeX RDF
1	Heechun Park, Taewhan Kim	Hybrid asynchronous circuit generation amenable to conventional EDA flow.	Integr.	2019	DBLP DOI BibTeX RDF
1	Subhabrata Roy, Abhijit Chandra	Design of Narrow Transition Band Digital Filter: An Analytical Approach.	Integr.	2019	DBLP DOI BibTeX RDF
1	Xin-Yu Shih, Hong-Ru Chou	Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding.	Integr.	2019	DBLP DOI BibTeX RDF
1	Xiongfei Qu, Ruifeng Liu, Lingling Cao, Yuanzhi Zhang, Wenshen Wang, Huimin Liu, Chao Lu 0005	A 5.8 GHz digitally configurable DSRC RF-SoC transmitter for China ETC systems.	Integr.	2019	DBLP DOI BibTeX RDF
1	Enahoro Oriero, Syed Rafay Hasan	Survey on recent counterfeit IC detection techniques and future research directions.	Integr.	2019	DBLP DOI BibTeX RDF
1	Hongyu An, M. Amimul Ehsan, Zhen Zhou, Fangyang Shen, Yang Yi 0002	Monolithic 3D neuromorphic computing system with hybrid CMOS and memristor-based synapses and neurons.	Integr.	2019	DBLP DOI BibTeX RDF
1	Zechariah Balan, Harikrishnan Ramiah, Jagadheswaran Rajendran, Nandini Vitee, Pravinah Nair Shasidharan, Jun Yin 0001, Pui-In Mak, Rui Paulo Martins	A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA.	Integr.	2019	DBLP DOI BibTeX RDF
1	Michail Noltsis, Eleni Maragkoudaki, Dimitrios Rodopoulos, Francky Catthoor, Dimitrios Soudris	Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point.	Integr.	2019	DBLP DOI BibTeX RDF
1	Masoud Shiroei, Bijan Alizadeh, Masahiro Fujita	Data-path aware high-level ECO synthesis.	Integr.	2019	DBLP DOI BibTeX RDF
1	Asieh Parhizkar Tarighat, Mostafa Yargholi	Low power active shunt feedback CMOS low noise amplifier for wideband wireless systems.	Integr.	2019	DBLP DOI BibTeX RDF
1	Remigiusz Wisniewski, Grzegorz Bazydlo, Pawel Szczesniak	SVM algorithm oriented for implementation in a low-cost Xilinx FPGA.	Integr.	2019	DBLP DOI BibTeX RDF
1	Yaoyao Ye, Zhe Zhang	A thermal-sensitive design of a 3D torus-based optical NoC architecture.	Integr.	2019	DBLP DOI BibTeX RDF
1	Chaudhry Indra Kumar, Anand Bulusu	High performance energy efficient radiation hardened latch for low voltage applications.	Integr.	2019	DBLP DOI BibTeX RDF
1	Ismael Lomeli-Illescas, Sergio A. Solis-Bustos, José Ernesto Rayas-Sánchez	A tool for the automatic generation and analysis of regular analog layout modules.	Integr.	2019	DBLP DOI BibTeX RDF
1	Sabir Ali Mondal, Pradip Mandal, Hafizur Rahaman 0001	Fast locking, startup-circuit free, low area, 32-phase analog DLL.	Integr.	2019	DBLP DOI BibTeX RDF
1	Hesong Xu, Nicola Massari, Leonardo Gasparini, Alessio Meneghetti, Alessandro Tomasi 0001	A SPAD-based random number generator pixel based on the arrival time of photons.	Integr.	2019	DBLP DOI BibTeX RDF
1	Sebastian Tobuschat, Adam Kostrzewa, Rolf Ernst	Selective congestion control for mixed-critical networks-on-chip.	Integr.	2019	DBLP DOI BibTeX RDF
1	Ioannis S. Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano	Workload- and process-variation aware voltage/frequency tuning for energy efficient performance sustainability of NTC manycores.	Integr.	2019	DBLP DOI BibTeX RDF
1	Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta	Look-ahead mapping of Boolean functions in memristive crossbar array.	Integr.	2019	DBLP DOI BibTeX RDF
1	Saeideh Kabirpour, Mohsen Jalali	A highly linear current-starved VCO based on a linearized current control mechanism.	Integr.	2019	DBLP DOI BibTeX RDF
1	Jiaji He, Xiaolong Guo, Travis Meade, Raj Gautam Dutta, Yiqiang Zhao, Yier Jin	SoC interconnection protection through formal verification.	Integr.	2019	DBLP DOI BibTeX RDF
1	Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir	Novel techniques for memristive multifunction logic design.	Integr.	2019	DBLP DOI BibTeX RDF
1	Moritz Weißbrich, Lukas Gerlach 0001, Holger Blume, Ardalan Najafi, Alberto García Ortiz, Guillermo Payá Vayá	FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework.	Integr.	2019	DBLP DOI BibTeX RDF
1	Sana Arshad, Rashad Ramzan, Qamar-ul-Wahab	50-830 MHz noise and distortion canceling CMOS low noise amplifier.	Integr.	2018	DBLP DOI BibTeX RDF
1	Nadia Nedjah, Heloisa Dina Bezerra, Luiza de Macedo Mourelle	Automatic generation of harmonious music using cellular automata based hardware design.	Integr.	2018	DBLP DOI BibTeX RDF
1	Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández 0001	Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator.	Integr.	2018	DBLP DOI BibTeX RDF
1	Amir Ardakani, Shahriar B. Shokouhi, Arash Reyhani-Masoleh	Improving performance of FPGA-based SR-latch PUF using Transient Effect Ring Oscillator and programmable delay lines.	Integr.	2018	DBLP DOI BibTeX RDF
1	Rupam Bhattacharya, Pranab Roy, Hafizur Rahaman 0001	Homogeneous droplet routing in DMFB: An enhanced technique for high performance bioassay implementation.	Integr.	2018	DBLP DOI BibTeX RDF
1	Giulia Di Capua, Nuno Horta, Francisco V. Fernández 0001, Günhan Dündar, Salvatore Pennisi, Gaetano Palumbo, Massimo Alioto, Gianluca Giustolisi	Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017.	Integr.	2018	DBLP DOI BibTeX RDF
1	Muharrem Orkun Saglamdemir, Günhan Dündar, Alper Sen 0001	Analog behavioral equivalence boundary computation under the effect of process variations.	Integr.	2018	DBLP DOI BibTeX RDF
1	Sefa Özbek, Golzar Alavi, Johannes Digel, Markus Grözing, Joachim N. Burghartz, Manfred Berroth	3-Path SiGe BiCMOS power amplifier on thinned substrate for IoT applications.	Integr.	2018	DBLP DOI BibTeX RDF
1	Kan Xu, Ravi Patel 0001, Praveen Raghavan, Eby G. Friedman	Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs.	Integr.	2018	DBLP DOI BibTeX RDF
1	Arianna Coccia, Saheed Tijani, Danilo Manstretta, Rinaldo Castello	A TVWS receiver with balanced output self-calibrated IIP2 LNTA employing a low-noise current multiplier.	Integr.	2018	DBLP DOI BibTeX RDF
1	Saverio Panarello, Claudia Triolo, F. Garesci, Salvatore Patanè, R. Denaro	Improving ICs reliability with high speed thermal mapping.	Integr.	2018	DBLP DOI BibTeX RDF
1	Anushree Mahapatra, Yidi Liu, Benjamin Carrión Schäfer	Accelerating cycle-accurate system-level simulations through behavioral templates.	Integr.	2018	DBLP DOI BibTeX RDF
1	Xin-Yu Shih, Po-Chun Huang, Hong-Ru Chou	VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system.	Integr.	2018	DBLP DOI BibTeX RDF
1	Adam Opara, Marcin Kubica, Dariusz Kania	Strategy of logic synthesis using MTBDD dedicated to FPGA.	Integr.	2018	DBLP DOI BibTeX RDF
1	Dominik Macko, Katarína Jelemenská, Pavel Cicák	Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation.	Integr.	2018	DBLP DOI BibTeX RDF
1	Ioannis A. Papistas, Vasilis F. Pavlidis	Contactless Heterogeneous 3-D ICs for Smart Sensing Systems.	Integr.	2018	DBLP DOI BibTeX RDF
1	Mohammad Asyaei	A new low-power dynamic circuit for wide fan-in gates.	Integr.	2018	DBLP DOI BibTeX RDF
1	Habib Rastegar, Saeid Zare, Jee-Youl Ryu	A low-voltage low-power capacitive-feedback voltage controlled oscillator.	Integr.	2018	DBLP DOI BibTeX RDF
1	Jun-Da Chen, Wen-Jun Wang	A 1.5 ∼ 5 GHz CMOS broadband low-power high-efficiency power amplifier for wireless communications.	Integr.	2018	DBLP DOI BibTeX RDF
1	Ali Ibrahim, Luigi Pinna, Maurizio Valle	Experimental characterization of dedicated front-end electronics for piezoelectric tactile sensing arrays.	Integr.	2018	DBLP DOI BibTeX RDF
1	Stefan Kristofík, Peter Malík	Enhancement of fault collection for embedded RAM redundancy analysis considering intersection and orphan faults.	Integr.	2018	DBLP DOI BibTeX RDF
1	Niccolo Lacaita, Matteo Bassi, Andrea Mazzanti, Francesco Svelto	A K-band low-noise bipolar class-C VCO for 5G backhaul systems in 55 nm BiCMOS technology.	Integr.	2018	DBLP DOI BibTeX RDF
1	Zeinab Hijazi, Marco Grassi, Daniele D. Caviglia, Maurizio Valle	Time-based calibration-less read-out circuit for interfacing wide range MOX gas sensors.	Integr.	2018	DBLP DOI BibTeX RDF
1	Shahzad Asif, Md. Selim Hossain, Yinan Kong, Wadood Abdul	A Fully RNS based ECC Processor.	Integr.	2018	DBLP DOI BibTeX RDF
1	Mohsen Hayati, Sajad Cheraghaliei, Sepehr Zarghami	Design of UWB low noise amplifier using noise-canceling and current-reused techniques.	Integr.	2018	DBLP DOI BibTeX RDF
1	Yufei Ma 0002, Naveen Suda, Yu Cao 0001, Sarma B. K. Vrudhula, Jae-sun Seo	ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.	Integr.	2018	DBLP DOI BibTeX RDF
1	Nunzio Greco, Alessandro Parisi, Nunzio Spina, Egidio Ragonese, Giuseppe Palmisano	Scalable lumped models of integrated transformers for galvanically isolated power transfer systems.	Integr.	2018	DBLP DOI BibTeX RDF
1	Lennart Bamberg, Amir Najafi 0001, Alberto García Ortiz	Edge effects on the TSV array capacitances and their performance influence.	Integr.	2018	DBLP DOI BibTeX RDF
1	Tze Sin Tan, Bakhtiar Affendi Rosdi	Hardware-assisted Verilog simulation system using an application specific microprocessor.	Integr.	2018	DBLP DOI BibTeX RDF
1	Qiang Han, Qiang Xu 0001, Wen-Ben Jone	SERA: statistical error rate analysis for profit-oriented performance binning of resilient circuits.	Integr.	2018	DBLP DOI BibTeX RDF
1	J. Ahmadi-Farsani, Hamed Sadjedi, M. B. Ghaznavi-Ghoushchi	An ultra low-power current-mode clock and data recovery design with input bit-rate adaptability for biomedical applications in CMOS 90 nm.	Integr.	2018	DBLP DOI BibTeX RDF
1	Armin Mohammadjany, Ali Reza Hazeri, Hossein Miar Naimi	Exact analyses for locking range in injection-locked frequency dividers.	Integr.	2018	DBLP DOI BibTeX RDF
1	Yun Fang, Xiaopeng Yu, Zheng Shi 0002, Kiat Seng Yeo	A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS.	Integr.	2018	DBLP DOI BibTeX RDF
1	Xiaolong Lv, Xiao Zhao, Yongqing Wang, Dawei Jia	Super class AB-AB bulk-driven folded cascode OTA.	Integr.	2018	DBLP DOI BibTeX RDF
1	Manas Kumar Hati, Tarun Kanti Bhattacharyya	Phase noise analysis of proposed PFD and CP switching circuit and its advantages over various PFD/CP switching circuits in phase-locked loops.	Integr.	2018	DBLP DOI BibTeX RDF
1	Mahdi Shabany, Dimpesh Patel, Mario Milicevic, Mojtaba Mahdavi 0001, P. Glenn Gulak	A 70 pJ/b configurable 64-QAM soft MIMO detector.	Integr.	2018	DBLP DOI BibTeX RDF
1	Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai	Asymmetry dual-LFSR reseeding for low power BIST.	Integr.	2018	DBLP DOI BibTeX RDF
1	Georg Gläser, Martin Grabmann, Gerrit Kropp, Andreas Furtig	There is a limit to everything: Automating AMS operating condition check generation on system-level.	Integr.	2018	DBLP DOI BibTeX RDF
1	Nagapuri Srinivas, Gayadhar Pradhan, Puli Kishore Kumar	An efficient hardware architecture for detection of vowel-like regions in speech signal.	Integr.	2018	DBLP DOI BibTeX RDF
1	Guoyong Shi	Toward automated reasoning for analog IC design by symbolic computation - A survey.	Integr.	2018	DBLP DOI BibTeX RDF
1	Siavash Mowlavi, Aram Baharmast, Jafar Sobhi, Ziaddin Daei Koozehkanani	A novel current-mode low-power adjustable wide input range four-quadrant analog multiplier.	Integr.	2018	DBLP DOI BibTeX RDF
1	Faiq Khalid, Syed Rafay Hasan, Osman Hasan, Falah R. Awwad	Runtime hardware Trojan monitors through modeling burst mode communication using formal verification.	Integr.	2018	DBLP DOI BibTeX RDF
1	Desheng Zheng, Xiaoyu Li, Guowu Yang, Hai Wang, Lulu Tian	An assertion graph based abstraction algorithm in GSTE and Its application.	Integr.	2018	DBLP DOI BibTeX RDF
1	Murat Pak, Francisco V. Fernández 0001, Günhan Dündar	A novel design methodology for the mixed-domain optimization of a MEMS accelerometer.	Integr.	2018	DBLP DOI BibTeX RDF
1	Fabrizio Riente, Andrea Giordano, Marco Vacca, Mariagrazia Graziano	Exploring N3ASIC technology for microwave imaging architectures.	Integr.	2018	DBLP DOI BibTeX RDF
1	Yiming Ouyang, Jianfeng Yang, Kun Xing, Zhengfeng Huang, Huaguo Liang	An improved communication scheme for non-HOL-blocking wireless NoC.	Integr.	2018	DBLP DOI BibTeX RDF
1	Minho Nam, Kyoung-Rok Cho	Implementation of real-time image edge detector based on a bump circuit and active pixels in a CMOS image sensor.	Integr.	2018	DBLP DOI BibTeX RDF
1	Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale	Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication.	Integr.	2018	DBLP DOI BibTeX RDF
1	Urvashi Bansal, Maneesha Gupta	High bandwidth transimpedance amplifier using FGMOS for low voltage operation.	Integr.	2018	DBLP DOI BibTeX RDF
1	Nan Wang 0003, Wei Zhong, Song Chen 0001, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu	Power-gating-aware scheduling with effective hardware resources optimization.	Integr.	2018	DBLP DOI BibTeX RDF
1	Sangmin Kim, Youngsoo Shin	Module grouping to reduce the area of test wrappers in SoCs.	Integr.	2018	DBLP DOI BibTeX RDF
1	Jonathan Calvillo, Ricardo Póvoa, Jorge Guilherme, Nuno Horta	Second-order compensation BGR with low TC and high performance for space applications.	Integr.	2018	DBLP DOI BibTeX RDF
1	Mohamed Abbas, Ashraf Ramadan	Low-cost methodology for fault diagnosis and localization in pipelined ADCs.	Integr.	2018	DBLP DOI BibTeX RDF
1	Ali Abou Khalil, Maurizio Valle, Hussein Chible, Chiara Bartolozzi	CMOS event-driven tactile sensor circuit.	Integr.	2018	DBLP DOI BibTeX RDF
1	Taeyoung Kim 0001, Sheldon X.-D. Tan, Chase Cook, Zeyu Sun 0001	Detection of counterfeited ICs via on-chip sensor and post-fabrication authentication policy.	Integr.	2018	DBLP DOI BibTeX RDF
1	Mehmet Tükel, Arda Yurdakul, Berna Örs	Customizable embedded processor array for multimedia applications.	Integr.	2018	DBLP DOI BibTeX RDF
1	Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma	Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design.	Integr.	2018	DBLP DOI BibTeX RDF
1	Mohammad Radpour, Sayed Masoud Sayedi	SystemC-AMS modeling of photodiode based on PWL technique to be used in energy harvesting CMOS image sensor.	Integr.	2018	DBLP DOI BibTeX RDF
1	Ankur Kumar, Rajendra Kumar Nagaria	A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits.	Integr.	2018	DBLP DOI BibTeX RDF
1	Vlastimil Kote, Adam Kubacak, Patrik Vacula, Jiri Jakovenko, Miroslav Husák	Automated pre-placement phase as a part of robust analog-mixed signal physical design flow.	Integr.	2018	DBLP DOI BibTeX RDF
1	Yanbin Li, Ming Tang 0002, Yuguang Li, Huanguo Zhang	Several weaknesses of the implementation for the theoretically secure masking schemes under ISW framework.	Integr.	2018	DBLP DOI BibTeX RDF
1	Xingquan Li, Jianli Chen, Wenxing Zhu	Discrete relaxation method for contact layer decomposition of DSA with triple patterning.	Integr.	2018	DBLP DOI BibTeX RDF
1	Yiran Chen 0001, Hai (Helen) Li, Chunpeng Wu, Chang Song 0001, Sicheng Li, Chuhan Min, Hsin-Pai Cheng, Wei Wen, Xiaoxiao Liu 0001	Neuromorphic computing's yesterday, today, and tomorrow - an evolutional view.	Integr.	2018	DBLP DOI BibTeX RDF
1	Axel Hald, Pekka Herzogenrath, Jürgen Scheible, Jens Lienig, Johannes Seelhorst, Peter Brandl	Full custom MEMS design: A new method for the analysis of motion-dependent parasitics.	Integr.	2018	DBLP DOI BibTeX RDF

Publications at "Integr."( http://dblp.L3S.de/Venues/Integr. )