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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 62 occurrences of 45 keywords
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Results
Found 708 publication records. Showing 707 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Turbo Majumder, Manan Suri, Vinay Shekhar |
NoC router using STT-MRAM based hybrid buffers with error correction and limited flit retransmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 2305-2308, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Zheng Li, Bonan Yan, Lun Yang, Weisheng Zhao, Yiran Chen 0001, Hai Li 0001 |
A new self-reference sensing scheme for TLC MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 593-596, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Kai Yang, Yanqing Zhao, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jun-Soo Bae |
Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8483-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Alessandro Grossi, Cristian Zambelli, Piero Olivo, Paolo Pellati, Michele Ramponi, Jérémy Alvarez-Herault, Ken Mackay |
Automated characterization of TAS-MRAM test arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015, Napoli, Italy, April 21-23, 2015, pp. 1-2, 2015, IEEE, 978-1-4799-1999-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Paolo Prinetto, Joan Figueras |
STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015, Napoli, Italy, April 21-23, 2015, pp. 1-6, 2015, IEEE, 978-1-4799-1999-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Rujia Wang, Lei Jiang 0001, Youtao Zhang, Linzhang Wang, Jun Yang 0002 |
Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, pp. 21:1-21:6, 2015, ACM, 978-1-4503-3520-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Richard Dorrance |
An Energy-Efficient Sparse-BLAS Coprocessor using STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2015 |
RDF |
|
16 | Kejie Huang, Ning Ning 0001, Yong Lian 0001 |
Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(5), pp. 1179-1182, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Kon-Woo Kwon, Sri Harsha Choday, Yusung Kim 0002, Kaushik Roy 0001 |
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(4), pp. 712-720, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Xuanyao Fong, Yusung Kim 0002, Sri Harsha Choday, Kaushik Roy 0001 |
Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(2), pp. 384-395, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung |
STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(7), pp. 1630-1634, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi 0001, Koji Tsunoda, Toshihiro Sugii |
STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12), pp. 2411-2417, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Yong Song, Kyu Ho Park |
UStore: STT-MRAM Based Light-Weight User-Level Storage for Enhancing Performance of Accessing Persistent Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 97-D(3), pp. 497-509, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Jue Wang, Xiangyu Dong, Yuan Xie 0001 |
Building and Optimizing MRAM-Based Commodity Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 11(4), pp. 36:1-36:22, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Ravi Patel 0001, Engin Ipek, Eby G. Friedman |
2T-1R STT-MRAM memory cells for enhanced on/off current ratio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 45(2), pp. 133-143, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Kejie Huang, Rong Zhao, Ning Ning 0001, Yong Lian 0001 |
A Low Power Localized 2T1R STT-MRAM Array With Pipelined Quad-Phase Saving Scheme for Zero Sleep Power Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9), pp. 2614-2623, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Jisu Kim, Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung |
A Split-Path Sensing Circuit for Spin Torque Transfer MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 61-II(3), pp. 193-197, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | S. Arcaro, Stefano Di Carlo, Marco Indaco, D. Pala, Paolo Prinetto, Elena I. Vatajelu |
Integration of STT-MRAM model into CACTI simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDT ![In: 9th International Design and Test Symposium, IDT 2014, Algeries, Algeria, December 16-18, 2014, pp. 67-72, 2014, IEEE, 978-1-4799-8200-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar |
Improving STT-MRAM density through multibit error correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, pp. 1-6, 2014, European Design and Automation Association, 978-3-9815370-2-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori |
Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, pp. 1-6, 2014, European Design and Automation Association, 978-3-9815370-2-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Wang Kang 0001, Weisheng Zhao, Lun Yang, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona |
One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NVMSA ![In: IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2014, Chongqing, China, August 20-21, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Kejie Huang, Rong Zhao, Yong Lian 0001 |
STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014, Paris, France, July 8-10, 2014, pp. 31-36, 2014, IEEE Computer Society/ACM, 978-1-4799-6383-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Jue Wang, Xiangyu Dong, Yuan Xie 0001 |
Enabling high-performance LPDDRx-compatible MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014, pp. 339-344, 2014, ACM, 978-1-4503-2975-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita |
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSIC ![In: Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014, pp. 1-2, 2014, IEEE, 978-1-4799-3327-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Le Zhang 0001, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy 0001 |
Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 2169-2172, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Ravi Patel 0001, Engin Ipek, Eby G. Friedman |
Field driven STT-MRAM cell for reduced switching latency and energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 2173-2176, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Matthias Hartmann, Halil Kükner, Prashant Agrawal, Praveen Raghavan, Liesbet Van der Perre, Wim Dehaene |
Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014, pp. 243-244, 2014, ACM, 978-1-4503-2816-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori |
Avoiding unnecessary write operations in STT-MRAM for low power implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014, pp. 548-553, 2014, IEEE, 978-1-4799-3945-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Ping Chi, Cong Xu, Xiaochun Zhu, Yuan Xie 0001 |
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014, pp. 639-644, 2014, IEEE, 978-1-4799-3945-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Raphael Robertazzi, Janusz Nowak, Jonathan Sun |
Analytical MRAM test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2014 International Test Conference, ITC 2014, Seattle, WA, USA, October 20-23, 2014, pp. 1-10, 2014, IEEE Computer Society, 978-1-4799-4722-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori |
Read disturb fault detection in STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2014 International Test Conference, ITC 2014, Seattle, WA, USA, October 20-23, 2014, pp. 1-7, 2014, IEEE Computer Society, 978-1-4799-4722-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe |
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIC ![In: 2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014, pp. 316-319, 2014, IEEE, 978-1-4799-4833-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Jayita Das |
Auxiliary Roles in STT-MRAM Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2014 |
RDF |
|
16 | Kwangil Choi, Hyunok Oh |
An energy aware buffer mapping technique on hybrid STT-MRAM memories with multiple retention time for stream applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 17(3-4), pp. 693-710, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Kui Cai 0001, Zhiliang Qin, Bingjin Chen |
Channel Capacity and Soft-Decision Decoding of LDPC Codes for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Commun. ![In: J. Commun. 8(4), pp. 225-232, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Ching-Yi Chen, Sheng-Hung Wang, Cheng-Wen Wu |
Write Current Self-Configuration Scheme for MRAM Yield Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(7), pp. 1260-1270, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Dmytro Apalkov, Alexey Khvalkovskiy, Steven Watts, Vladimir Nikitin, Xueti Tang, Daniel Lottis, Kiseok Moon, Xiao Luo, Eugene Chen, Adrian Ong, Alexander Driskill-Smith, Mohamad Krounbi |
Spin-transfer torque magnetic random access memory (STT-MRAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 9(2), pp. 13:1-13:35, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Wang Kang 0001, Weisheng Zhao, Zhaohao Wang, Yue Zhang 0010, Jacques-Olivier Klein, Youguang Zhang, Claude Chappert, Dafine Ravelosona |
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 53(9-11), pp. 1224-1229, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Safeen Huda, Ali Sheikholeslami |
A Novel STT-MRAM Cell With Disturbance-Free Read Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6), pp. 1534-1547, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Li Zhang, Weisheng Zhao, Yiqi Zhuang, Junlin Bao, Hualian Tang, Cong Li, Xin Xiang |
Design and analysis of the reference cells for STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 10(12), pp. 20130352, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Kui Cai 0001, Zhiliang Qin, Bingjin Chen |
Channel capacity and soft-decision decoding of LDPC codes for spin-torque transfer magnetic random access memory (STT-MRAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNC ![In: International Conference on Computing, Networking and Communications, ICNC 2013, San Diego, CA, USA, January 28-31, 2013, pp. 550-554, 2013, IEEE Computer Society, 978-1-4673-5287-1. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Lionel Torres, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli, Luis Vitório Cargnini |
Evaluation of hybrid MRAM/CMOS cells for reconfigurable computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013, Paris, France, June 16-19, 2013, pp. 1-6, 2013, IEEE, 978-1-4799-0618-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Hiwa Mahmoudi, Thomas Windbacher, Viktor Sverdlov, Siegfried Selberherr |
MRAM-based logic array for large-scale non-volatile logic-in-memory applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013, Brooklyn, NY, USA, July 15-17, 2013, pp. 26-27, 2013, IEEE Computer Society, 978-1-4799-0873-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Thomas W. Andre, Syed M. Alam, Dietmar Gogl, C. K. Subramanian, Hal Lin, W. Meadows, X. Zhang, Nicholas D. Rizzo, Jason Janesky, D. Houssameddine, Jon M. Slaughter |
ST-MRAM fundamentals, challenges, and applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013, San Jose, CA, USA, September 22-25, 2013, pp. 1-8, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Mihail Jefremow, Thomas Kern, Wolf Allers, Christian Peters, Jan Otterstedt, Othmane Bahlous, Karl Hofmann, Robert Allinger, Stephan Kassenetter, Doris Schmitt-Landsiedel |
Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013, pp. 216-217, 2013, IEEE, 978-1-4673-4515-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Yu-Der Chih, Tong-Chern Ong, Tsung-Yung Jonathan Chang, Sreedhar Natarajan, Luan C. Tran |
Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013, pp. 224-225, 2013, IEEE, 978-1-4673-4515-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Qing Guo 0004, Xiaochen Guo, Ravi Patel 0001, Engin Ipek, Eby G. Friedman |
AC-DIMM: associative computing with STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013, pp. 189-200, 2013, ACM, 978-1-4503-2079-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Yong Li 0009, Yaojun Zhang, Yiran Chen 0001, Alex K. Jones |
Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 4(4), pp. 82-85, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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16 | Weisheng Zhao, Yue Zhang 0010, Thibaut Devolder, Jacques-Olivier Klein, Dafine Ravelosona, Claude Chappert, Pascale Mazoyer |
Failure and reliability analysis of STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 52(9-10), pp. 1848-1852, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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16 | Wenqing Wu, Xiaochun Zhu, Seung H. Kang, Kendrick Yuen, Rob Gilmore |
Probabilistically Programmed STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 2(1), pp. 42-51, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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16 | Yongsik Park, Gyu-Hyun Kil, Yunheub Song |
A novel sensing algorithm for Spin-Transfer-Torque magnetic RAM (STT-MRAM) by utilizing dynamic reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 9(3), pp. 153-159, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Hyunjun Jang, Baik Song An, Nikhil Kulkarni, Ki Hwan Yum, Eun Jung Kim 0001 |
A Hybrid Buffer Design with STT-MRAM for On-Chip Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Copenhagen, Denmark, 9-11 May, 2012, pp. 193-200, 2012, IEEE Computer Society, 978-0-7695-4677-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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16 | Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay |
Impact of resistive-open defects on the heat current of TAS-MRAM architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, pp. 532-537, 2012, IEEE, 978-1-4577-2145-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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16 | Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay |
Coupling-based resistive-open defects in TAS-MRAM architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, pp. 1, 2012, IEEE Computer Society, 978-1-4673-0697-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay |
Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, pp. 125-130, 2012, IEEE Computer Society, 978-1-4673-4555-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yusung Kim 0002, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy 0001 |
Write-optimized reliable design of STT MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012, pp. 3-8, 2012, ACM, 978-1-4503-1249-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Dongsoo Lee, Sumeet Kumar Gupta, Kaushik Roy 0001 |
High-performance low-energy STT MRAM based on balanced write scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012, pp. 9-14, 2012, ACM, 978-1-4503-1249-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Yahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert |
MRAM crossbar based configurable logic block. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 2945-2948, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Ravi Patel 0001, Engin Ipek, Eby G. Friedman |
STT-MRAM memory cells with enhanced on/off ratio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: IEEE 25th International SOC Conference, SOCC 2012, Niagara Falls, NY, USA, September 12-14, 2012, pp. 148-152, 2012, IEEE, 978-1-4673-1294-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Byung-Min Lee, Gi-Ho Park |
Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012, pp. 247-250, 2012, IEEE, 978-1-4673-2989-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Lei Jiang 0001, Bo Zhao 0007, Youtao Zhang, Jun Yang 0002 |
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, pp. 907-912, 2012, ACM, 978-1-4503-1199-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Jee-Hwan Song, Jisu Kim, Seung-Hyuk Kang, Sei-Seung Yoon, Seong-Ook Jung |
Sensing margin trend with technology scaling in MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 39(3), pp. 313-325, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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16 | Weisheng Zhao, Thibaut Devolder, Yahya Lakys, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer |
Design considerations and strategies for high-reliable STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 51(9-11), pp. 1454-1458, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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16 | Karthik Swaminathan, Ravindhiran Mukundrajan, Niranjan Soundararajan, Vijaykrishnan Narayanan |
Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India, pp. 236-241, 2011, IEEE Computer Society, 978-0-7695-4447-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Weisheng Zhao, Yue Zhang 0010, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli |
Embedded MRAM for high-speed computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011, pp. 37-42, 2011, IEEE, 978-1-4577-0171-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Yiming Huai, Yuchen Zhou, Ioan Tudosa, Roger Malmhall, Rajiv Ranjan, Jing Zhang |
Progress and outlook for STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, California, USA, November 7-10, 2011, pp. 235, 2011, IEEE Computer Society, 978-1-4577-1399-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Weisheng Zhao, Lionel Torres, Yoann Guillemenet, Luis Vitório Cargnini, Yahya Lakys, Jacques-Olivier Klein, Dafine Ravelosona, Gilles Sassatelli, Claude Chappert |
Design of MRAM based logic circuits and its applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011, pp. 431-436, 2011, ACM, 978-1-4503-0667-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Lionel Torres, Weisheng Zhao |
Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011, pp. 429-430, 2011, ACM, 978-1-4503-0667-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Hongbin Sun 0001, Chuanyin Liu, Nanning Zheng 0001, Tai Min, Tong Zhang 0002 |
Design techniques to improve the device write margin for MRAM-based cache memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011, pp. 97-102, 2011, ACM, 978-1-4503-0667-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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16 | Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao |
Diagnosis of MRAM Write Disturbance Fault. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(12), pp. 1762-1766, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Jing Li 0073, Patrick Ndai, Ashish Goel, Sayeef S. Salahuddin, Kaushik Roy 0001 |
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(12), pp. 1710-1723, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Jisu Kim, Jee-Hwan Song, Seung-Hyuk Kang, Sei-Seung Yoon, Seong-Ook Jung |
Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 93-C(6), pp. 912-921, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Saied Tehrani |
Status and prospect for MRAM technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Chips Symposium ![In: 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, pp. 1-23, 2010, IEEE, 978-1-4673-8875-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Lionel Torres, Yoann Guillemenet, Syed Zahid Ahmed |
A Dynamic Reconfigurable MRAM based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ERSA ![In: Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA, pp. 31-40, 2010, CSREA Press, 1-60132-140-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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16 | Luis Vitório Cargnini, Yoann Guillemenet, Lionel Torres, Gilles Sassatelli |
Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings, pp. 150-155, 2010, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer |
High Density Asynchronous LUT Based on Non-volatile MRAM Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy, pp. 374-379, 2010, IEEE Computer Society, 978-0-7695-4179-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | David Halupka, Safeen Huda, William Song, Ali Sheikholeslami, Koji Tsunoda, Chikako Yoshida, Masaki Aoki |
Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010, pp. 256-257, 2010, IEEE, 978-1-4244-6033-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe |
A 64Mb MRAM with clamped-reference and adequate-reference schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010, pp. 258-259, 2010, IEEE, 978-1-4244-6033-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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16 | Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai |
Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 92-C(4), pp. 417-422, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer |
Spin transfer torque (STT)-MRAM-based runtime reconfiguration FPGA circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 9(2), pp. 14:1-14:16, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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16 | Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami, Hiromitsu Hada, Tadahiko Sugibayashi, Naoki Kasai |
A 90nm 12ns 32Mb 2T1MTJ MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009, pp. 462-463, 2009, IEEE, 978-1-4244-3458-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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16 | Joseph J. Nahas, Thomas W. Andre, Brad Garni, Chitra K. Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino |
A 180 Kbit Embeddable MRAM Memory Module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 43(8), pp. 1826-1834, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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16 | Wan-Yu Lo, Ching-Yi Chen, Chin-Lung Su, Cheng-Wen Wu |
Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, pp. 417-422, 2008, IEEE Computer Society, 978-0-7695-3396-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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16 | Jing Li 0073, Haixin Liu, Sayeef S. Salahuddin, Kaushik Roy 0001 |
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008, pp. 193-196, 2008, IEEE, 978-1-4244-2018-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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16 | Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara |
A 16-Mb Toggle MRAM With Burst Modes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 42(11), pp. 2378-2385, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara |
MRAM Cell Technology for Over 500-MHz SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 42(4), pp. 830-838, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai |
MRAM Applications Using Unlimited Write Endurance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 90-C(10), pp. 1936-1940, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara |
Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 90-C(2), pp. 531-535, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Joseph J. Nahas, Thomas W. Andre, Chitra K. Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino |
A 180 Kbit Embeddable MRAM Memory Module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007, pp. 791-794, 2007, IEEE, 978-1-4244-1623-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Weisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert |
TAS-MRAM based Non-volatile FPGA logic circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007, pp. 153-160, 2007, IEEE, 1-4244-1472-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao |
Diagnosis for MRAM write disturbance fault. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007, pp. 1-9, 2007, IEEE Computer Society, 1-4244-1128-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Matthew B. Leslie, R. Jacob Baker |
Noise-shaping sense amplifier for MRAM cross-point arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 41(3), pp. 699-704, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Thomas M. Maffitt, John K. DeBrosse, John A. Gabric, Earl T. Gow, Mark C. Lamorey, John S. Parenteau, Dennis R. Willmott, Mark A. Wood, William J. Gallagher |
Design considerations for MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 50(1), pp. 25-40, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Michael C. Gaidis, Eugene J. O'Sullivan, Janusz Jozef Nowak, Yu Lu, Sivananda K. Kanakasabapathy, Philip Louis Trouilloud, Daniel Christopher Worledge, Solomon Assefa, Keith R. Milkove, George P. Wright, William J. Gallagher |
Two-level BEOL processing for rapid iteration in MRAM development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 50(1), pp. 41-54, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | David William Abraham, Philip Louis Trouilloud, Daniel Christopher Worledge |
Rapid-turnaround characterization methods for MRAM development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 50(1), pp. 55-68, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Daniel Christopher Worledge |
Single-domain model for toggle MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 50(1), pp. 69-80, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Heinz Hoenigschmid, P. Beer, Alexander Bette, R. Dittrich, R. Gardic, Dietmar Gogl, Stefan Lammers, J. Schmid, Laith Altimime, Serge Bournat, Gerhard Müller |
Signal-Margin-Screening for Multi-Mb MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006, pp. 467-476, 2006, IEEE, 1-4244-0079-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda |
A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006, pp. 477-486, 2006, IEEE, 1-4244-0079-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ming-Jer Kao |
Testing MRAM for Write Disturbance Fault. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006, pp. 1-9, 2006, IEEE Computer Society, 1-4244-0292-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Thomas W. Andre, Joseph J. Nahas, Chitra K. Subramanian, Bradley J. Garni, Halbert S. Lin, Asim Omair, William L. Martino |
A 4-Mb 0.18-μm 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(1), pp. 301-309, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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