Search results for "MRAM"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Turbo Majumder, Manan Suri, Vinay Shekhar	NoC router using STT-MRAM based hybrid buffers with error correction and limited flit retransmission.	ISCAS	2015	DBLP DOI BibTeX RDF
16	Zheng Li, Bonan Yan, Lun Yang, Weisheng Zhao, Yiran Chen 0001, Hai Li 0001	A new self-reference sensing scheme for TLC MRAM.	ISCAS	2015	DBLP DOI BibTeX RDF
16	Kai Yang, Yanqing Zhao, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jun-Soo Bae	Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform.	ASICON	2015	DBLP DOI BibTeX RDF
16	Alessandro Grossi, Cristian Zambelli, Piero Olivo, Paolo Pellati, Michele Ramponi, Jérémy Alvarez-Herault, Ken Mackay	Automated characterization of TAS-MRAM test arrays.	DTIS	2015	DBLP DOI BibTeX RDF
16	Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Paolo Prinetto, Joan Figueras	STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations.	DTIS	2015	DBLP DOI BibTeX RDF
16	Rujia Wang, Lei Jiang 0001, Youtao Zhang, Linzhang Wang, Jun Yang 0002	Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM.	DAC	2015	DBLP DOI BibTeX RDF
16	Richard Dorrance	An Energy-Efficient Sparse-BLAS Coprocessor using STT-MRAM.		2015	RDF
16	Kejie Huang, Ning Ning 0001, Yong Lian 0001	Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
16	Kon-Woo Kwon, Sri Harsha Choday, Yusung Kim 0002, Kaushik Roy 0001	AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
16	Xuanyao Fong, Yusung Kim 0002, Sri Harsha Choday, Kaushik Roy 0001	Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
16	Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung	STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
16	Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi 0001, Koji Tsunoda, Toshihiro Sugii	STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2014	DBLP DOI BibTeX RDF
16	Yong Song, Kyu Ho Park	UStore: STT-MRAM Based Light-Weight User-Level Storage for Enhancing Performance of Accessing Persistent Data.	IEICE Trans. Inf. Syst.	2014	DBLP DOI BibTeX RDF
16	Jue Wang, Xiangyu Dong, Yuan Xie 0001	Building and Optimizing MRAM-Based Commodity Memories.	ACM Trans. Archit. Code Optim.	2014	DBLP DOI BibTeX RDF
16	Ravi Patel 0001, Engin Ipek, Eby G. Friedman	2T-1R STT-MRAM memory cells for enhanced on/off current ratio.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
16	Kejie Huang, Rong Zhao, Ning Ning 0001, Yong Lian 0001	A Low Power Localized 2T1R STT-MRAM Array With Pipelined Quad-Phase Saving Scheme for Zero Sleep Power Systems.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
16	Jisu Kim, Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung	A Split-Path Sensing Circuit for Spin Torque Transfer MRAM.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
16	S. Arcaro, Stefano Di Carlo, Marco Indaco, D. Pala, Paolo Prinetto, Elena I. Vatajelu	Integration of STT-MRAM model into CACTI simulator.	IDT	2014	DBLP DOI BibTeX RDF
16	Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar	Improving STT-MRAM density through multibit error correction.	DATE	2014	DBLP DOI BibTeX RDF
16	Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori	Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM.	DATE	2014	DBLP DOI BibTeX RDF
16	Wang Kang 0001, Weisheng Zhao, Lun Yang, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona	One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.	NVMSA	2014	DBLP DOI BibTeX RDF
16	Kejie Huang, Rong Zhao, Yong Lian 0001	STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing.	NANOARCH	2014	DBLP DOI BibTeX RDF
16	Jue Wang, Xiangyu Dong, Yuan Xie 0001	Enabling high-performance LPDDRx-compatible MRAM.	ISLPED	2014	DBLP DOI BibTeX RDF
16	Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita	Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU.	VLSIC	2014	DBLP DOI BibTeX RDF
16	Le Zhang 0001, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy 0001	Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM.	ISCAS	2014	DBLP DOI BibTeX RDF
16	Ravi Patel 0001, Engin Ipek, Eby G. Friedman	Field driven STT-MRAM cell for reduced switching latency and energy.	ISCAS	2014	DBLP DOI BibTeX RDF
16	Matthias Hartmann, Halil Kükner, Prashant Agrawal, Praveen Raghavan, Liesbet Van der Perre, Wim Dehaene	Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories.	ACM Great Lakes Symposium on VLSI	2014	DBLP DOI BibTeX RDF
16	Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori	Avoiding unnecessary write operations in STT-MRAM for low power implementation.	ISQED	2014	DBLP DOI BibTeX RDF
16	Ping Chi, Cong Xu, Xiaochun Zhu, Yuan Xie 0001	Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding.	ISQED	2014	DBLP DOI BibTeX RDF
16	Raphael Robertazzi, Janusz Nowak, Jonathan Sun	Analytical MRAM test.	ITC	2014	DBLP DOI BibTeX RDF
16	Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori	Read disturb fault detection in STT-MRAM.	ITC	2014	DBLP DOI BibTeX RDF
16	Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe	Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.	ISIC	2014	DBLP DOI BibTeX RDF
16	Jayita Das	Auxiliary Roles in STT-MRAM Memory.		2014	RDF
16	Kwangil Choi, Hyunok Oh	An energy aware buffer mapping technique on hybrid STT-MRAM memories with multiple retention time for stream applications.	Des. Autom. Embed. Syst.	2013	DBLP DOI BibTeX RDF
16	Kui Cai 0001, Zhiliang Qin, Bingjin Chen	Channel Capacity and Soft-Decision Decoding of LDPC Codes for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM).	J. Commun.	2013	DBLP DOI BibTeX RDF
16	Ching-Yi Chen, Sheng-Hung Wang, Cheng-Wen Wu	Write Current Self-Configuration Scheme for MRAM Yield Improvement.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
16	Dmytro Apalkov, Alexey Khvalkovskiy, Steven Watts, Vladimir Nikitin, Xueti Tang, Daniel Lottis, Kiseok Moon, Xiao Luo, Eugene Chen, Adrian Ong, Alexander Driskill-Smith, Mohamad Krounbi	Spin-transfer torque magnetic random access memory (STT-MRAM).	ACM J. Emerg. Technol. Comput. Syst.	2013	DBLP DOI BibTeX RDF
16	Wang Kang 0001, Weisheng Zhao, Zhaohao Wang, Yue Zhang 0010, Jacques-Olivier Klein, Youguang Zhang, Claude Chappert, Dafine Ravelosona	A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
16	Safeen Huda, Ali Sheikholeslami	A Novel STT-MRAM Cell With Disturbance-Free Read Operation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
16	Li Zhang, Weisheng Zhao, Yiqi Zhuang, Junlin Bao, Hualian Tang, Cong Li, Xin Xiang	Design and analysis of the reference cells for STT-MRAM.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
16	Kui Cai 0001, Zhiliang Qin, Bingjin Chen	Channel capacity and soft-decision decoding of LDPC codes for spin-torque transfer magnetic random access memory (STT-MRAM).	ICNC	2013	DBLP DOI BibTeX RDF
16	Lionel Torres, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli, Luis Vitório Cargnini	Evaluation of hybrid MRAM/CMOS cells for reconfigurable computing.	NEWCAS	2013	DBLP DOI BibTeX RDF
16	Hiwa Mahmoudi, Thomas Windbacher, Viktor Sverdlov, Siegfried Selberherr	MRAM-based logic array for large-scale non-volatile logic-in-memory applications.	NANOARCH	2013	DBLP DOI BibTeX RDF
16	Thomas W. Andre, Syed M. Alam, Dietmar Gogl, C. K. Subramanian, Hal Lin, W. Meadows, X. Zhang, Nicholas D. Rizzo, Jason Janesky, D. Houssameddine, Jon M. Slaughter	ST-MRAM fundamentals, challenges, and applications.	CICC	2013	DBLP DOI BibTeX RDF
16	Mihail Jefremow, Thomas Kern, Wolf Allers, Christian Peters, Jan Otterstedt, Othmane Bahlous, Karl Hofmann, Robert Allinger, Stephan Kassenetter, Doris Schmitt-Landsiedel	Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS.	ISSCC	2013	DBLP DOI BibTeX RDF
16	Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Yu-Der Chih, Tong-Chern Ong, Tsung-Yung Jonathan Chang, Sreedhar Natarajan, Luan C. Tran	Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology.	ISSCC	2013	DBLP DOI BibTeX RDF
16	Qing Guo 0004, Xiaochen Guo, Ravi Patel 0001, Engin Ipek, Eby G. Friedman	AC-DIMM: associative computing with STT-MRAM.	ISCA	2013	DBLP DOI BibTeX RDF
16	Yong Li 0009, Yaojun Zhang, Yiran Chen 0001, Alex K. Jones	Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration.	IEEE Embed. Syst. Lett.	2012	DBLP DOI BibTeX RDF
16	Weisheng Zhao, Yue Zhang 0010, Thibaut Devolder, Jacques-Olivier Klein, Dafine Ravelosona, Claude Chappert, Pascale Mazoyer	Failure and reliability analysis of STT-MRAM.	Microelectron. Reliab.	2012	DBLP DOI BibTeX RDF
16	Wenqing Wu, Xiaochun Zhu, Seung H. Kang, Kendrick Yuen, Rob Gilmore	Probabilistically Programmed STT-MRAM.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2012	DBLP DOI BibTeX RDF
16	Yongsik Park, Gyu-Hyun Kil, Yunheub Song	A novel sensing algorithm for Spin-Transfer-Torque magnetic RAM (STT-MRAM) by utilizing dynamic reference.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
16	Hyunjun Jang, Baik Song An, Nikhil Kulkarni, Ki Hwan Yum, Eun Jung Kim 0001	A Hybrid Buffer Design with STT-MRAM for On-Chip Interconnects.	NOCS	2012	DBLP DOI BibTeX RDF
16	Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay	Impact of resistive-open defects on the heat current of TAS-MRAM architectures.	DATE	2012	DBLP DOI BibTeX RDF
16	Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay	Coupling-based resistive-open defects in TAS-MRAM architectures.	ETS	2012	DBLP DOI BibTeX RDF
16	Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay	Impact of Resistive-Bridge Defects in TAS-MRAM Architectures.	Asian Test Symposium	2012	DBLP DOI BibTeX RDF
16	Yusung Kim 0002, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy 0001	Write-optimized reliable design of STT MRAM.	ISLPED	2012	DBLP DOI BibTeX RDF
16	Dongsoo Lee, Sumeet Kumar Gupta, Kaushik Roy 0001	High-performance low-energy STT MRAM based on balanced write scheme.	ISLPED	2012	DBLP DOI BibTeX RDF
16	Yahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert	MRAM crossbar based configurable logic block.	ISCAS	2012	DBLP DOI BibTeX RDF
16	Ravi Patel 0001, Engin Ipek, Eby G. Friedman	STT-MRAM memory cells with enhanced on/off ratio.	SoCC	2012	DBLP DOI BibTeX RDF
16	Byung-Min Lee, Gi-Ho Park	Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM.	ISOCC	2012	DBLP DOI BibTeX RDF
16	Lei Jiang 0001, Bo Zhao 0007, Youtao Zhang, Jun Yang 0002	Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors.	DAC	2012	DBLP DOI BibTeX RDF
16	Jee-Hwan Song, Jisu Kim, Seung-Hyuk Kang, Sei-Seung Yoon, Seong-Ook Jung	Sensing margin trend with technology scaling in MRAM.	Int. J. Circuit Theory Appl.	2011	DBLP DOI BibTeX RDF
16	Weisheng Zhao, Thibaut Devolder, Yahya Lakys, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer	Design considerations and strategies for high-reliable STT-MRAM.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
16	Karthik Swaminathan, Ravindhiran Mukundrajan, Niranjan Soundararajan, Vijaykrishnan Narayanan	Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM.	ISVLSI	2011	DBLP DOI BibTeX RDF
16	Weisheng Zhao, Yue Zhang 0010, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli	Embedded MRAM for high-speed computing.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
16	Yiming Huai, Yuchen Zhou, Ioan Tudosa, Roger Malmhall, Rajiv Ranjan, Jing Zhang	Progress and outlook for STT-MRAM.	ICCAD	2011	DBLP DOI BibTeX RDF
16	Weisheng Zhao, Lionel Torres, Yoann Guillemenet, Luis Vitório Cargnini, Yahya Lakys, Jacques-Olivier Klein, Dafine Ravelosona, Gilles Sassatelli, Claude Chappert	Design of MRAM based logic circuits and its applications.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
16	Lionel Torres, Weisheng Zhao	Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
16	Hongbin Sun 0001, Chuanyin Liu, Nanning Zheng 0001, Tai Min, Tong Zhang 0002	Design techniques to improve the device write margin for MRAM-based cache memory.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
16	Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao	Diagnosis of MRAM Write Disturbance Fault.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
16	Jing Li 0073, Patrick Ndai, Ashish Goel, Sayeef S. Salahuddin, Kaushik Roy 0001	Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
16	Jisu Kim, Jee-Hwan Song, Seung-Hyuk Kang, Sei-Seung Yoon, Seong-Ook Jung	Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits.	IEICE Trans. Electron.	2010	DBLP DOI BibTeX RDF
16	Saied Tehrani	Status and prospect for MRAM technology.	Hot Chips Symposium	2010	DBLP DOI BibTeX RDF
16	Lionel Torres, Yoann Guillemenet, Syed Zahid Ahmed	A Dynamic Reconfigurable MRAM based FPGA.	ERSA	2010	DBLP BibTeX RDF
16	Luis Vitório Cargnini, Yoann Guillemenet, Lionel Torres, Gilles Sassatelli	Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM).	ReConFig	2010	DBLP DOI BibTeX RDF
16	Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer	High Density Asynchronous LUT Based on Non-volatile MRAM Technology.	FPL	2010	DBLP DOI BibTeX RDF
16	David Halupka, Safeen Huda, William Song, Ali Sheikholeslami, Koji Tsunoda, Chikako Yoshida, Masaki Aoki	Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS.	ISSCC	2010	DBLP DOI BibTeX RDF
16	Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe	A 64Mb MRAM with clamped-reference and adequate-reference schemes.	ISSCC	2010	DBLP DOI BibTeX RDF
16	Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai	Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
16	Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer	Spin transfer torque (STT)-MRAM-based runtime reconfiguration FPGA circuit.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF
16	Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami, Hiromitsu Hada, Tadahiko Sugibayashi, Naoki Kasai	A 90nm 12ns 32Mb 2T1MTJ MRAM.	ISSCC	2009	DBLP DOI BibTeX RDF
16	Joseph J. Nahas, Thomas W. Andre, Brad Garni, Chitra K. Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino	A 180 Kbit Embeddable MRAM Memory Module.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
16	Wan-Yu Lo, Ching-Yi Chen, Chin-Lung Su, Cheng-Wen Wu	Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault.	ATS	2008	DBLP DOI BibTeX RDF
16	Jing Li 0073, Haixin Liu, Sayeef S. Salahuddin, Kaushik Roy 0001	Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement.	CICC	2008	DBLP DOI BibTeX RDF
16	Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara	A 16-Mb Toggle MRAM With Burst Modes.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
16	Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara	MRAM Cell Technology for Over 500-MHz SoC.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
16	Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai	MRAM Applications Using Unlimited Write Endurance.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
16	Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara	Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
16	Joseph J. Nahas, Thomas W. Andre, Chitra K. Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino	A 180 Kbit Embeddable MRAM Memory Module.	CICC	2007	DBLP DOI BibTeX RDF
16	Weisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert	TAS-MRAM based Non-volatile FPGA logic circuit.	FPT	2007	DBLP DOI BibTeX RDF
16	Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao	Diagnosis for MRAM write disturbance fault.	ITC	2007	DBLP DOI BibTeX RDF
16	Matthew B. Leslie, R. Jacob Baker	Noise-shaping sense amplifier for MRAM cross-point arrays.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
16	Thomas M. Maffitt, John K. DeBrosse, John A. Gabric, Earl T. Gow, Mark C. Lamorey, John S. Parenteau, Dennis R. Willmott, Mark A. Wood, William J. Gallagher	Design considerations for MRAM.	IBM J. Res. Dev.	2006	DBLP DOI BibTeX RDF
16	Michael C. Gaidis, Eugene J. O'Sullivan, Janusz Jozef Nowak, Yu Lu, Sivananda K. Kanakasabapathy, Philip Louis Trouilloud, Daniel Christopher Worledge, Solomon Assefa, Keith R. Milkove, George P. Wright, William J. Gallagher	Two-level BEOL processing for rapid iteration in MRAM development.	IBM J. Res. Dev.	2006	DBLP DOI BibTeX RDF
16	David William Abraham, Philip Louis Trouilloud, Daniel Christopher Worledge	Rapid-turnaround characterization methods for MRAM development.	IBM J. Res. Dev.	2006	DBLP DOI BibTeX RDF
16	Daniel Christopher Worledge	Single-domain model for toggle MRAM.	IBM J. Res. Dev.	2006	DBLP DOI BibTeX RDF
16	Heinz Hoenigschmid, P. Beer, Alexander Bette, R. Dittrich, R. Gardic, Dietmar Gogl, Stefan Lammers, J. Schmid, Laith Altimime, Serge Bournat, Gerhard Müller	Signal-Margin-Screening for Multi-Mb MRAM.	ISSCC	2006	DBLP DOI BibTeX RDF
16	Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda	A 16Mb MRAM with FORK Wiring Scheme and Burst Modes.	ISSCC	2006	DBLP DOI BibTeX RDF
16	Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ming-Jer Kao	Testing MRAM for Write Disturbance Fault.	ITC	2006	DBLP DOI BibTeX RDF
16	Thomas W. Andre, Joseph J. Nahas, Chitra K. Subramanian, Bradley J. Garni, Halbert S. Lin, Asim Omair, William L. Martino	A 4-Mb 0.18-μm 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF