Search results for "PI-Bus"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Milan M. Jovanovic, Milo Tomasevic, Veljko M. Milutinovic	A simulation-based comparison of two reflective memory approaches.	HICSS (1)	1995	DBLP DOI BibTeX RDF	simulation-based comparison, reflective memory approaches, Reflective Memory/Memory Channel, RM/MC system, bus-based system architecture, update consistency mechanism, block transfers, simulation analysis, synthetic workload model, real-time response, run-time actions, compile-time actions, performance evaluation, real-time systems, virtual machines, shared memory systems, distributed memory systems, system buses, message latency, data handling, distributed shared memory systems, shared data
22	Hee Yong Youn, Calvin Ching-Yuen Chen	A Comprehensive Performance Evaluation of Crossbar Networks.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	processor acceptanceprobability, rejected request handling, home memory concept, performance evaluation, performance evaluation, parallel architectures, multiprocessor interconnection networks, multiprocessing systems, memory bandwidth, crossbar networks, bus arbitration
22	Wei-lun Kao, Ravishankar K. Iyer, Dong Tang	FINE: A Fault Injection and Monitoring Environment for Tracing the UNIX System Behavior under Faults.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	FINE, fault injection and monitoring environment, UNIX system behavior, hardware-induced software errors, fault injector, analysis utilities, SunOS 4.1.2, transient Markov reward analysis, bus faults, CPU faults, pointer faults, software tools, Unix, program testing, system monitoring, software faults, software monitor, workload generator
22	Stephan Olariu, James L. Schwing, Jingyuan Zhang	Efficient Image Computations on Reconfigurable Meshes.	CONPAR	1992	DBLP DOI BibTeX RDF	bus systems, computer vision, image processing, segmentation, robotics, convex hull, reconfigurable meshes, area, perimeter, component labeling
22	János Sztrik, Demetres D. Kouvatsos	Asymptotic Analysis of a Heterogeneous Multiprocessor System in a Randomly Changing Environment.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	asymptotic queuing theoretic approach, heterogeneous multiprocessor computer system, randomly changing environment, stochastic times, random environment, service rates, busy period length, exponentially distributed random variable, steady-state performance measures, mean delay time, expected waiting time, performance evaluation, reliability, queueing theory, multiprocessing systems, stochastic processes, bus, system throughput, FCFS
22	Norihisa Suzuki	TOP-1 Multiprocessor Workstation.	Workshop on Parallel Lisp	1989	DBLP DOI BibTeX RDF	Snoop cache, Queuing model simulation, Cache coherency, Interprocessor communication, Shared-bus multiprocessor
21	Martin Mitzlaff, Rüdiger Kapitza, Wolfgang Schröder-Preikschat	Enabling mode changes in a distributed automotive system.	EDCC-CARS	2010	DBLP DOI BibTeX RDF
21	Bin Yu, Zhongzhen Yang	A dynamic holding strategy in public transit systems with real-time information.	Appl. Intell.	2009	DBLP DOI BibTeX RDF	Dynamic holding strategy, Genetic algorithm, SVM, Forecasting
21	Xu Guo 0001, Patrick Schaumont	Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform.	ARC	2009	DBLP DOI BibTeX RDF
21	Christian S. Jensen, Dalia Tiesyte	TransDB: GPS data management with applications in collective transport.	MobiQuitous	2008	DBLP DOI BibTeX RDF
21	Chenjie Yu, Peter Petrov	Latency and bandwidth efficient communication through system customization for embedded multiprocessors.	DAC	2008	DBLP DOI BibTeX RDF	snoop protocol, embedded multiprocessor
21	Sankalp S. Kallakuri, Alex Doboli	Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	Srinivasa R. Sridhara, Naresh R. Shanbhag	Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
21	Brinda Ganesh, Aamer Jaleel, David Wang 0003, Bruce L. Jacob	Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling.	HPCA	2007	DBLP DOI BibTeX RDF
21	Jin Guo 0001, Antonis Papanikolaou, Francky Catthoor	Topology exploration for energy efficient intra-tile communication.	ASP-DAC	2007	DBLP DOI BibTeX RDF
21	Andrew G. Schmidt, Ron Sass	Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing Cores.	FPL	2007	DBLP DOI BibTeX RDF
21	Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu	Exploiting on-chip data behavior for delay minimization.	SLIP	2007	DBLP DOI BibTeX RDF	coding, crosstalk, deep-submicron
21	Seunghyun Oh	The Vehicle Location Tracking System Using Wireless Network.	MMM (2)	2007	DBLP DOI BibTeX RDF	APTS, ad-hoc network, ITS, sensor node, vehicle tracking
21	Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha	Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.	VLSI Design	2007	DBLP DOI BibTeX RDF
21	Andrei Hagiescu, Unmesh D. Bordoloi, Samarjit Chakraborty, Prahladavaradan Sampath, P. Vignesh V. Ganesan, S. Ramesh 0002	Performance Analysis of FlexRay-based ECU Networks.	DAC	2007	DBLP DOI BibTeX RDF
21	Manuel Barranco, Julián Proenza, Guillermo Rodríguez-Navas, Luís Almeida 0001	An active star topology for improving fault confinement in CAN networks.	IEEE Trans. Ind. Informatics	2006	DBLP DOI BibTeX RDF
21	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De	Formal derivation of optimal active shielding for low-power on-chip buses.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	Alokika Dash, Peter Petrov	Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering.	DSD	2006	DBLP DOI BibTeX RDF
21	Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri	Memory-based crosstalk canceling CODECs for on-chip buses.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Valter Filipe Silva, Joaquim Castro Ferreira, José Alberto Fonseca	Dynamic Topology Management in CAN.	ETFA	2006	DBLP DOI BibTeX RDF
21	Suvodeep Gupta, Srinivas Katkoori	Intrabus crosstalk estimation using word-level statistics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
21	Krishnan Sundaresan, Nihar R. Mahapatra	Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses.	HPCA	2005	DBLP DOI BibTeX RDF
21	Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De	Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
21	Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv	A Case Study in Networks-on-Chip Design for Embedded Video.	DATE	2004	DBLP DOI BibTeX RDF
21	Jiangjiang Liu 0002, Krishnan Sundaresan, Nihar R. Mahapatra	Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study.	ICCD	2004	DBLP DOI BibTeX RDF
21	Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne H. Wolf	A dictionary-based en/decoding scheme for low-power data buses.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
21	Daniele Rossi 0001, Steven V. E. S. van Dijk, Richard P. Kleihorst, André K. Nieuwland, Cecilia Metra	Power Consumption of Fault Tolerant Codes: the Active Elements.	IOLTS	2003	DBLP DOI BibTeX RDF
21	Byoung-Woon Kim, Chong-Min Kyung	Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
21	Taro Miura, Yoshikazu Fujishiro	Spectrum management of pulse transmission by high-cut filter line.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
21	Justin A. Boyan, Michael Mitzenmacher	IMproved results for route planning in stochastic transportation.	SODA	2001	DBLP BibTeX RDF
21	Kenneth E. Hoganson	Mapping Parallel Application Communication Topology to Rhombic Overlapping-Cluster Multiprocessors.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	cluster, parallel programming, interconnection network, shared-memory multiprocessor, overlapped cluster
21	Jeffrey B. Rothman, Alan Jay Smith	Analysis of Shared Memory Misses and Reference Patterns.	ICCD	2000	DBLP DOI BibTeX RDF
21	Markus Rudack, Michael Redeker, Dieter Treytnar, Ole Mende, Klaus Herrmann 0002	Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications.	DFT	2000	DBLP DOI BibTeX RDF
21	Krishna Kant 0001, Youjip Won	Server Capacity Planning for Web Traffic Workload.	IEEE Trans. Knowl. Data Eng.	1999	DBLP DOI BibTeX RDF	caching/proxy server, band-width requirements, Web server, self-similarity, symmetric multiprocessors, traffic characterization
21	Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira	Using Complementation and Resequencing to Minimize Transitions.	DAC	1998	DBLP DOI BibTeX RDF	reconfigurable computing, event-driven simulation
21	Xiaohan Qin, Jean-Loup Baer	A Performance Evaluation of Cluster-Based Architectures.	SIGMETRICS	1997	DBLP DOI BibTeX RDF
21	Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano	Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
21	Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, David A. Wood 0001	Coherent Network Interfaces for Fine-Grain Communication.	ISCA	1996	DBLP DOI BibTeX RDF
21	Baher Haroun, Behzad Sajjadi	Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses.	FPGA	1995	DBLP DOI BibTeX RDF
21	Scott T. Leutenegger, Mary K. Vernon	A Mean-Value Performance Analysis of a New Multiprocessor Architecture.	SIGMETRICS	1988	DBLP DOI BibTeX RDF
21	Thomas Philip	Using animated color graphics to illustrate software and hardware organizations (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
21	Jack W. Davidson, Richard A. Vaughan	The Effect of Instruction Set Complexity on Program Size and Memory Performance.	ASPLOS	1987	DBLP DOI BibTeX RDF
21	Cauligi S. Raghavendra	HMESH: A VLSI Architecture for Parallel Processing.	CONPAR	1986	DBLP DOI BibTeX RDF
21	Richard Mateosian	System considerations in the NS32032 design.	AFIPS National Computer Conference	1984	DBLP DOI BibTeX RDF
21	Stephen K. Sunter, Aubin Roy	A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution.	ETS	2011	DBLP DOI BibTeX RDF	mixed-signal DFT, analog bus, mixed-signal BIST
21	Waseem Roshen	Enterprise Service Bus with USB-like Universal Ports.	ECOWS	2011	DBLP DOI BibTeX RDF	Universal Ports, Web Services, SOA, Service Oriented Architecture, Protocol, Services, Enterprise Service Bus, ESB
21	Fangyong Hou, Hongjun He, Nong Xiao, Fang Liu 0002, Guangjun Zhong	Efficient Encryption-Authentication of Shared Bus-Memory in SMP System.	CIT	2010	DBLP DOI BibTeX RDF	Authentication, Encryption, Shared Memory, Bus
21	Lu Ye	A Bus Park Information Integration System Based on J2EE and RFID.	MVHI	2010	DBLP DOI BibTeX RDF	Bus Park, Integratio, RFID, J2EE
21	Guangfeng Chen, Weibin Wang, Yang Xu, Qingqing Li, Zhuo Meng	CAN Bus Based Jacquard Control System for Carpet Tufting Machine.	MVHI	2010	DBLP DOI BibTeX RDF	carpet tufting machine, jacquard control system, step motor, CAN Bus
21	Luobei Kuang, Ming Xu 0002, Zhijun Wang	An Adaptive Routing Protocol for Bus Networks.	AINA	2010	DBLP DOI BibTeX RDF	bus network, routing protocol, Internet access
21	Kota Tsubouchi, Kazuo Hiekata, Hiroyuki Yamato	Scheduling Algorithm for On-Demand Bus System.	ITNG	2009	DBLP DOI BibTeX RDF	On-line Dial-A-Ride Problem with Time Window, On-demand Bus
21	Hongkyun Jung, Xianzhe Jin, Younjin Jung, Ok Kim, Byoungyup Lee, Jungbum Heo, Kwangki Ryoo	Design of Multimedia SoC Platform with a Crossbar On-Chip Bus for Embedded Systems.	NCM (1)	2008	DBLP DOI BibTeX RDF	SoC platform, crossbar, on-chip bus
21	Maurizio Skerlj, Paolo Ienne	Error Protected Data Bus Inversion Using Standard DRAM Components.	ISQED	2008	DBLP DOI BibTeX RDF	bus inversion, reliability, low power, memory, ECC, DRAM, error protection
21	Marcin Szpyrka	Analysis of VME-Bus communication protocol - RTCP-net approach.	Real Time Syst.	2007	DBLP DOI BibTeX RDF	RTCP-nets, VME-Bus
21	K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas	Bus encoding schemes for minimizing delay in VLSI interconnects.	SBCCI	2007	DBLP DOI BibTeX RDF	bus encoding technique, crosstalk class, delay, encoder, decoder, VLSI interconnects
21	Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez	A parallelized way to provide data encryption and integrity checking on a processor-memory bus.	DAC	2006	DBLP DOI BibTeX RDF	bus encryption, data confidentiality and integrity, architectures
21	Robert C. Martin	The Test Bus Imperative: Architectures That Support Automated Acceptance Testing.	IEEE Softw.	2005	DBLP DOI BibTeX RDF	automated acceptance testing, test bus
21	Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino	Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces.	ISLPED	2004	DBLP DOI BibTeX RDF	LCD displays, digital display interfaces, low-power bus encoding
21	Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III	Low-power design methodology for an on-chip bus with adaptive bandwidth capability.	DAC	2003	DBLP DOI BibTeX RDF	low-power, delay, on-chip interconnect, bus, current-mode, point-to-point
21	Jörg Henkel, Tony Givargis, Frank Vahid	Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design.	DATE	2000	DBLP DOI BibTeX RDF	low power, cache, estimation, System-on-a-chip, intellectual property, on-chip bus
21	Chauchin Su, Yue-Tsang Chen	Crosstalk Effect Removal for Analog Measurement in Analog Test Bus.	VTS	2000	DBLP DOI BibTeX RDF	Analog Test Bus, Design for Testability, Analog Test, Mixed Signal Test
21	Chung-Ho Chen, Feng-Fu Lin	An Easy-to-Use Approach for Practical Bus-Based System Design.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Bus-based shared-memory multiprocessor, queuing delay model, system design, memory system design
21	Tommy Klevin, Lennart Lindh	Scalable Architecture for Real-Time Applications and Use of Bus-Monitoring.	RTCSA	1999	DBLP DOI BibTeX RDF	bus monitor and multiprocessor systems, real-time system, architecture, real-time kernel
21	Haklin Kimm	Two dimensional maximal elements problem on a reconfigurable optical pipelined bus system.	SAC	1998	DBLP DOI BibTeX RDF	maximal dominance, reconfigurable pipelined optical bus system, parallel algorithm, computational geometry
21	Keqin Li	Constant Time Boolean Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System.	J. Supercomput.	1997	DBLP DOI BibTeX RDF	Boolean matrix closure, reconfigurability, time complexity, cost, transitive closure, processor array, optical bus, boolean matrix multiplication
21	Pedro A. Molina, Peter Y. K. Cheung	A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems.	ASYNC	1997	DBLP DOI BibTeX RDF	Tri-state Buffers, Asynchronous, Composability, Bus, Data Path, Delay-Insensitive, Handshake Circuits
21	Horng-Ren Tsai, Shi-Jinn Horng, Shun-Shan Tsai, Shung-Shing Lee, Tzong-Wann Kao, Chia-Ho Chen	Parallel Clustering Algorithms on a Reconfigurable Array of Processors with Wider Bus Networks.	ICPADS	1997	DBLP DOI BibTeX RDF	k-means method, array of processors with a wider bus network (RAPWBN), pattern recognition, parallel algorithm, image processing, cluster analysis, pattern cluster
21	P. Bosch, A. Carloganu, Daniel Etiemble	Complete x86 instruction trace generation from hardware bus collect.	EUROMICRO	1997	DBLP DOI BibTeX RDF	complete x86 instruction trace generation, hardware bus collect, architectural improvements, benchmark traces, hardware/software approach, x86 execution traces, commercial analyzer, computer architecture, microprocessors, memory hierarchies, trace driven simulation, performance data
21	Kanad Chakraborty, Pinaki Mazumder	An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards.	ICCAD	1996	DBLP DOI BibTeX RDF	bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing
21	Tsutomu Ishikawa	Hypercube Multiprocessors with Bus Connections for Improving Communication Performance.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	bus connection, Hypercubes, routing algorithms, Hamming code, communication performance, network diameter, multiprocessor network, perfect code
21	Michael Sheliga, Edwin Hsing-Mean Sha	Bus minimization and scheduling of multi-chip systems.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	bus minimization, multi-chip module design, scheduling, scheduling, logic CAD, polynomial time algorithm, circuit layout CAD, multichip modules, signal flow graphs, signal flow graphs, algorithm efficiency
21	Oran Sharon, Adrian Segall	On the efficiency of slot reuse in the Dual Bus configuration.	IEEE/ACM Trans. Netw.	1994	DBLP DOI BibTeX RDF	destination release, slotted dual-bus, medium access control, slot reuse
21	Appie van de Liefvoort, Narayan Subramanian	A New Approach for the Performance Analysis of a Single-Bus Multiprocessor System with General Service Times.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	single-bus multiprocessor system, general service times, linear algebraic approach, M/G/1/N queuing system, load-dependent arrivals, rational Laplace transform, symbolic programming techniques, explicit closed-form expression, performance evaluation, performance analysis, queueing theory, multiprocessing systems, queuing theory
21	Barry Wilkinson	On Crossbar Switch and Multiple Bus Interconnection Networks with Overlapping Connectivity.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	multiple bus interconnection networks, overlapping connectivity, overlapping connectivity networks, multiprocessor interconnection networks, neural computers, dataflow computers
21	MenChow Chiang, Gurindar S. Sohi	Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	throughput-oriented environment, overall throughput, design choices, mean value analysis analytical models, trace-driven simulation analysis, cache block sizes, cache set associativity, multiprocessor throughput, performance evaluation, performance, multiprocessing systems, digital simulation, shared bus multiprocessors
21	Qing Yang 0001, Laxmi N. Bhuyan	Analysis of Packet-Switched Multiple-Bus Multiprocessor Systems.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	approximate queueing network models, packet-switched multiple-bus multiprocessor systems, flow equivalence, crossbar-based multiprocessors, performance evaluation, performance analysis, queueing theory, packet switching, multiprocessing systems, decomposition, single-server queue, synchronous control, asynchronous control
21	Ibrahim H. Önyüksel, Keki B. Irani	Markovian Queueing Network Models for Performance Analysis of a Single-Bus Multiprocessor System.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	Markovian queueing network models, single-bus multiprocessor system, r-stage hypoexponential distribution, hyperexponential distribution, equilibrium probabilities, service time distributions, performance evaluation, performance analysis, Markov processes, queueing theory, multiprocessing systems, recurrence relations
21	S. S. S. P. Rao, J. R. Isaac	Interface Optimization: An Algorithm for the Detection of Data Path Redundancy and Reconfigurability Towards Obtaining Minimal Bus Interfaces.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	submodules interconnection, data path redundancy, minimal bus interfaces, indirect paths, VLSI, reconfigurability, redundancy, design tool, data transfer, digital systems, computer interfaces, computer interfaces
21	Bohdan L. Bodnar, A. C. Liu	Modeling and Performance Analysis of Single-Bus Tightly-Coupled Multiprocessors.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	global performance metrics, single-bus tightly-coupled multiprocessors, hierarchical stochastic queuing model, single queue/server pair, probabilistic task migration, CPU sensitivity analysis, performance evaluation, modelling, performance analysis, shared memory, multiprocessing systems, processing elements
21	Shahid H. Bokhari	Finding Maximum on an Array Processor with a Global Bus.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	two-phase algorithm, global bus, maximum, parallel processing, networks, Array processors, interconnection structures
21	Pauline Markenscoff	A Deterministic Model for Evaluating the Performance of a Multiple Processor with a Shared Bus.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	performance evaluation, real time control, Multiple processor system, shared bus
21	Keki B. Irani, Ibrahim H. Önyüksel	A Closed-Form Solution for the Performance Analysis of Multiple-Bus Multiprocessor Systems.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	Markovian queueing networks, performance analysis, Markov chains, multiprocessor systems, memory contention, Bus contention, processing efficiency, multiple buses
21	Michael Fine, Fouad A. Tobagi	Demand Assignment Multiple Access Schemes in Broadcast Bus Local Area Networks.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	Broadcast bus networks, multiaccess protocols, performance, local area networks, packet switching, random access, carrier sensing, token passing
21	Marco Ajmone Marsan, Gianfranco Balbo, Gianni Conte, Francesco Gregoretti	Modeling Bus Contention and Memory Interference in a Multiprocessor System.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	performance evaluation, Petri nets, Markov chains, multiprocessors, message passing, queueing networks, memory interference, Bus contention
21	P. V. Afshari, Steven C. Bruell, Richard Y. Kain	On the Load Balancing Bus Accessing Scheme.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	modeling, load balancing, distributed computing, queueing networks, Bus
21	Werner Bux	Analysis of a Local-Area Bus System with Controlled Access.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	scheduling, performance, protocol, Access method, bus, local network
21	Tomás Lang, Mateo Valero, Ignacio Alegre	Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	multiprocessors, shared memory, memory bandwidth, Bus arbitration, multiple buses
21	Kwok-Tung Fung, Hwa C. Torng	On the Analysis of Memory Conflicts and Bus Contentions in a Multiple-Microprocessor System.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	multiple-microprocessor system, interference, memory mapping, memory conflict, Bus contention
20	Chen Kang Lo, Ren-Song Tsay	Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model.	ASP-DAC	2009	DBLP DOI BibTeX RDF
20	Ralph Mietzner, Tammo van Lessen, Alexander Wiese, Matthias Wieland 0001, Dimka Karastoyanova, Frank Leymann	Virtualizing Services and Resources with ProBus: The WS-Policy-Aware Service and Resource Bus.	ICWS	2009	DBLP DOI BibTeX RDF
20	Min-Young Nam, Rodolfo Pellizzoni, Lui Sha, Richard M. Bradford	ASIIST: Application Specific I/O Integration Support Tool for Real-Time Bus Architecture Designs.	ICECCS	2009	DBLP DOI BibTeX RDF
20	Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag	Joint Equalization and Coding for On-Chip Bus Communication.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
20	Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey	Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
20	Sampo Tuuna, Li-Rong Zheng 0001, Jouni Isoaho, Hannu Tenhunen	Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
20	Zonghai Chen, Haibo Wang	Open Intelligent Robot Controller Based on Field-Bus and RTOS.	Innovations in Hybrid Intelligent Systems	2008	DBLP DOI BibTeX RDF