Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Shan Yan, Bill Lin 0001 |
Stream Execution on Embedded Wide-Issue Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2008, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Tsung-Han Tsai 0001, Chun-Nan Liu, Jui Hong Hung |
VLIW-aware software optimization of AAC decoder on parallel architecture core DSP (PACDSP) processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Consumer Electron. ![In: IEEE Trans. Consumer Electron. 54(2), pp. 933-939, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Rahul Nagpal, Y. N. Srikant |
Pragmatic integrated scheduling for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Pract. Exp. ![In: Softw. Pract. Exp. 38(3), pp. 227-257, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Nagm Mohamed, Nazeih Botros, Mohamad Alweh |
Cache Memory Energy Exploitation in VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCSS (2) ![In: Advanced Techniques in Computing Sciences and Software Engineering, Volume II of the proceedings of the 2008 International Conference on Systems, Computing Sciences and Software Engineering (SCSS), part of the International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering, CISSE 2008, Bridgeport, Connecticut, USA, pp. 351-355, 2008, Springer, 978-90-481-3659-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Michael Vogel, Mario Schölzel |
Automatic Generation of Cycle Accurate SystemC Models for Application Specific Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Freiburg, Germany, March 3-5, 2008, pp. 81-90, 2008, Shaker. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
16 | Mostafa E. A. Ibrahim, Markus Rupp, Hossam A. H. Fahmy |
Power estimation methodology for VLIW Digital Signal Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSCC ![In: 42nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2008, Pacific Grove, CA, USA, October 26-29, 2008, pp. 1840-1844, 2008, IEEE, 978-1-4244-2940-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Dirk Tetzlaff |
Erweitertes Hyperblock-Scheduling für VLIW-Prozessoren. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Informatiktage ![In: Informatiktage 2008 - Fachwissenschaftlicher Informatik-Kongress, 14. und 15. März 2008, B-IT Bonn-Aachen International Center for Information Technology in Bonn, pp. 111-114, 2008, GI, 978-3-88579-440-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
16 | Stephan Wong, Thijs van As, Geoffrey Brown |
p-VEX: A reconfigurable and extensible softcore VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008, pp. 369-372, 2008, IEEE, 978-1-4244-2796-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Abbas Hormati, Sied Mehdi Fakhraie |
An Efficient and Extendable Modeling Approach for VLIW DSP Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSICC ![In: Advances in Computer Science and Engineering - 13th International CSI Computer Conference, CSICC 2008, Kish Island, Iran, March 9-11, 2008 Revised Selected Papers, pp. 267-274, 2008, 978-3-540-89984-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Debyo Saptono, Vincent Brost, Fan Yang 0019, Eri Prasetyo |
Design Space Exploration for a Custom VLIW Architecture: Direct Photo Printer Hardware Setting Using VEX Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SITIS ![In: 4th IEEE International Conference on Signal Image Technology and Internet Based Systems, SITIS 2008, Bali, Indonesia, November 30 - December 3, 2008, pp. 416-421, 2008, IEEE Computer Society, 978-0-7695-3493-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Gunter Haug |
Emulation synthetisierter Verhaltensbeschreibungen mit VLIW-Prozessoren ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2008 |
RDF |
|
16 | Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim |
An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 42(10), pp. 2257-2269, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Christoph W. Kessler, Andrzej Bednarski, Mattias V. Eriksson |
Classification and generation of schedules for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 19(18), pp. 2369-2389, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee |
PALF: compiler supports for irregular register files in clustered VLIW DSP processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 19(18), pp. 2391-2406, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | |
Real-time Face Recognition Using SIMD and VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Inf. Technol. ![In: J. Comput. Inf. Technol. 15(2), pp. 143-149, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest |
Energy-aware compilation and hardware design for VLIW embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Embed. Syst. ![In: Int. J. Embed. Syst. 3(1/2), pp. 73-82, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Vincenzo Catania, Maurizio Palesi, Davide Patti |
Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 16(5), pp. 819-846, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Muhammad Sohail Sadiq, Shoab Ahmed Khan |
Optimal Mapping of DSP Algorithms on Commercially Available Off-The-Shelf (COTS) VLIW DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Consumer Electron. ![In: IEEE Trans. Consumer Electron. 53(3), pp. 1061-1067, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Pawel Pawlowski, Adam Dabrowski, Mario Schölzel |
Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007, pp. 313-318, 2007, IEEE Computer Society, 1-4244-1161-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Jos Huisken |
Integrating VLIW Processors with a Network on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 2, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner |
A Customizable LEON2-Based VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007, pp. 55-60, 2007, Univ. Montpellier II, 2-9517461-3-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
16 | Min Li 0001, Bruno Bougard, Eduardo Lopez-Estraviz, André Bourdoux, Liesbet Van der Perre, Francky Catthoor |
The Quality-Energy Scalable OFDMA Modulation for Low Power Transmitter and VLIW Processor Based Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GLOBECOM ![In: Proceedings of the Global Communications Conference, 2007. GLOBECOM '07, Washington, DC, USA, 26-30 November 2007, pp. 2894-2898, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Amin Farmahini Farahani, Mahmoud Mousavinezhad, Sied Mehdi Fakhraie |
Simulation of Voice Processing Applications through VLIW DSP Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007, pp. 291-293, 2007, IEEE, 978-1-4244-1377-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Vincent Brost, Fan Yang 0019, Michel Paindavoine |
A modular VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3968-3971, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Ricardo Ribeiro dos Santos |
2D-VLIW: a processor architecture based on the geometry of the computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2007 |
RDF |
|
16 | Esther Salamí |
Optimizing VLIW architectures for multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2007 |
RDF |
|
16 | Montserrat Ros |
Code compression optimisation for VLIW processors ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2007 |
RDF |
|
16 | Christoph W. Keßler, Andrzej Bednarski |
Optimal integrated code generation for VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 18(11), pp. 1353-1390, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Karine Heydemann, François Bodin, Peter M. W. Knijnenburg, Laurent Morin |
UFS: a global trade-off strategy for loop unrolling for VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 18(11), pp. 1413-1434, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Enric Gibert, F. Jesús Sánchez, Antonio González 0001 |
Instruction scheduling for a clustered VLIW processor with a word-interleaved cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 18(11), pp. 1391-1411, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Alex K. Jones, Raymond R. Hoare, Dara Kusic, Justin Stander, Gayatri Mehta, Joshua Fazekas |
A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 53-II(11), pp. 1250-1254, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Raymond R. Hoare, Alex K. Jones, Dara Kusic, Joshua Fazekas, John Foster 0001, Shen Chih Tung, Michael L. McCloud |
Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Adv. Signal Process. ![In: EURASIP J. Adv. Signal Process. 2006, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest |
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 339-344, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl |
Datapath and ISA Customization for Soft VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, September 20-22, 2006, pp. 280-289, 2006, IEEE Computer Society, 1-4244-0690-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti |
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: IEEE International Conference on Evolutionary Computation, CEC 2006, part of WCCI 2006, Vancouver, BC, Canada, 16-21 July 2006, pp. 1736-1743, 2006, IEEE, 0-7803-9487-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Rahul Nagpal, Y. N. Srikant |
Exploring Energy-Performance Trade-Offs for Heterogeneous Interconnect Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2006, 13th International Conference, Bangalore, India, December 18-21, 2006, Proceedings, pp. 497-508, 2006, Springer, 3-540-68039-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga |
Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 541-546, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Andy Heinig, Mario Schölzel |
Zeitbeschränkte Clusterung zur Design-Space-Exploration geclusterter VLIW-Prozessoren. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Dresden, Germany, February 20-22, 2006, pp. 319-328, 2006, Fraunhofer Institut für Integrierte Schaltungen. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
16 | Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim |
A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006, pp. 1606-1615, 2006, IEEE, 1-4244-0079-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Sourav Roy, Rajat Bhatia, Ashish Mathur |
An accurate Energy estimation framework for VLIW Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, pp. 464-469, 2006, IEEE, 978-0-7803-9707-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Zhou Zhixiong, Yang Xu, He Hu 0002, Yihe Sun |
A Retargetable Compiler of VLIW ASIP for Media Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2006 International Conference on Embedded Systems & Applications, Las Vegas, Nevada, USA, June 26-29, 2006, pp. 46-52, 2006, CSREA Press, 1-60132-017-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
16 | Reza Iraji, Hamid Sarbazi-Azad |
A Probability-Based Instruction Combining Method for Scheduling in VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), March 8-11, Dubai/Sharjah, UAE, pp. 673-679, 2006, IEEE Computer Society, 1-4244-0211-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Giuseppe Desoli, Thierry Strudel, Jean-Philippe Cousin, Kaushik Saha |
Current and future trends in embedded VLIW microprocessors applied to multimedia and signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSIPCO ![In: 14th European Signal Processing Conference, EUSIPCO 2006, Florence, Italy, September 4-8, 2006, pp. 1-5, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
16 | Mario Schölzel |
Automatisierter Entwurf anwendungsspezifischer VLIW-Prozessoren. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
RDF |
|
16 | Shu Xiao 0001 |
Power-balanced instruction scheduling for pipelined VLIW architectures ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
DOI RDF |
|
16 | Alessandro Scotto |
Architectural exploration technology based on simulation of reconfigurable VLIW processors driven by multimedia applications for HW-SW co-design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
RDF |
|
16 | Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon |
Reducing the complexity of instruction-level power models for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 10(1), pp. 49-67, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Steve Haga, Andrew Webber, Yi Zhang, Nghi Nguyen, Rajeev Barua |
Reducing code size in VLIW instruction scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Embed. Comput. ![In: J. Embed. Comput. 1(3), pp. 415-433, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
16 | Jean-Luc Gaudiot, Jung-Yup Kang, Won Woo Ro |
Techniques to Improve Performance Beyond Pipelining: Superpipelining, Superscalar, and VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adv. Comput. ![In: Adv. Comput. 63, pp. 2-35, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon |
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 38(3), pp. 515-524, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Kazutoshi Kobayashi, Masao Aramoto, Hidetoshi Onodera |
A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 88-C(4), pp. 552-558, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Radu Muresan, Catherine H. Gebotys |
Instantaneous current modeling in a complex VLIW processor core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(2), pp. 415-451, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Instruction-level current model, current and power measurement in a processor, instantaneous current model, power and energy model |
16 | Joseph A. Fisher, Paolo Faraboschi, Cliff Young |
Embedded computing - a VLIW approach to architecture, compilers, and tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2005 |
RDF |
|
16 | Stephan Suijkerbuijk, Ben H. H. Juurlink |
Implementing Hardware Multithreading in a VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IASTED PDCS ![In: International Conference on Parallel and Distributed Computing Systems, PDCS 2005, November 14-16, 2005, Phoenix, AZ, USA, pp. 674-679, 2005, IASTED/ACTA Press, 0-88986-525-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
16 | Atsushi Tsukikawa, Fumihito Furukawa, Takayuki Aoki, Daisuke Oka, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba |
Design and Implementation of a VLIW Processor Simulation Environment with Instruction Scheduling Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IASTED PDCS ![In: International Conference on Parallel and Distributed Computing Systems, PDCS 2005, November 14-16, 2005, Phoenix, AZ, USA, pp. 536-541, 2005, IASTED/ACTA Press, 0-88986-525-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
16 | Shu Xiao 0001, Edmund Ming-Kit Lai |
A rough programming approach to power-aware VLIW instruction scheduling for digital signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP (5) ![In: 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '05, Philadelphia, Pennsylvania, USA, March 18-23, 2005, pp. 141-144, 2005, IEEE, 0-7803-8874-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Kevin D. Rich, Shankar G. Govindaraju, Robert Shaw, David Dobrikin |
DVGen: a test generator for the transmeta Efficeon VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30 - December 2, 2005, pp. 94-101, 2005, IEEE Computer Society, 0-7803-9571-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Arun Vijayaraghavan, M. Kannan, R. Seshasayanan |
Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005, pp. 143-152, 2005, CSREA Press, 1-932415-54-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
16 | Francesco Menichelli, Mauro Olivieri, Simone Smorfa, Irene Zaccardini |
Software optimization of the JPEG2000 algorithm on a VLIW CPU core for system-on-chip implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits, Signals, and Systems ![In: Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, Marina del Rey, CA, USA, October 24-26, 2005, pp. 222-227, 2005, IASTED/ACTA Press, 0-88986-509-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
16 | Minyi Guo |
Keynote Address: Energy-Aware Compiler Scheduling for VLIW Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 34th International Conference on Parallel Processing Workshops (ICPP 2005 Workshops), 14-17 June 2005, Oslo, Norway, pp. 197, 2005, IEEE Computer Society, 0-7695-2381-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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16 | Thomas Zeitlhofer, Bernhard Wess |
Integrated assignment of registers and functional units for heterogeneous vliw-architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Proceedings 2005 IEEE International SOC Conference, September 25-28, 2005, Washington Dulles Airport, Herndon, VA, USA, pp. 119-124, 2005, IEEE, 0-7803-9264-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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16 | Hamed Fatemi, Henk Corporaal, Twan Basten, Richard P. Kleihorst, Pieter P. Jonker |
Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIVS ![In: Advanced Concepts for Intelligent Vision Systems, 7th International Conference, ACIVS 2005, Antwerp, Belgium, September 20-23, 2005, Proceedings, pp. 689-696, 2005, Springer, 3-540-29032-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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16 | Shu Xiao 0001, Edmund Ming-Kit Lai, A. Prasad Vinod 0001 |
VLIW instruction scheduling for DSP processors based on rough set theory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSPA ![In: Proceedings of the Eighth International Symposium on Signal Processing and Its Applications, ISSPA 2005, 28-31 August 2005, Sydney, Australia, pp. 311-314, 2005, IEEE, 0-7803-9243-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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16 | Steve Haga |
VLIW Instruction Scheduling for Reduced Code Size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2005 |
RDF |
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16 | Domenico Barretta |
Joint exploitation of ILP and thread level parallelism on multicluster VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2005 |
RDF |
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16 | Suhyun Kim, Soo-Mook Moon, Kemal Ebcioglu, Erik R. Altman |
VLaTTe: A Java Just-in-Time Compiler for VLIW with Fast Scheduling and Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 87-D(7), pp. 1712-1720, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
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16 | Wanli Liu, David H. Albonesi, John Gostomski, Lloyd Palum, Dave Hinterberger, Rick Wanzenried, Mark Indovina |
An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 13(6), pp. 1321-1346, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Mile K. Stojcev |
Power estimation and optimization for VLIW-based embedded systems; Vittorio Zaccaria, Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano. Hardcover, pp 203, plus XXIV, Kluwer Academic Publishers, Boston, 2003. ISBN 1-4020-7377-1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 44(4), pp. 707-708, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Jinhwan Kim, Yunheung Paek, Gang-Ryung Uh |
Code optimizations for a VLIW-style network processing unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Pract. Exp. ![In: Softw. Pract. Exp. 34(9), pp. 847-874, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Zili Shao, Qingfeng Zhuge, Youtao Zhang, Edwin Hsing-Mean Sha |
Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Comput. Netw. ![In: Int. J. High Perform. Comput. Netw. 1(1/2/3), pp. 4-16, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero |
High-performance and low-power VLIW cores for numerical computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Comput. Netw. ![In: Int. J. High Perform. Comput. Netw. 1(4), pp. 171-179, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero |
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 88-97, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Seokhoon Ju, Wonyong Sung |
Implementation of a digital color copier using a VLIW SIMD architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP (5) ![In: 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2004, Montreal, Quebec, Canada, May 17-21, 2004, pp. 933-936, 2004, IEEE, 0-7803-8484-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Brian Valentine, Oliver P. Sohm |
Optimizing the JPEG2000 binary arithmetic encoder for VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP (5) ![In: 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2004, Montreal, Quebec, Canada, May 17-21, 2004, pp. 117-120, 2004, IEEE, 0-7803-8484-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Alex K. Jones, Raymond Hoare, Ivan S. Kourtev, Joshua Fazekas, Dara Kusic, John Foster 0001, Sedric Boddie, Ahmed Muaydh |
A 64-way VLIW/SIMD FPGA architecture and design flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004, Tel Aviv, Israel, December 13-15, 2004, pp. 499-502, 2004, IEEE, 0-7803-8715-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Montserrat Ros, Peter Sutton |
Code Compression Based on Operand-Factorization for VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Data Compression Conference ![In: 2004 Data Compression Conference (DCC 2004), 23-25 March 2004, Snowbird, UT, USA, pp. 559, 2004, IEEE Computer Society, 0-7695-2082-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Yu Hu 0016, Qing Li 0001, C.-C. Jay Kuo |
Efficient implementation of elliptic curve cryptography (ECC) on VLIW-micro-architecture media processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, ICME 2004, 27-30 June 2004, Taipei, Taiwan, pp. 879-882, 2004, IEEE Computer Society, 0-7803-8603-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
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16 | Andreas Lundgren, Wido Kruijtzer |
A scalable VLIW for smart imaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2004, Stockholm, Sweden, September 6-7, 2004, pp. 47-52, 2004, IEEE Computer Society, 0-7803-8631-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Johannes Fürtler, Konrad J. Mayer, Werner Krattenthaler, Ivan Bajla |
SPOT - Development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Imaging ![In: Real Time Imaging 9(6), pp. 387-399, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Andrea Lodi 0002, Mario Toma, Fabio Campi, Andrea Cappelli, Roberto Canegallo, Roberto Guerrieri |
A VLIW processor with reconfigurable instruction set for embedded applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(11), pp. 1876-1886, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda |
A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(11), pp. 1992-2000, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Miroslav N. Velev, Randal E. Bryant |
Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Symb. Comput. ![In: J. Symb. Comput. 35(2), pp. 73-106, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Satish Pillai, Margarida F. Jacome |
Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Embedded Software for SoC ![In: Embedded Software for SoC, pp. 245-259, 2003, Kluwer / Springer, 978-1-4020-7528-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Wayne H. Wolf, I. Burak Özer, Tiehan Lv |
Exploiting parallelism in media processing using VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (3) ![In: Proceedings of the 2003 International Conference on Image Processing, ICIP 2003, Barcelona, Catalonia, Spain, September 14-18, 2003, pp. 97-100, 2003, IEEE, 0-7803-7750-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Enric Gibert, F. Jesús Sánchez, Antonio González 0001 |
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 315-325, 2003, IEEE Computer Society, 0-7695-2043-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Taeksang Hwang, Wonyong Sung |
Implementation of a digital copier using TMS320C6414 VLIW DSP processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP (2) ![In: 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '03, Hong Kong, April 6-10, 2003, pp. 621-624, 2003, IEEE, 0-7803-7663-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | J. Prakash, C. Sandeep, Priti Shankar, Y. N. Srikant |
A Simple and Fast Scheme for Code Compression for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCC ![In: 2003 Data Compression Conference (DCC 2003), 25-27 March 2003, Snowbird, UT, USA, pp. 444, 2003, IEEE Computer Society, 0-7695-1896-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Jun Tanahe, Yasuhiro Taniguchi, Takashi Miyamori, Yukimasa Miyamoto, Hideki Takeda, Masaya Tarui, Hiromitsu Nakayama, Nohuyulu Takeda, Kenichi Maeda, Masataka Matsui |
Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003, pp. 185-188, 2003, IEEE, 0-7803-7842-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero |
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings, pp. 113-126, 2003, Springer, 3-540-20359-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: First Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2003, October 3-4, 2003, Newport Beach, California, USA, co-located with CODES-ISSS 2003, Proceedings, pp. 65-72, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
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16 | Davide Rizzo, Osvaldo Colavin, Shiva Navab |
A Runtime Reconfigurable Clustered VLIW Architecture for Mediaprocessing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: First Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2003, October 3-4, 2003, Newport Beach, California, USA, co-located with CODES-ISSS 2003, Proceedings, pp. 142-148, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
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16 | G. R. Chaji, R. M. Pourrad, Seid Mehdi Fakhraie, Mohammad H. Tehranipour |
eUTDSP: a design study of a new VLIW-based DSP architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 137-140, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Sunghyun Jee, Kannappan Palaniappan |
Performance of dynamically scheduling VLIW instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: Proceedings of the 2003 International Symposium on System-on-Chip, Tampere, Finland, November 19-21, 2003, pp. 7-10, 2003, IEEE, 0-7803-8160-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Ulrich Hirnschrott, Andreas Krall |
VLIW operation refinement for reducing energy consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: Proceedings of the 2003 International Symposium on System-on-Chip, Tampere, Finland, November 19-21, 2003, pp. 131-134, 2003, IEEE, 0-7803-8160-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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16 | Massimo Bariani |
Architectural exploration technology based on simulation of VLIW processors driven by multimedia applications for HW-SW co-design of embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2003 |
RDF |
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16 | Luca Benini, Davide Bruni, Mauro Chinosi, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon |
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 7(3), pp. 183-203, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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16 | Cagdas Akturan, Margarida F. Jacome |
An Effective Software Pipelining Algorithm for Clustered Embedded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 7(1-2), pp. 115-138, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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16 | Sanjive Agarwala, Timothy Anderson, Anthony M. Hill, M. D. Ales, Raguram Damodaran, Paul Wiley, Steven Mullinnix, J. Leach, Anthony Lell, Michael Gill, Arjun Rajagopal, Abhijeet Chachad, M. Agarwala, John Apostol, Manjeri Krishnan, Duc Bui, Quang An, N. S. Nagaraj, Tod Wolf, T. T. Elappuparackal |
A 600-MHz VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(11), pp. 1532-1544, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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16 | Chris Basoglu, Woobin Lee, John O'Donnell |
The Equator MAP-CA™ DSP: an end-to-end broadband signal processor™ VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 12(8), pp. 646-659, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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16 | K. H. Hong, Woon-Seng Gan, Yong Kim Chong, T. F. Cheong, S. H. Tan |
Rapid prototyping of DSP algorithms on VLIW TMS320C6701 DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 26(7), pp. 311-324, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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