Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Shan Yan, Bill Lin 0001 |
Stream Execution on Embedded Wide-Issue Clustered VLIW Architectures. |
EURASIP J. Embed. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Tsung-Han Tsai 0001, Chun-Nan Liu, Jui Hong Hung |
VLIW-aware software optimization of AAC decoder on parallel architecture core DSP (PACDSP) processor. |
IEEE Trans. Consumer Electron. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Rahul Nagpal, Y. N. Srikant |
Pragmatic integrated scheduling for clustered VLIW architectures. |
Softw. Pract. Exp. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Nagm Mohamed, Nazeih Botros, Mohamad Alweh |
Cache Memory Energy Exploitation in VLIW Architectures. |
SCSS (2) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Michael Vogel, Mario Schölzel |
Automatic Generation of Cycle Accurate SystemC Models for Application Specific Clustered VLIW Processors. |
MBMV |
2008 |
DBLP BibTeX RDF |
|
16 | Mostafa E. A. Ibrahim, Markus Rupp, Hossam A. H. Fahmy |
Power estimation methodology for VLIW Digital Signal Processors. |
ACSCC |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Dirk Tetzlaff |
Erweitertes Hyperblock-Scheduling für VLIW-Prozessoren. |
Informatiktage |
2008 |
DBLP BibTeX RDF |
|
16 | Stephan Wong, Thijs van As, Geoffrey Brown |
p-VEX: A reconfigurable and extensible softcore VLIW processor. |
FPT |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Abbas Hormati, Sied Mehdi Fakhraie |
An Efficient and Extendable Modeling Approach for VLIW DSP Processors. |
CSICC |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Debyo Saptono, Vincent Brost, Fan Yang 0019, Eri Prasetyo |
Design Space Exploration for a Custom VLIW Architecture: Direct Photo Printer Hardware Setting Using VEX Compiler. |
SITIS |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Gunter Haug |
Emulation synthetisierter Verhaltensbeschreibungen mit VLIW-Prozessoren |
|
2008 |
RDF |
|
16 | Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim |
An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches. |
IEEE J. Solid State Circuits |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Christoph W. Kessler, Andrzej Bednarski, Mattias V. Eriksson |
Classification and generation of schedules for VLIW processors. |
Concurr. Comput. Pract. Exp. |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee |
PALF: compiler supports for irregular register files in clustered VLIW DSP processors. |
Concurr. Comput. Pract. Exp. |
2007 |
DBLP DOI BibTeX RDF |
|
16 | |
Real-time Face Recognition Using SIMD and VLIW Architecture. |
J. Comput. Inf. Technol. |
2007 |
DBLP DOI BibTeX RDF |
|
16 | José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest |
Energy-aware compilation and hardware design for VLIW embedded systems. |
Int. J. Embed. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Vincenzo Catania, Maurizio Palesi, Davide Patti |
Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario. |
J. Circuits Syst. Comput. |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Muhammad Sohail Sadiq, Shoab Ahmed Khan |
Optimal Mapping of DSP Algorithms on Commercially Available Off-The-Shelf (COTS) VLIW DSPs. |
IEEE Trans. Consumer Electron. |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Pawel Pawlowski, Adam Dabrowski, Mario Schölzel |
Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy Arithmetic. |
DDECS |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Jos Huisken |
Integrating VLIW Processors with a Network on Chip. |
SAMOS |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner |
A Customizable LEON2-Based VLIW Processor. |
ReCoSoC |
2007 |
DBLP BibTeX RDF |
|
16 | Min Li 0001, Bruno Bougard, Eduardo Lopez-Estraviz, André Bourdoux, Liesbet Van der Perre, Francky Catthoor |
The Quality-Energy Scalable OFDMA Modulation for Low Power Transmitter and VLIW Processor Based Implementation. |
GLOBECOM |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Amin Farmahini Farahani, Mahmoud Mousavinezhad, Sied Mehdi Fakhraie |
Simulation of Voice Processing Applications through VLIW DSP Architectures. |
ICECS |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Vincent Brost, Fan Yang 0019, Michel Paindavoine |
A modular VLIW Processor. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Ricardo Ribeiro dos Santos |
2D-VLIW: a processor architecture based on the geometry of the computation. |
|
2007 |
RDF |
|
16 | Esther Salamí |
Optimizing VLIW architectures for multimedia applications. |
|
2007 |
RDF |
|
16 | Montserrat Ros |
Code compression optimisation for VLIW processors |
|
2007 |
RDF |
|
16 | Christoph W. Keßler, Andrzej Bednarski |
Optimal integrated code generation for VLIW architectures. |
Concurr. Comput. Pract. Exp. |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Karine Heydemann, François Bodin, Peter M. W. Knijnenburg, Laurent Morin |
UFS: a global trade-off strategy for loop unrolling for VLIW architectures. |
Concurr. Comput. Pract. Exp. |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Enric Gibert, F. Jesús Sánchez, Antonio González 0001 |
Instruction scheduling for a clustered VLIW processor with a word-interleaved cache. |
Concurr. Comput. Pract. Exp. |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Alex K. Jones, Raymond R. Hoare, Dara Kusic, Justin Stander, Gayatri Mehta, Joshua Fazekas |
A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power. |
IEEE Trans. Circuits Syst. II Express Briefs |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Raymond R. Hoare, Alex K. Jones, Dara Kusic, Joshua Fazekas, John Foster 0001, Shen Chih Tung, Michael L. McCloud |
Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions. |
EURASIP J. Adv. Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest |
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl |
Datapath and ISA Customization for Soft VLIW Processors. |
ReConFig |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti |
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. |
IEEE Congress on Evolutionary Computation |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Rahul Nagpal, Y. N. Srikant |
Exploring Energy-Performance Trade-Offs for Heterogeneous Interconnect Clustered VLIW Processors. |
HiPC |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga |
Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Andy Heinig, Mario Schölzel |
Zeitbeschränkte Clusterung zur Design-Space-Exploration geclusterter VLIW-Prozessoren. |
MBMV |
2006 |
DBLP BibTeX RDF |
|
16 | Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim |
A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications. |
ISSCC |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Sourav Roy, Rajat Bhatia, Ashish Mathur |
An accurate Energy estimation framework for VLIW Processor Cores. |
ICCD |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Zhou Zhixiong, Yang Xu, He Hu 0002, Yihe Sun |
A Retargetable Compiler of VLIW ASIP for Media Signal Processing. |
ESA |
2006 |
DBLP BibTeX RDF |
|
16 | Reza Iraji, Hamid Sarbazi-Azad |
A Probability-Based Instruction Combining Method for Scheduling in VLIW Processors. |
AICCSA |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Giuseppe Desoli, Thierry Strudel, Jean-Philippe Cousin, Kaushik Saha |
Current and future trends in embedded VLIW microprocessors applied to multimedia and signal processing. |
EUSIPCO |
2006 |
DBLP BibTeX RDF |
|
16 | Mario Schölzel |
Automatisierter Entwurf anwendungsspezifischer VLIW-Prozessoren. |
|
2006 |
RDF |
|
16 | Shu Xiao 0001 |
Power-balanced instruction scheduling for pipelined VLIW architectures |
|
2006 |
DOI RDF |
|
16 | Alessandro Scotto |
Architectural exploration technology based on simulation of reconfigurable VLIW processors driven by multimedia applications for HW-SW co-design. |
|
2006 |
RDF |
|
16 | Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon |
Reducing the complexity of instruction-level power models for VLIW processors. |
Des. Autom. Embed. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Steve Haga, Andrew Webber, Yi Zhang, Nghi Nguyen, Rajeev Barua |
Reducing code size in VLIW instruction scheduling. |
J. Embed. Comput. |
2005 |
DBLP BibTeX RDF |
|
16 | Jean-Luc Gaudiot, Jung-Yup Kang, Won Woo Ro |
Techniques to Improve Performance Beyond Pipelining: Superpipelining, Superscalar, and VLIW. |
Adv. Comput. |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon |
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach. |
Integr. |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Kazutoshi Kobayashi, Masao Aramoto, Hidetoshi Onodera |
A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era. |
IEICE Trans. Electron. |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Radu Muresan, Catherine H. Gebotys |
Instantaneous current modeling in a complex VLIW processor core. |
ACM Trans. Embed. Comput. Syst. |
2005 |
DBLP DOI BibTeX RDF |
Instruction-level current model, current and power measurement in a processor, instantaneous current model, power and energy model |
16 | Joseph A. Fisher, Paolo Faraboschi, Cliff Young |
Embedded computing - a VLIW approach to architecture, compilers, and tools. |
|
2005 |
RDF |
|
16 | Stephan Suijkerbuijk, Ben H. H. Juurlink |
Implementing Hardware Multithreading in a VLIW Architecture. |
IASTED PDCS |
2005 |
DBLP BibTeX RDF |
|
16 | Atsushi Tsukikawa, Fumihito Furukawa, Takayuki Aoki, Daisuke Oka, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba |
Design and Implementation of a VLIW Processor Simulation Environment with Instruction Scheduling Framework. |
IASTED PDCS |
2005 |
DBLP BibTeX RDF |
|
16 | Shu Xiao 0001, Edmund Ming-Kit Lai |
A rough programming approach to power-aware VLIW instruction scheduling for digital signal processors. |
ICASSP (5) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Kevin D. Rich, Shankar G. Govindaraju, Robert Shaw, David Dobrikin |
DVGen: a test generator for the transmeta Efficeon VLIW processor. |
HLDVT |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Arun Vijayaraghavan, M. Kannan, R. Seshasayanan |
Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency. |
CDES |
2005 |
DBLP BibTeX RDF |
|
16 | Francesco Menichelli, Mauro Olivieri, Simone Smorfa, Irene Zaccardini |
Software optimization of the JPEG2000 algorithm on a VLIW CPU core for system-on-chip implementation. |
Circuits, Signals, and Systems |
2005 |
DBLP BibTeX RDF |
|
16 | Minyi Guo |
Keynote Address: Energy-Aware Compiler Scheduling for VLIW Embedded Software. |
ICPP Workshops |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Thomas Zeitlhofer, Bernhard Wess |
Integrated assignment of registers and functional units for heterogeneous vliw-architectures. |
SoCC |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Hamed Fatemi, Henk Corporaal, Twan Basten, Richard P. Kleihorst, Pieter P. Jonker |
Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures. |
ACIVS |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Shu Xiao 0001, Edmund Ming-Kit Lai, A. Prasad Vinod 0001 |
VLIW instruction scheduling for DSP processors based on rough set theory. |
ISSPA |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Steve Haga |
VLIW Instruction Scheduling for Reduced Code Size. |
|
2005 |
RDF |
|
16 | Domenico Barretta |
Joint exploitation of ILP and thread level parallelism on multicluster VLIW processors. |
|
2005 |
RDF |
|
16 | Suhyun Kim, Soo-Mook Moon, Kemal Ebcioglu, Erik R. Altman |
VLaTTe: A Java Just-in-Time Compiler for VLIW with Fast Scheduling and Register Allocation. |
IEICE Trans. Inf. Syst. |
2004 |
DBLP BibTeX RDF |
|
16 | Wanli Liu, David H. Albonesi, John Gostomski, Lloyd Palum, Dave Hinterberger, Rick Wanzenried, Mark Indovina |
An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications. |
J. Circuits Syst. Comput. |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Mile K. Stojcev |
Power estimation and optimization for VLIW-based embedded systems; Vittorio Zaccaria, Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano. Hardcover, pp 203, plus XXIV, Kluwer Academic Publishers, Boston, 2003. ISBN 1-4020-7377-1. |
Microelectron. Reliab. |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Jinhwan Kim, Yunheung Paek, Gang-Ryung Uh |
Code optimizations for a VLIW-style network processing unit. |
Softw. Pract. Exp. |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Zili Shao, Qingfeng Zhuge, Youtao Zhang, Edwin Hsing-Mean Sha |
Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors. |
Int. J. High Perform. Comput. Netw. |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero |
High-performance and low-power VLIW cores for numerical computations. |
Int. J. High Perform. Comput. Netw. |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero |
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units. |
SAMOS |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Seokhoon Ju, Wonyong Sung |
Implementation of a digital color copier using a VLIW SIMD architecture. |
ICASSP (5) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Brian Valentine, Oliver P. Sohm |
Optimizing the JPEG2000 binary arithmetic encoder for VLIW architectures. |
ICASSP (5) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Alex K. Jones, Raymond Hoare, Ivan S. Kourtev, Joshua Fazekas, Dara Kusic, John Foster 0001, Sedric Boddie, Ahmed Muaydh |
A 64-way VLIW/SIMD FPGA architecture and design flow. |
ICECS |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Montserrat Ros, Peter Sutton |
Code Compression Based on Operand-Factorization for VLIW Processor. |
Data Compression Conference |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Yu Hu 0016, Qing Li 0001, C.-C. Jay Kuo |
Efficient implementation of elliptic curve cryptography (ECC) on VLIW-micro-architecture media processor. |
ICME |
2004 |
DBLP BibTeX RDF |
|
16 | Andreas Lundgren, Wido Kruijtzer |
A scalable VLIW for smart imaging. |
ESTIMedia |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Johannes Fürtler, Konrad J. Mayer, Werner Krattenthaler, Ivan Bajla |
SPOT - Development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing. |
Real Time Imaging |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Andrea Lodi 0002, Mario Toma, Fabio Campi, Andrea Cappelli, Roberto Canegallo, Roberto Guerrieri |
A VLIW processor with reconfigurable instruction set for embedded applications. |
IEEE J. Solid State Circuits |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda |
A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements. |
IEEE J. Solid State Circuits |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Miroslav N. Velev, Randal E. Bryant |
Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors. |
J. Symb. Comput. |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Satish Pillai, Margarida F. Jacome |
Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines. |
Embedded Software for SoC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Wayne H. Wolf, I. Burak Özer, Tiehan Lv |
Exploiting parallelism in media processing using VLIW processor. |
ICIP (3) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Enric Gibert, F. Jesús Sánchez, Antonio González 0001 |
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. |
MICRO |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Taeksang Hwang, Wonyong Sung |
Implementation of a digital copier using TMS320C6414 VLIW DSP processor. |
ICASSP (2) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | J. Prakash, C. Sandeep, Priti Shankar, Y. N. Srikant |
A Simple and Fast Scheme for Code Compression for VLIW Processors. |
DCC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Jun Tanahe, Yasuhiro Taniguchi, Takashi Miyamori, Yukimasa Miyamoto, Hideki Takeda, Masaya Tarui, Hiromitsu Nakayama, Nohuyulu Takeda, Kenichi Maeda, Masataka Matsui |
Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications]. |
CICC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero |
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. |
ISHPC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. |
ESTIMedia |
2003 |
DBLP BibTeX RDF |
|
16 | Davide Rizzo, Osvaldo Colavin, Shiva Navab |
A Runtime Reconfigurable Clustered VLIW Architecture for Mediaprocessing. |
ESTIMedia |
2003 |
DBLP BibTeX RDF |
|
16 | G. R. Chaji, R. M. Pourrad, Seid Mehdi Fakhraie, Mohammad H. Tehranipour |
eUTDSP: a design study of a new VLIW-based DSP architecture. |
ISCAS (4) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Sunghyun Jee, Kannappan Palaniappan |
Performance of dynamically scheduling VLIW instructions. |
SoC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Ulrich Hirnschrott, Andreas Krall |
VLIW operation refinement for reducing energy consumption. |
SoC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Massimo Bariani |
Architectural exploration technology based on simulation of VLIW processors driven by multimedia applications for HW-SW co-design of embedded systems. |
|
2003 |
RDF |
|
16 | Luca Benini, Davide Bruni, Mauro Chinosi, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon |
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems. |
Des. Autom. Embed. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Cagdas Akturan, Margarida F. Jacome |
An Effective Software Pipelining Algorithm for Clustered Embedded VLIW Processors. |
Des. Autom. Embed. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Sanjive Agarwala, Timothy Anderson, Anthony M. Hill, M. D. Ales, Raguram Damodaran, Paul Wiley, Steven Mullinnix, J. Leach, Anthony Lell, Michael Gill, Arjun Rajagopal, Abhijeet Chachad, M. Agarwala, John Apostol, Manjeri Krishnan, Duc Bui, Quang An, N. S. Nagaraj, Tod Wolf, T. T. Elappuparackal |
A 600-MHz VLIW DSP. |
IEEE J. Solid State Circuits |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Chris Basoglu, Woobin Lee, John O'Donnell |
The Equator MAP-CA™ DSP: an end-to-end broadband signal processor™ VLIW. |
IEEE Trans. Circuits Syst. Video Technol. |
2002 |
DBLP DOI BibTeX RDF |
|
16 | K. H. Hong, Woon-Seng Gan, Yong Kim Chong, T. F. Cheong, S. H. Tan |
Rapid prototyping of DSP algorithms on VLIW TMS320C6701 DSP. |
Microprocess. Microsystems |
2002 |
DBLP DOI BibTeX RDF |
|