Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich |
A pseudo-dynamic comparator for error detection in fault tolerant architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 50-55, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Nicholas Tzou, Thomas Moon, Xian Wang 0003, Hyun Woo Choi, Abhijit Chatterjee |
Dual-frequency incoherent subsampling driven test response acquisition of spectrally sparse wideband signals with enhanced time resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 140-145, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | V. Prasanth, Virendra Singh, Rubin A. Parekhji |
Derating based hardware optimizations in soft error tolerant designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 282-287, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ji Hwan (Paul) Chun, Siew Mooi Lim, Shao Chee Ong, Jae Wook Lee, Jacob A. Abraham |
Test of phase interpolators in high speed I/Os using a sliding window search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 134-139, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Dzmitry Maliuk, Nathan Kupp, Yiorgos Makris |
Towards a fully stand-alone analog/RF BIST: A cost-effective implementation of a neural classifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 62-67, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie |
Test generator with preselected toggling for low power built-in self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 1-6, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Baris Arslan, Alex Orailoglu |
Delay test resource allocation and scheduling for multiple frequency domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 114-119, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Panagiota Papavramidou, Michael Nicolaidis |
Test algorithms for ECC-based memory repair in nanotechnologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 228-233, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Wei Zhao 0010, Sreejit Chakravarty, Junxia Ma, Narendra Devta-Prasanna, Fan Yang 0060, Mohammad Tehranipoor |
A novel method for fast identification of peak current during test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 191-196, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu |
A Memory Failure Pattern Analyzer for memory diagnosis and repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 234-239, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Irith Pomeranz |
Static test compaction for transition faults under the hazard-based detection conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 176-181, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Patricia S. Lee, Ian G. Harris |
Test generation for subtractive specification errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 258-263, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Sreejit Chakravarty, Narendra Devta-Prasanna, Arun Gunda, Junxia Ma, Fan Yang 0060, H. Guo, R. Lai, D. Li |
Silicon evaluation of faster than at-speed transition delay tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 80-85, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Wen Yueh, Subho Chatterjee, Amit Ranjan Trivedi, Saibal Mukhopadhyay |
On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 264-269, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Michel Renovell, Vincent Kerzerho, Olivier Potin, Christophe Kelma |
Smart selection of indirect parameters for DC-based alternate RF IC testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 19-24, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Afsaneh Nassery, Srinath Byregowda, Sule Ozev, Marian Verhelst, Mustapha Slamani |
Built-in-Self Test of transmitter I/Q mismatch using self-mixing envelope detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 56-61, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, Valeria Bertacco |
Comprehensive online defect diagnosis in on-chip networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 44-49, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
Are advanced DfT structures sufficient for preventing scan-attacks? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 246-251, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Nourredine Akkouche, Salvador Mir, Emmanuel Simeu, Mustapha Slamani |
Analog/RF test ordering in the early stages of production testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 25-30, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Michihiro Shintani, Takashi Sato |
A Bayesian-based process parameter estimation using IDDQ current signature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 86-91, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Xi Qian, Chao Han, Adit D. Singh |
Detection of gate-oxide defects with timing tests at reduced power supply. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 120-126, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Peyman Pouyan, Esteve Amat, Antonio Rubio 0001 |
Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 240-245, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Sushmita Kadiyala Rao, Chaitra Sathyanarayana, Ajay Kallianpur, Ryan W. Robucci, Chintan Patel |
Estimating Power Supply Noise and its impact on path delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 276-281, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Yang Zhao, Lisa Grenier, Amitava Majumdar 0002 |
Power Characterization of Embedded SRAMs for Power Binning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 203-208, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu |
Cost modeling and analysis for interposer-based three-dimensional IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 108-113, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel |
Advanced test methods for SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 300-301, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, Ding-Ming Kwai |
A SAR ADC missing-decision level detection and removal technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 31-36, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Peter Wohl, John A. Waicukauski, Jonathon E. Colburn |
Enhancing testability by structured partial scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 152-157, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Francisco J. Galarza-Medina, Jose Luis Garcia-Gervacio, Víctor H. Champac, Alex Orailoglu |
Small-delay defects detection under process variation using Inter-Path Correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 127-132, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Yong-Xiao Chen, Yu-Jen Huang, Jin-Fu Li 0001 |
Test cost optimization technique for the pre-bond test of 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 102-107, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Amit Ranjan Trivedi, Saibal Mukhopadhyay |
Self-adaptive power gating with test circuit for on-line characterization of energy inflection activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 38-43, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | |
30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012 ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![IEEE Computer Society, 978-1-4673-1074-1 The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
1 | Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram |
A SMT-based diagnostic test generation method for combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 215-220, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Shreepad Panth, Sung Kyu Lim |
Transition delay fault testing of 3D ICs with IR-drop study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 270-275, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Onnik Yaglioglu, Ben Eldridge |
Direct connection and testing of TSV and microbump devices using NanoPierce™ contactor for 3D-IC integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 96-101, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Mayur Bubna, Kaushik Roy 0001, Ashish Goel |
HBIST: An approach towards zero external test cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 13-18, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Suraj Sindia, Vishwani D. Agrawal |
Towards spatial fault resilience in array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 288-293, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Thomas Moon, Nicholas Tzou, Xian Wang 0003, Hyun Woo Choi, Abhijit Chatterjee |
Low-cost high-speed pseudo-random bit sequence characterization using nonuniform periodic sampling in the presence of noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, pp. 146-151, 2012, IEEE Computer Society, 978-1-4673-1074-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Prakash Narayanan, Rajesh Mittal, Sumanth Poddutur, Vivek Singhal, Puneet Sabbarwal |
Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 154-159, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Yasuhiro Takahashi, Akinori Maeda |
Multi Domain Test: Novel test strategy to reduce the Cost of Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 303-308, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Baosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick |
Structural tests of slave clock gating in low-power flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 254-259, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | |
29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![IEEE Computer Society, 978-1-61284-657-6 The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
1 | Yu-Jen Huang, Jin-Fu Li 0001, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 20-25, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Suriyaprakash Natarajan, Arani Sinha |
The buck stops with wafer test: Dream or reality? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 111, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Eshan Singh |
Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 32-37, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Mohammad Hossein Neishaburi, Zeljko Zilic |
A distributed AXI-based platform for post-silicon validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 8-13, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh Karri |
Design and analysis of ring oscillator based Design-for-Trust technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 105-110, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Kanad Basu, Prabhat Mishra 0001 |
Efficient trace data compression using statically selected dictionary. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 14-19, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Siddharth Garg, Diana Marculescu |
Special session 4A: New topics parametric yield and reliability of 3D integrated circuits: New challenges and solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 99, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu |
Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 219-224, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | LeRoy Winemberg, Mohammad Tehranipoor |
Special session: Hot topic: Smart silicon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 323, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Dongsoo Lee, Sang Phill Park, Ashish Goel, Kaushik Roy 0001 |
Memory-based embedded digital ATE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 266-271, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ke Peng, Fang Bao, Geoff Shofner, LeRoy Winemberg, Mohammad Tehranipoor |
Case Study: Efficient SDD test generation for very large integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 78-83, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Julien Guilhemsang, Olivier Héron, Nicolas Ventroux, Olivier Goncalves, Alain Giulieri |
Impact of the application activity on intermittent faults in embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 191-196, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Srinivasulu Alampally, R. T. Venkatesh, Priyadharshini Shanmugasundaram, Rubin A. Parekhji, Vishwani D. Agrawal |
An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 285-290, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Cheng-Wen Wu |
Special session: Hot topic design and test of 3D and emerging memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 328, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Arani Sinha, Suriyaprakash Natarajan |
The bang for the buck with resiliency: Yield or field? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 152, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jeffrey F. Wheeldon |
Calibrated high-efficiency testing and modelling methodologies for concentrated multi-junction solar cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 209, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Nader Alawadhi, Ozgur Sinanoglu |
Revival of partial scan: Test cube analysis driven conversion of flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 260-265, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Michail Maniatakos, Yiorgos Makris, Prabhakar Kudva, Bruce M. Fleischer |
Exponent monitoring for low-cost concurrent error detection in FPU control logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 235-240, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ender Yilmaz, Anne Meixner, Sule Ozev |
An industrial case study of analog fault modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 178-183, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Junxia Ma, Nisar Ahmed, Mohammad Tehranipoor |
Low-cost diagnostic pattern generation and evaluation procedures for noise-related failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 309-314, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Zhongwei Jiang, Zheng Wang, Jing Wang 0006, D. M. H. Walker |
Levelized low cost delay test compaction considering IR-drop induced power supply noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 52-57, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Suraj Sindia, Vishwani D. Agrawal, Virendra Singh |
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 64-69, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Rajamani Sethuram, Karim Arabi, Mohamed H. Abu-Rahma |
Leakage power profiling and leakage power reduction using DFT hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 46-51, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux |
Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 229-234, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar 0002, LeRoy Winemberg |
Special session 5B: Panel How much toggle activity should we be testing with? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 114, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard 0001, Mohammad Tehranipoor |
Power-aware test generation with guaranteed launch safety for at-speed scan testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 166-171, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Kurt Rosenfeld, Ramesh Karri |
Security-aware SoC test access mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 100-104, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Samah Mohamed Saeed, Ozgur Sinanoglu |
Expedited response compaction for scan power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 40-45, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Saghir Shaikh |
Test and characterization of high-speed circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 38, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Anne Gattiker |
Invited paper: Yin and Yang of embedded sensors for post-scaling-era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 324-327, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Irith Pomeranz |
On clustering of undetectable transition faults in standard-scan circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 128-133, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | W.-A. Lin, C.-C. Lee, J.-L. Huang |
Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 315-320, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal |
Enhancing online error detection through area-efficient multi-site implications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 241-246, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Kyoung Youn Cho, Rajagopalan Srinivasan |
A scan cell architecture for inter-clock at-speed delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 213-218, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jesús Moreno, Víctor H. Champac, Michel Renovell |
A new methodology for realistic open defect detection probability evaluation under process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 184-189, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Dilip K. Bhavsar |
Harmony Widget for X-free scan testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 225-228, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Shobha Vasudevan |
Coverage closure in SoC verification: Are we chasing a mirage? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 211, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Eun Jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham |
Efficient and product-representative timing model validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 90-95, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Rudrajit Datta, Nur A. Touba |
Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 134-139, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Wei Zhao 0010, Mohammad Tehranipoor, Sreejit Chakravarty |
Power-safe test application using an effective gating approach considering current limits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 160-165, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Celestino V. Martins, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001 |
Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 203-208, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Songwei Pei, Huawei Li 0001, Xiaowei Li 0001 |
A unified test architecture for on-line and off-line delay fault detections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 272-277, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Yasuo Sato |
Special session: Multifaceted approaches for field reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 96, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Irith Pomeranz |
Static test compaction for delay fault test sets consisting of broadside and skewed-load tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 84-89, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ujjwal Guin, Chen-Huan Chiang |
Design for Bit Error Rate estimation of high speed serial links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 278-283, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme |
Programmable extended SEC-DED codes for memory errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 140-145, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Takushi Hashida, Yuuki Araga, Makoto Nagata |
A diagnosis testbench of analog IP cores against on-chip environmental disturbances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 70-75, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Kameshwar Chandrasekar, Surendra Bommu, Sanjay Sengupta |
Low Coverage Analysis using dynamic un-testability debug in ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 291-296, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Seongmoon Wang |
An efficient method to screen resistive opens under presence of process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 122-127, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu |
Training-based forming process for RRAM yield improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 146-151, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Mike Laisne |
Advanced methods for leveraging new test standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 97, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir |
Understanding customer returns from a test perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 2-7, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Amitava Majumdar 0002, Arani Sinha, Nehal Patel, Ramamurthy Setty, Yan Dong, Shu-Hsuan Chou |
A Novel mechanism for speed characterization during delay test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 116-121, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Aritra Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee |
Automatic test stimulus generation for accurate diagnosis of RF systems using transient response signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 58-63, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Kee Sup Kim, Rob Roy |
Apprentice - VTS edition: Season 4. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 113, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Priyadharshini Shanmugasundaram, Vishwani D. Agrawal |
Dynamic scan clock control for test time reduction maintaining peak power limit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 248-253, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Wing Chiu Tam, Ronald D. Blanton |
SLIDER: A fast and accurate defect simulation framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 172-177, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Shreepad Panth, Sung Kyu Lim |
Scan chain and power delivery network synthesis for pre-bond test of 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 26-31, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|