Search results for "low-voltage"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Seong-Ik Cho, Jung-Hwan Lee, Hong-June Park, Gyu-Ho Lim, Young-Hee Kim	Two-phase boosted voltage generator for low-voltage DRAMs.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
16	Lei Wang, Sherif H. K. Embabi	Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
16	Chua-Chin Wang, Ya-Hsin Hsueh, Ting-Wan Kuo, Ron Hu	A boosted wordline voltage generator for low-voltage memories.	ICECS	2003	DBLP DOI BibTeX RDF
16	Saravanan Rajapandian, Zheng Xu 0003, Kenneth L. Shepard	Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
16	Fujihiko Matsumoto, Hiroki Wasaki, Yasuaki Noguchi	Low-Voltage Linear Bipolar OTAs Employing Hyperbolic Circuits with an Intermediate Voltage Terminal.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
16	Jaber A. Abu-Qahouq, Natorn Pongratananukul, Issa Batarseh, Takis Kasparis	DSP controlled low-voltage high-current fast-transient Voltage Regulator Module.	ICASSP	2002	DBLP DOI BibTeX RDF
16	Luis Henrique de Carvalho Ferreira, Robson L. Moreno, Tales C. Pimenta, Carlos A. R. Filho	A precise sample-and-hold circuit topology in CMOS for low voltage applications with offset voltage self correction.	ICECS	2002	DBLP DOI BibTeX RDF
16	Salvatore Pennisi	Using a low-voltage COA for high-performance voltage amplification.	ICECS	2002	DBLP DOI BibTeX RDF
16	A. Bendali, Yvon Savaria	Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
16	Mikko Waltari, Kari Halonen	Reference voltage driver for low-voltage CMOS A/D converters.	ICECS	2000	DBLP DOI BibTeX RDF
16	Hoi Lee, Philip K. T. Mok, Wing-Hung Ki	A novel voltage-control scheme for low-voltage DC-DC converters with fast transient recovery.	ISCAS	2000	DBLP DOI BibTeX RDF
16	Jaime Ramírez-Angulo, Ramón G. Carvajal, Juana M. Martínez-Heredia, Antonio Torralba 0002	Very low-voltage class AB CMOS precision voltage and current rectifiers.	ISCAS	2000	DBLP DOI BibTeX RDF
16	Gajendra P. Singh, Raoul B. Salem	High-voltage-tolerant I/O buffers with low-voltage CMOS process.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
16	Giuseppe Ferri, Franco Alfonsetti, Gian Carlo Cardarilli, Marco Re	Bipolar and CMOS low voltage-supply reduced-power voltage followers.	ICECS	1999	DBLP DOI BibTeX RDF
16	Takayuki Kawahara, Syun-ichi Saeki, Yusuke Jyouno, Naoki Miyamoto, Takashi Kobayashi 0002, Katsutaka Kimura	Internal voltage generator for low voltage, quarter-micrometer flash memories.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
16	Simon Cimin Li, Reggie Chien, Jerry Chien, Kaung-Long Lin	A Simple Architecture of Low Voltage GHz BiCMOS Four-Quadrant Analogue Multiplier using Complementary Voltage Follower.	ASP-DAC	1998	DBLP DOI BibTeX RDF
16	Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi	A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs.	ISLPED	1998	DBLP DOI BibTeX RDF
16	Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki	A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
16	Jaime Ramírez-Angulo	High Slew Rate, Low Voltage BiCMOS and Bipolar Operational Amplifier Architectures with Rail to Rrail Common Mode Input Voltage Swing.	ISCAS	1994	DBLP DOI BibTeX RDF
16	Jaime Ramírez-Angulo, Alejandro Díaz-Sánchez	Low-voltage Programmable FIR Filters Using Voltage Followers and Analog Multipliers.	ISCAS	1993	DBLP BibTeX RDF
15	Francesco Gullo, Giovanni Ponti, Andrea Tagarelli, Salvatore liritano, Massimiliano Ruffolo, Diego Labate	Low-voltage electricity customer profiling based on load data clustering.	IDEAS	2009	DBLP DOI BibTeX RDF
15	Burak Çatli, Mona Mostafa Hella	A 0.5-V 3.6/5.2 GHz CMOS multi-band LC VCO for ultra low-voltage wireless applications.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Daryl Van Vorst, Shahriar Mirabbasi	Low-voltage bulk-driven mixer with on-chip balun.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Fabrice Guigues, Edith Kussener, Benjamin Duval, Hervé Barthélemy	Moderate Inversion: Highlights for Low Voltage Design.	PATMOS	2007	DBLP DOI BibTeX RDF
15	Pedro J. Trujillo Tarazona	Field evaluation of a protocol for data transmission through the distribution lines of the low voltage grid.	EATIS	2007	DBLP DOI BibTeX RDF	PowerBus, automatic meter reading, power line carrier, embedded system, PLC, AMR
15	George Fikos, Lazaros Nalpantidis, Stilianos Siskos	A low-voltage, analog power-law function generator.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Behnam Sedighi, Mehrdad Sharif Bakhtiar	A New Class AB Current-Mode Circuit for Low-Voltage Applications.	APCCAS	2006	DBLP DOI BibTeX RDF
15	Haihua Yan, Adit D. Singh, Gefu Xu	Delay Defect Characterization Using Low Voltage Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
15	Louie Pylarinos, Khoman Phang	Low-voltage programmable gm-C filter for hearing aids using dynamic gate biasing.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
15	Payam Heydari, Ravindran Mohanavelu	Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
15	Guangbin Zhang, Jin Liu 0004, Sungyong Jung	An accurate current source with on-chip self-calibration circuits for low-voltage differential transmitter drivers.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
15	Romero Tavares, Bruno Vaz, João Goes, Nuno F. Paulino, Adolfo Steiger-Garção	Design and optimization of low-voltage two-stage CMOS amplifiers with enhanced performance.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Tsung-Sum Lee, Chi-Chang Lu	A fully differential low-voltage CMOS high-speed track-and-hold circuit.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Jaime Ramírez-Angulo, Ramón González Carvajal, Gladys Omayra Ducoudray	New very compact CMOS continuous-time low-voltage analog rank-order filter architecture.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Jader A. De Lima	An active leakage-injection scheme applied to low-voltage SRAMs.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
15	Yngvar Berg, Snorre Aunet, Øivind Næss, Johannes Goplen Lomsdalen, Mats Høvin	Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	Payam Heydari	Design issues in low-voltage high-speed current-mode logic buffers.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	VLSI, noise, integrated circuit, high-speed, current-mode logic
15	Payam Heydari	Design and Analysis of Low-Voltage Current-Mode Logic Buffers.	ISQED	2003	DBLP DOI BibTeX RDF
15	Eric W. MacDonald, Nur A. Touba	Very Low Voltage Testing of SOI Integrated Circuits.	VTS	2002	DBLP DOI BibTeX RDF
15	Tsung-Sum Lee, Chi-Chang Lu	A low-voltage fully differential CMOS high-speed track-and-hold circuit.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
15	Giuseppe Palmisano, Salvatore Pennisi	Low-voltage continuous-time CMOS current amplifier with dynamic biasing.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
15	Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin	Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
15	Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin	Extreme low-voltage floating-gate CMOS transconductance amplifier.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
15	Tsung-Sum Lee, Jing-Lea Huang	A low-voltage BiCMOS transconductor with improved linearity for VHF transconductance-C filters.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
15	Tuna B. Tarim, H. Hakan Kuntman, Mohammed Ismail 0001	Robust Design of Basic Low Voltage CMOS Transconductors.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
15	G. Xu, Sherif H. K. Embabi, P. Hao, Edgar Sánchez-Sinencio	A low voltage fully differential nested Gm capacitance compensation amplifier: analysis and design.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
15	Akira Hyogo, Y. Fukutomi, Keitaro Sekine	Low voltage four-quadrant analog multiplier using square-root circuit based on CMOS pair.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
15	Fathi A. Farag, Carlos Galup-Montoro, Márcio C. Schneider	A programmable low voltage switched-current FIR filter.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
15	Yngvar Berg, Tor Sverre Lande	Tunable current mirrors for ultra low voltage.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
15	Sergio Callegari, Gianluca Setti	Improved bandwidth, low voltage log domain building blocks.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
15	Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	A Low Energy FFT/IFFT Processor for Hearing Aids.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Jingyu Hu, Mike R. May, Matt D. Felder, Len DiSanza, Lawrence H. Ragan	A Fully Integrated Inductorless Low Noise Amplifier with 1dB-Step Programmable Gain for FM Radio Receiver Front-End.	ISCAS	2007	DBLP DOI BibTeX RDF
15	M. R. Nabavi	A 1-V 12-bit switched-op amp pipelined ADC with power optimization.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Mingoo Seok, David T. Blaauw, Dennis Sylvester	Clock network design for ultra-low power applications.	ISLPED	2010	DBLP DOI BibTeX RDF	ultra-low power, robust design, clock network
15	Haizheng Guo, Robert Sobot	RF power harvesting analog front-end circuit for implants.	CCECE	2009	DBLP DOI BibTeX RDF
15	Mohamed H. Abu-Rahma, Mohab Anis	A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
15	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.	SoCC	2008	DBLP DOI BibTeX RDF
15	Alfredo Olmos, Andre Vilas Boas, Jefferson Soldera	A Sub-1V Low Power Temperature Compensated Current Reference.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Cosmin Popa	Linearized CMOS active resistor independent on the bulk effect.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	CMOS design, active resistor, linearity, area minimization
15	Hong-Yi Huang, Chia-Ming Liang, Wei-Ming Chiu	1-99% input duty 50% output duty cycle corrector.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Srikanth Sundaram, Praveen Elakkumanan, Ramalingam Sridhar	High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach.	VLSI Design	2006	DBLP DOI BibTeX RDF
15	Jun-Da Chen, Zhi-Ming Lin	2.4 GHz High IIP3 and Low-Noise Down-conversion Mixer.	APCCAS	2006	DBLP DOI BibTeX RDF
15	Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen	Memory Testing Under Different Stress Conditions: An Industrial Evaluation.	DATE	2005	DBLP DOI BibTeX RDF
15	Chi Yat Leung, Ka Nang Leung, Philip K. T. Mok	Design of a 1.5-V high-order curvature-compensated CMOS bandgap reference.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
15	Chih-Lung Hsiao, Ro-Min Weng, Kun-Yi Lin	A 1V fully differential CMOS LNA for 2.4GHz application.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
15	José Pineda de Gyvez, Rosa Rodríguez-Montañés	Threshold Voltage Mismatch (DeltaVT) Fault Modeling.	VTS	2003	DBLP DOI BibTeX RDF
15	Wang-Chi Cheng, Cheong-Fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun	A 1.2 V 900 MHz CMOS mixer.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
15	Wang-Chi Cheng, Cheong-Fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun	A 900 MHz 1.2 V CMOS mixer with high linearity.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
15	Spiridon Vlassis, George Fikos, Stilianos Siskos	A floating gate CMOS Euclidean distance calculator and its application to hand-written digit recognition.	ICIP (3)	2001	DBLP DOI BibTeX RDF
15	Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal	Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
15	John Poulton	An Embedded DRAM for CMOS ASICs.	ARVLSI	1997	DBLP DOI BibTeX RDF
14	Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto	High performance current-mode differential logic.	ASP-DAC	2008	DBLP DOI BibTeX RDF
14	Magnus Wiklund, Stefan Nilsson, Christian Bjork, Sven Mattisson	A 2GHz image-reject receiver in a low IF architecture fabricated in a 0.1µm CMOS technology.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
14	Zhiguo Ge, Tulika Mitra, Weng-Fai Wong	A DVS-based pipelined reconfigurable instruction memory.	DAC	2009	DBLP DOI BibTeX RDF	reconfigurable memory, low power, instruction cache
14	Wayne H. Cheng, Bevan M. Baas	Dynamic voltage and frequency scaling circuits with two supply voltages.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Xiaoxi He, Leiting Chen	Path Planning Based on Grid-Potential Fields.	CSSE (2)	2008	DBLP DOI BibTeX RDF
14	Matthew Seetharam A. Holtz, Seetharam Narasimhan, Swarup Bhunia	On-die CMOS voltage droop detection and dynamiccompensation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	di/dt voltage droop, on-die voltage droop compensation, power supply droop, predictive current injection
14	David Roberts, Nam Sung Kim, Trevor N. Mudge	On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology.	DSD	2007	DBLP DOI BibTeX RDF
14	Behnam Amelifard, Massoud Pedram	Design of an efficient power delivery network in an soc to enable dynamic power management.	ISLPED	2007	DBLP DOI BibTeX RDF	power delivery network, voltage regulator, low-power design, DC-DC converter
14	Behnam Amelifard, Massoud Pedram	Optimal Selection of Voltage Regulator Modules in a Power Delivery Network.	DAC	2007	DBLP DOI BibTeX RDF
14	Ilya Obridko, Ran Ginosar	Minimal Energy Asynchronous Dynamic Adders.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
14	P. Naktongkul, Apinunt Thanachayanont	1.5-V 900-µW 40-dB CMOS variable gain amplifier.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Wang-Chi Cheng, Cheong-Fat Chan, Kong-Pang Pun, Oliver Chiu-sing Choy	0.8 V GPS band CMOS VCO with 29% Tuning Range.	APCCAS	2006	DBLP DOI BibTeX RDF
14	Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Kuo-Feng Yu, Tong-Chern Ong	A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
14	R. Arona, Edoardo Bonizzoni, Franco Maloberti, Guido Torelli	Heap charge pump optimisation by a tapered architecture.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
14	Vishal Gupta 0003, Gabriel A. Rincón-Mora	Predicting and Designing for the Impact of Process Variations and Mismatch on the Trim Range and Yield of Bandgap References.	ISQED	2005	DBLP DOI BibTeX RDF
14	Lianxi Liu, Yintang Yang, Zhangming Zhu	A High Accuracy Bandgap Reference with Chopped Modulator to Compensate MOSFET Mismatch.	VLSI Design	2005	DBLP DOI BibTeX RDF
14	Amitabh Menon, S. K. Nandy 0001, Mahesh Mehendale	Multivoltage scheduling with voltage-partitioned variable storage.	ISLPED	2003	DBLP DOI BibTeX RDF	multivoltage, high level synthesis, datapath synthesis
14	Vijay Raghunathan, Mani B. Srivastava, Rajesh K. Gupta 0001	A survey of techniques for energy efficient on-chip communication.	DAC	2003	DBLP DOI BibTeX RDF	low power design, power management, communication architectures, system-on-chip design, energy efficient design
14	Kiyoo Itoh 0001	Trends in Ultralow-Voltage RAM Technology.	PATMOS	2002	DBLP DOI BibTeX RDF
14	Douglas A. Wiegmann, Aaron M. Rich, Thomas J. Overbye, Yan Sun	Human Factors Aspects of Power System Voltage Visualizations.	HICSS	2002	DBLP DOI BibTeX RDF	power system visualization, human factors
14	Fernando Muñoz 0001, Alfredo Pérez Vega-Leal, Ramón González Carvajal, Antonio Jesús Torralba Silgado, Jonathan Noel Tombs, Jaime Ramírez-Angulo	A 1.1 V low-power Sigma-Delta modulator for 14-b 16 kHz A/D conversion.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
14	Chih-Chun Tang, Wen-Shih Lu, Lan-Da Van, Wu-Shiung Feng	A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
14	Apinunt Thanachayanont	A 1.5-V CMOS fully differential inductorless RF bandpass amplifier.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
14	Chao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh	MINVDD Testing for Weak CMOS ICs.	VTS	2001	DBLP DOI BibTeX RDF
14	Sanjeev Kumar Maheshwari, G. S. Visweswaran	A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O Buffer.	VLSI Design	2000	DBLP DOI BibTeX RDF
14	Alberto Nannarelli, Tomás Lang	Low-Power Divider.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Floating-point division, low-power, digit-recurrence division
13	Lucas Compassi Severo, Tailize C. De-Oliveira, Paulo César Comassetto de Aguirre, Wilhelmus A. M. Van Noije, Alessandro Gonçalves Girardi	Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
13	Parthiv Bhau, Vijay Savani	Design and Analysis of Low-Voltage and Low-Power 19T FinFET-TGDI-Based Hybrid Full Adders.	J. Circuits Syst. Comput.	2024	DBLP DOI BibTeX RDF
13	Ramon H. Vieira, Tawan Chrysther dos Santos, Renan D. P. de Oliveira, Alessandro Gonçalves Girardi, Lucas C. Severo, Paulo César Comassetto de Aguirre	A Low-Voltage Low-Power 20-Msps 3-Bit Rail-to-Rail Flash ADC.	LASCAS	2024	DBLP DOI BibTeX RDF