Search results for "processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa	An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture.	EUC	2005	DBLP DOI BibTeX RDF
18	Alireza Hodjat, David Hwang 0001, Ingrid Verbauwhede	A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks.	ITCC (1)	2005	DBLP DOI BibTeX RDF	security, Elliptic Curve Cryptography, side-channel attacks, Galois fields, hardware architecture
18	Oscar del Rio Herrero, X. Maufroid	Innovative hybrid optical/digital ultra-fast packet-switched processor for meshed satellite networks.	IEEE J. Sel. Areas Commun.	2004	DBLP DOI BibTeX RDF
18	Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis	The Virtex II ProTM MOLEN Processor.	SAMOS	2004	DBLP DOI BibTeX RDF
18	Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera	An SoC architecture and its design methodology using unifunctional heterogeneous processor array.	ASP-DAC	2004	DBLP DOI BibTeX RDF
18	Mikio Hashimoto, Hiroyoshi Haruki, Takeshi Kawabata	Secure Processor Consistent with Both Foreign Software Protection and User Privacy Protection.	Security Protocols Workshop	2004	DBLP DOI BibTeX RDF
18	Mikio Hashimoto	Secure Processor Consistent with Both Foreign Software Protection and User Privacy Protection (Transcript of Discussion).	Security Protocols Workshop	2004	DBLP DOI BibTeX RDF
18	Steve Carr 0001, Philip H. Sweany	Automatic data partitioning for the agere payload plus network processor.	CASES	2004	DBLP DOI BibTeX RDF	scheduling, partitioning, network processors
18	Long Bu, John A. Chandy	A keyword match processor architecture using content addressable memory.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	keyword matching, text search hardware
18	Mok Pak Lun, Anthony S. Fong, Gary K. W. Hau	Object-oriented processor requirements with instruction analysis of Java programs.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF
18	Frederik Vermeulen, Francky Catthoor, Lode Nachtergaele, Diederik Verkest, Hugo De Man	Power-efficient flexible processor architecture for embedded applications.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
18	Nathan Tuck, Dean M. Tullsen	Initial Observations of the Simultaneous Multithreading Pentium 4 Processor.	IEEE PACT	2003	DBLP DOI BibTeX RDF
18	Mok Pak Lun, Anthony S. Fong, Gary K. W. Hau	Object-oriented processor requirements with instruction analysis of Java programs.	ISICT	2003	DBLP BibTeX RDF
18	Clinton Kelly IV, Virantha N. Ekanayake, Rajit Manohar	SNAP: A Sensor-Network Asynchronous Processor.	ASYNC	2003	DBLP DOI BibTeX RDF
18	Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal	Low Power Coarse-Grained Reconfigurable Instruction Set Processor.	FPL	2003	DBLP DOI BibTeX RDF
18	Eryk Laskowski, Marek Tudruj	Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches.	FPL	2003	DBLP DOI BibTeX RDF
18	Young-Ki Ko, Eui Kyeong Hong, Myung Kim	An XPATH Query Processor for a Decomposition Storage Scheme.	Human.Society@Internet 2003	2003	DBLP DOI BibTeX RDF
18	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A Scalable Application-Specific Processor Synthesis Methodology.	ICCAD	2003	DBLP DOI BibTeX RDF
18	Jen-Chih Kuo, Ching-Hua Wen, An-Yeu Wu	Implementation of a programmable 64~2048-point FFT/IFFT processor for OFDM-based communication systems.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
18	Hans Eberle, Nils Gura, Sheueling Chang Shantz	A Cryptograhpic Processor for Arbitrary Elliptic Curves over.	ASAP	2003	DBLP DOI BibTeX RDF
18	Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores.	ITC	2003	DBLP DOI BibTeX RDF
18	Philip Heng Wai Leong, Ivan K. H. Leung	A microcoded elliptic curve processor using FPGA technology.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
18	Abhijit Jas, Nur A. Touba	Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	test data compression, system-on-chip testing, deterministic testing
18	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor.	MICRO	2002	DBLP DOI BibTeX RDF
18	G. D. Nagendra, V. G. Prem Kumar, B. S. Sheshadri Chakravarthy	Simulation bridge: a framework for multi-processor simulation.	CODES	2002	DBLP DOI BibTeX RDF	simulation framework, instruction set simulator, multiprocessor simulation
18	Marek Tudruj, Lukasz Masko	Program Execution Control for Communication on the Fly in Dynamic Shared Memory Processor Clusters.	PARELEC	2002	DBLP DOI BibTeX RDF
18	Lori Carter, Weihaw Chuang, Brad Calder	An EPIC Processor with Pending Functional Units.	ISHPC	2002	DBLP DOI BibTeX RDF
18	Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim	Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip.	ASAP	2002	DBLP DOI BibTeX RDF
18	Kedarnath J. Balakrishnan, Nur A. Touba	Matrix-Based Test Vector Decompression Using an Embedded Processor.	DFT	2002	DBLP DOI BibTeX RDF
18	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Instruction-Based Self-Testing of Processor Cores.	VTS	2002	DBLP DOI BibTeX RDF
18	Eric Sprangle, Doug Carmean	Increasing Processor Performance by Implementing Deeper Pipelines.	ISCA	2002	DBLP DOI BibTeX RDF	Pipeline depth, Pipeline
18	Li Chen, Sujit Dey	Software-based self-testing methodology for processor cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
18	Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki	IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements.	ICIP (3)	2001	DBLP DOI BibTeX RDF
18	Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana	The MOLEN rho-mu-Coded Processor.	FPL	2001	DBLP DOI BibTeX RDF
18	César A. F. De Rose, Hans-Ulrich Heiss	Dynamic Processor Allocation in Large Mesh-Connected Multicomputers.	Euro-Par	2001	DBLP DOI BibTeX RDF
18	Thomas Rauber, Robert Reilein, Gudula Rünger	Orthogonal Processor Groups for Message-Passing Programs.	HPCN	2001	DBLP DOI BibTeX RDF
18	Marek Tudruj	Embedded Cluster Computing through Dynamic Reconfigurability of Inter-Processor Connections.	IWCC	2001	DBLP DOI BibTeX RDF
18	K. A. Jung, Y. S. Lee, H. S. Yang, W. S. Yang, J. H. Kim, S. H. Lee, B. H. Kang	An integrated H.263 video CODEC with protocol processor.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
18	Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busá	Synthesizing A Long Latency Unit Within Vliw Processor.	VLSI Design	2001	DBLP DOI BibTeX RDF
18	Buthayna Eilouti, Emanuel-George Vakalo	A Language-Based Framework for a Form Processor.	IV	2000	DBLP DOI BibTeX RDF	Form Visualization, Architectural Graphics, Geometric Modeling, Form Processing
18	Subhash Chandra, Rajat Moona	Retargetable Functional Simulator Using High Level Processor Models.	VLSI Design	2000	DBLP DOI BibTeX RDF
18	Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng	Embedded hardware and software self-testing methodologies for processor cores.	DAC	2000	DBLP DOI BibTeX RDF
18	Ralf Hartmut Güting, Stefan Dieker, Claudia Freundorfer, Ludger Becker, Holger Schenk	SECONDO/QP: Implementation of a Generic Query Processor.	DEXA	1999	DBLP DOI BibTeX RDF
18	Martin S. Schmookler, Ramesh C. Agarwal, Fred G. Gustavson	Series Approximation Methods for Divide and Square Root in the Power3(TM) Processor.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
18	Guoqing Zhang, Michael Talley, Wael M. Badawy, Michael Weeks, Magdy A. Bayoumi	A low power prototype for a 3D discrete wavelet transform processor.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
18	Shen-Fu Hsiao	A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
18	Ken Batcher, Christos A. Papachristou	Instruction Randomization Self Test For Processor Cores.	VTS	1999	DBLP DOI BibTeX RDF
18	Chun-Mok Chung, Shin-Dug Kim	A Dualthreaded Java Processor for Java Multithreading.	ICPADS	1998	DBLP DOI BibTeX RDF
18	Jacob R. Lorch, Alan Jay Smith	Scheduling techniques for reducing processor energy use in MacOS.	Wirel. Networks	1997	DBLP DOI BibTeX RDF
18	Sundararajan Sriram, Edward A. Lee	Determining the Order of Processor Transactions in Statically Scheduled Multiprocessors.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
18	Rainer Leupers, Peter Marwedel	Retargetable generation of code selectors from HDL processor models.	ED&TC	1997	DBLP DOI BibTeX RDF
18	Sherry Moore, Lionel M. Ni	The Effects of Network Contention on Processor Allocation Strategies.	IPPS	1996	DBLP DOI BibTeX RDF
18	Steve Fu	Memory Hierarchy Synthesis of a Multimedia Embedded Processor.	ICCD	1996	DBLP DOI BibTeX RDF
18	Chih-Ming Chang, Shih-Lien Lu	Design of a static MIMD data flow processor using micropipelines.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
18	Andreas Jakoby, Rüdiger Reischuk	Data Transmission in Processor Networks.	WDAG	1995	DBLP DOI BibTeX RDF
18	Arthur Abnous, Nader Bagherzadeh	Pipelining and Bypassing in a VLIW Processor.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	VLIWprocessor, very long instruction word, pipeline data hazards, performance evaluation, performance, parallel architectures, computer architecture, pipeline processing, pipeline structure, bypassing
18	Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi	DCT/IDCT processor for HDTV developed with dsp silicon compiler.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
18	Jacqueline Chame, Michel Dubois 0001	Cache Inclusion and Processor Sampling in Multiprocessor Simulations.	SIGMETRICS	1993	DBLP DOI BibTeX RDF
18	P. J. Narayanan	Processor Autonomy on SIMD Architectures.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF
18	Jürgen Teich, Lothar Thiele	Control generation in the design of processor arrays.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
18	Jim Weigang	The User Command Processor.	APL	1991	DBLP DOI BibTeX RDF	APL
18	Margaret L. Simmons, Harvey J. Wasserman	Performance evaluation of the IBM RISC System/6000: comparison of an optimized scalar processor with two vector processors.	SC	1990	DBLP DOI BibTeX RDF	RISC
18	Mark R. Thistle, Burton J. Smith	A processor architecture for horizon.	SC	1988	DBLP DOI BibTeX RDF
18	Won Kim 0001, Daniel Gajski, David J. Kuck	A Parallel Pipelined Relational Query Processor.	ACM Trans. Database Syst.	1984	DBLP DOI BibTeX RDF
18	George H. Goble, Michael H. Marsh	A dual processor VAX 11/780.	ISCA	1982	DBLP BibTeX RDF	UNIX, VAX
18	Gilles Berger-Sabbatel, Philippe Olivier Alexandre Navaux	Data Base Processor MAGE.	Computer Architecture for Non-Numeric Processing	1980	DBLP DOI BibTeX RDF
18	Somnath Paul, Swarup Bhunia	VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.	ISLPED	2010	DBLP DOI BibTeX RDF	narrow-width operand, superscalar processor, within-die variation
18	Hoseok Chang, Junho Cho, Wonyong Sung	Compiler-Based Performance Evaluation of an SIMD Processor with a Multi-Bank Memory Unit.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Multi-bank memory, Vectorizing compiler, Data allocation, On-chip memory, SIMD processor
18	Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest	Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC)
18	Nicholas Lowell	Model-based software design tools for the cell processor.	ACM Southeast Regional Conference	2009	DBLP DOI BibTeX RDF	run-time kernel, system dataflow modeling, code generation, automatic target recognition, cell processor
18	Yadan Deng, Ning Jing, Wei Xiong 0010, Chen Luo, Hongsheng Chen	Hash Join Optimization Based on Shared Cache Chip Multi-processor.	DASFAA	2009	DBLP DOI BibTeX RDF	Radix-Join, Shared L2-Cache, Chip Multi-Processor, Cache Conflict
18	Daniele Paolo Scarpazza, Gregory F. Russell	High-performance regular expression scanning on the Cell/B.E. processor.	ICS	2009	DBLP DOI BibTeX RDF	multi-core, regular expressions, cell processor
18	Slo-Li Chu, Chih-Chieh Hsiao, Pin-Hua Chiu	Design a Hardware Mechanism to Utilize Multiprocessors on a Uni-processor Operating System.	ICA3PP	2009	DBLP DOI BibTeX RDF	Xilinx ML310, FPGA, Linux, Multi-core, Inter-Processor Communication
18	Masa-Aki Fukase, Atsuko Yokoyama, Tomoaki Sato	A ubiquitous processor embedded with progressive cipher pipelines.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	hardware cryptography, random number addressing, single chip processor, pipeline, ubiquitous
18	Jie Tao 0001, Marcel Kunze, Fabian Nowak, Rainer Buchty, Wolfgang Karl	Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Simulation, Reconfigurable architecture, Multicore processor, Cache performance
18	Michael A. Bender, David P. Bunde, Erik D. Demaine, Sándor P. Fekete, Vitus J. Leung, Henk Meijer, Cynthia A. Phillips	Communication-Aware Processor Allocation for Supercomputers: Finding Point Sets of Small Average Distance.	Algorithmica	2008	DBLP DOI BibTeX RDF	Manhattan distance, Clustering, Approximation, Supercomputers, Communication cost, Processor allocation, Polynomial-time approximation scheme (PTAS)
18	Hiroaki Inoue, Junji Sakai, Masato Edahiro	Processor virtualization for secure mobile terminals.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	processor virtualization, Multiprocessor
18	Jae Hyun Baek, Sung Dae Kim, Myung Hoon Sunwoo	SPOCS: Application Specific Signal Processor for OFDM Communication Systems.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	ASSP, Communications, FFT, DSP, OFDM, Application-Specific Instruction-Set Processor (ASIP), Bit manipulation
18	Xiaolong Jin, Geyong Min	Performance modelling of generalized processor sharing systems with multiple self-similar traffic flows.	Telecommun. Syst.	2008	DBLP DOI BibTeX RDF	Flow decomposition, Performance modelling, Self-similarity, Generalized Processor Sharing (GPS)
18	Julien Bernard 0001, Jean-Louis Roch, Daouda Traoré	Processor-Oblivious Parallel Stream Computations.	PDP	2008	DBLP DOI BibTeX RDF	processor-oblivious parallel stream work-stealing
18	Vaibhav Saxena, Prashant Agrawal, Yogish Sabharwal, Vijay K. Garg, Vimitha A. Kuruvilla, John A. Gunnels	Optimization of BLAS on the Cell Processor.	HiPC	2008	DBLP DOI BibTeX RDF	Direct Memory Access (DMA), multi-core, linear algebra, BLAS, Cell processor
18	Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, Nader Bagherzadeh	A Generic Network Interface Architecture for a Networked Processor Array (NePA).	ARCS	2008	DBLP DOI BibTeX RDF	Networked Processor Array (NePA), Multiprocessor System-on-Chip (MPSoC), Interconnection Network, Network Interface, Network-on-Chip (NoC)
18	Hyun Min Choi, Chun Pyo Hong, Chang Hoon Kim	High Performance Elliptic Curve Cryptographic Processor Over GF(2^163).	DELTA	2008	DBLP DOI BibTeX RDF	Cryptographic Processor, VLSI, Finite Field, Elliptic Curve Cryptosystem, Gaussian Normal Basis
18	Tao Liu 0033, Depei Qian, Yongxiang Huang, Rui Wang 0014	An Architecture for Distributed Controllable Networks and Manageable Node Based on Network Processor.	APWeb	2008	DBLP DOI BibTeX RDF	Network Processor, Distributed Network Management
18	Kai Shen, Alex Zhang, Terence Kelly, Christopher Stewart	Operational analysis of processor speed scaling.	SPAA	2008	DBLP DOI BibTeX RDF	acpi, datacenter-on-chip, p-states, scheduling, performance modeling, power, multicore, capacity planning, queuing, dynamic resource allocation, multi-processor, operational analysis, internet servers
18	Tse-Yu Yeh	Low-Power, High-Performance Architecture of the PWRficient Processor Family.	IEEE Micro	2007	DBLP DOI BibTeX RDF	coherent memory system, low power, computer architecture, chip multiprocessor, high-performance, processor
18	Regina Egorova, Bert Zwart	Tail behavior of conditional sojourn times in Processor-Sharing queues.	Queueing Syst. Theory Appl.	2007	DBLP DOI BibTeX RDF	Exponential asymptotics, Tail behavior, Laplace-Stieltjes transforms, Random sums, Processor Sharing, Sojourn time, Branching processes, M/G/1 queue
18	Samuel Williams 0001, John Shalf, Leonid Oliker, Shoaib Kamil 0001, Parry Husbands, Katherine A. Yelick	Scientific Computing Kernels on the Cell Processor.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	GEMM, SpMV, three level memory, FFT, sparse matrix, Cell processor, Stencil
18	Adam Janiak, Tomasz Krysiak	Single processor scheduling with job values depending on their completion times.	J. Sched.	2007	DBLP DOI BibTeX RDF	Single processor, Job value, Heuristic, NP-hardness, Polynomial time
18	Jingui Huang, Jianer Chen, Songqiao Chen, Jianxin Wang 0001	A simple linear time approximation algorithm for multi-processor job scheduling on four processors.	J. Comb. Optim.	2007	DBLP DOI BibTeX RDF	Multi-processor job scheduling, Approximation algorithm, NP-hard problem
18	Yiyu Tan, Anthony S. Fong, Xiaojian Yang	An Instruction Folding Solution to a Java Processor.	NPC	2007	DBLP DOI BibTeX RDF	Instruction folding, Java virtual machine, Bytecode, Java processor
18	Viswanathan Subramanian, Mikel Bezdek, Naga Durga Prasad Avirneni, Arun K. Somani	Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning.	DSN	2007	DBLP DOI BibTeX RDF	overclocking, Reliability, Fault-Tolerant Computing, Dynamic, Superscalar processor
18	Thuy Duong Vu, Chris R. Jesshope	Formalizing SANE Virtual Processor in Thread Algebra.	ICFEM	2007	DBLP DOI BibTeX RDF	SANE Virtual Processor, microthreading, thread algebra
18	Xiaolong Jin, Geyong Min	An analytical model for generalized processor sharing scheduling with heterogeneous network traffic.	SAC	2007	DBLP DOI BibTeX RDF	short range dependence, long range dependence, self-similar traffic, generalized processor sharing, large deviation principle
18	Afshin Niktash, Hooman Parizi, Nader Bagherzadeh	A Reconfigurable Processor for Forward Error Correction.	ARCS	2007	DBLP DOI BibTeX RDF	Turbo, Forward Error Correction, Processing Element, Reconfigurable Processor, Viterbi
18	Christopher Ostler, Karam S. Chatha, Goran Konjevod	Approximation Algorithm for Process Mapping on Network Processor Architectures.	ASP-DAC	2007	DBLP DOI BibTeX RDF	Intel IXP2400 architecture, programmable network processor architectures, symmetric multiprocessing, automated system-level design, NP-complete problem, process mapping, polynomial time approximation algorithm, block multithreading
18	Juha Leino 0002	Approximating optimal load balancing policy in discriminatory processor sharing systems.	VALUETOOLS	2007	DBLP DOI BibTeX RDF	discriminatory processor sharing, load balancing, approximation, Markov decision processes, queue length
18	Yong Ki Lee, Ingrid Verbauwhede	A Compact Architecture for Montgomery Elliptic Curve Scalar Multiplication Processor.	WISA	2007	DBLP DOI BibTeX RDF	Compact Elliptic Curve Processor, Montgomery Scalar Multiplication
18	Li Wang 0027, Xuejun Yang, Guibin Wang, Xiaobo Yan, Yu Deng 0001, Jing Du 0002, Ying Zhang 0032, Tao Tang 0001, Kun Zeng	Implementation and Optimization of Sparse Matrix-Vector Multiplication on Imagine Stream Processor.	ISPA	2007	DBLP DOI BibTeX RDF	stream processor, Imagine, Sparse Matrix-Vector Multiplication
18	Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng 0001, Jiang Jiang, Ying Zhang 0032	A 64-bit stream processor architecture for scientific applications.	ISCA	2007	DBLP DOI BibTeX RDF	architecture, compiler, high performance computing, program language, scientific application, stream processor