Search results for "single-event"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Luca Schiano, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli, Adelio Salsano	On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories.	DATE	2005	DBLP DOI BibTeX RDF
5	Balkaran S. Gill, Michael Nicolaidis, Francis G. Wolff, Christos A. Papachristou, Steven L. Garverick	An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories.	DATE	2005	DBLP DOI BibTeX RDF
5	Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes	Techniques for Fast Transient Fault Grading Based on Autonomous Emulation.	DATE	2005	DBLP DOI BibTeX RDF
5	Wonjin Jang, Alain J. Martin	SEU-Tolerant QDI Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
5	Todd M. Austin, Valeria Bertacco, David T. Blaauw, Trevor N. Mudge	Opportunities and challenges for better than worst-case design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
5	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
5	Weikuan Yu, Shuang Liang, Dhabaleswar K. Panda 0001	High performance support of parallel virtual file system (PVFS2) over Quadrics.	ICS	2005	DBLP DOI BibTeX RDF	parallel IO, parallel file system, RDMA, quadrics, zero-copy
5	David de Andrés, José Albaladejo, Lenin Lemus, Pedro J. Gil	Fast Run-Time Reconfiguration for SEU Injection.	EDCC	2005	DBLP DOI BibTeX RDF
5	Mahdi Fazeli, Reza Farivar 0003, Shaahin Hessabi, Seyed Ghassem Miremadi	A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems.	LADC	2005	DBLP DOI BibTeX RDF
5	Michel Pignol	How to Cope with SEU/SET at System Level?.	IOLTS	2005	DBLP DOI BibTeX RDF
5	Andre L. R. Pouponnot	Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessors: Past, Present and Future.	IOLTS	2005	DBLP DOI BibTeX RDF
5	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	Efficient Estimation of SEU Effects in SRAM-Based FPGAs.	IOLTS	2005	DBLP DOI BibTeX RDF
5	Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes	Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading.	IOLTS	2005	DBLP DOI BibTeX RDF
5	Robert C. Aitken, Betina Hold	Modeling Soft-Error Susceptibility for IP Blocks.	IOLTS	2005	DBLP DOI BibTeX RDF
5	Raoul Velazco, R. Ecoffet, F. Faure	How to Characterize the Problem of SEU in Processors and Representative Errors Observed on Flight.	IOLTS	2005	DBLP DOI BibTeX RDF
5	Guillaume Hubert, Nadine Buard, Cécile Weulersse, Thierry Carrière, Marie-Catherine Palau, Jean-Marie Palau, Damien Lambert, Jacques Baggio, Frederic Wrobel, Frédéric Saigné, Rémi Gaillard	A Review of DASIE Code Family: Contribution to SEU/MBU Understanding.	IOLTS	2005	DBLP DOI BibTeX RDF
5	Jeetendra Kumar, Mehdi Baradaran Tahoori	A Low Power Soft Error Suppression Technique for Dynamic Logic.	DFT	2005	DBLP DOI BibTeX RDF
5	Haruhiko Kaneko	Error Control Coding for Semiconductor Memory Systems in the Space Radiation Environment.	DFT	2005	DBLP DOI BibTeX RDF
5	Harmander Deogun, Dennis Sylvester, David T. Blaauw	Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate.	ISQED	2005	DBLP DOI BibTeX RDF
5	Ghazanfar Asadi, Mehdi Baradaran Tahoori	Soft Error Mitigation for SRAM-Based FPGAs.	VTS	2005	DBLP DOI BibTeX RDF
5	Kartik Mohanram	Closed-Form Simulation and Robustness Models for SEU-Tolerant Design.	VTS	2005	DBLP DOI BibTeX RDF
5	André K. Nieuwland, Richard P. Kleihorst	IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	IC cost, IC production, fault tolerant, redundancy, yield, soft error, on-line test, defect density, SEU, SER, BISR
5	M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, Alessandro Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin	Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA.	DATE	2004	DBLP DOI BibTeX RDF
5	Maya B. Gokhale, Paul S. Graham, Darrel Eric Johnson, Nathan Rollins, Michael J. Wirthlin	Dynamic Reconfiguration for Management of Radiation-Induced Faults in FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF
5	Srivathsan Krishnamohan, Nihar R. Mahapatra	A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits.	ICCD	2004	DBLP DOI BibTeX RDF
5	Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs.	IOLTS	2004	DBLP DOI BibTeX RDF
5	Guillermo Gutiérrez-Alcaraz, Gerald B. Sheblé	Real Option Data Requirements of Power System Data for Competitive Bidding.	HICSS	2004	DBLP DOI BibTeX RDF
5	Yuan Xie 0001, Lin Li 0002, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Reliability-Aware Co-Synthesis for Embedded Systems.	ASAP	2004	DBLP DOI BibTeX RDF
5	Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali	Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs.	PRDC	2004	DBLP DOI BibTeX RDF
5	Michael J. Turmon, Robert Granat, Daniel S. Katz, John Z. Lou	Tests and Tolerances for High-Performance Software-Implemented Fault Detection.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	error analysis, Algorithm-based fault tolerance, result checking, aerospace, parallel numerical algorithms
5	Richard Conway 0001, John S. Nelson	New CRT-Based RNS Converter Using Restricted Moduli Set.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	error analysis, Algorithm-based fault tolerance, result checking, aerospace, parallel numerical algorithms
5	Matthias Pflanz, Karsten Walther, Christian Galke, Heinrich Theodor Vierhaus	On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	cross-parity check, on-line BIST, multiple soft-error detection, self-repair
5	Matteo Sonza Reorda, Massimo Violante	Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits.	FPL	2003	DBLP DOI BibTeX RDF
5	Michael J. Wirthlin, Darrel Eric Johnson, Nathan Rollins, Michael P. Caffrey, Paul S. Graham	The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets.	FCCM	2003	DBLP DOI BibTeX RDF
5	André K. Nieuwland, Richard P. Kleihorst	The positive effect on IC yield of embedded Fault Tolerance for SEUs.	IOLTS	2003	DBLP DOI BibTeX RDF
5	Bruce I. Reiner, Eliot L. Siegel, John A. Carrino	Workflow Optimization: Current Trends and Future Directions.	J. Digit. Imaging	2002	DBLP DOI BibTeX RDF
5	Bernard Coloma, Patrick Delaunay, Olivier Husson	High Speed 15 ns 4 Mbits SRAM for Space Application.	MTDT	2002	DBLP DOI BibTeX RDF
5	Bernard Coloma, Patrick Delaunay, Olivier Husson	High Speed 15 ns 4 Mbits SRAM for Space Application.	IOLTW	2002	DBLP DOI BibTeX RDF
5	Hongyuan Zha, Xiang Ji 0001	Correlating multilingual documents via bipartite graph modeling.	SIGIR	2002	DBLP DOI BibTeX RDF	translingual text summarization, singular value decomposition, graph partitioning, bipartite graph
5	Lörinc Antoni, Régis Leveugle, Béla Fehér	Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.	DFT	2002	DBLP DOI BibTeX RDF
5	Matteo Sonza Reorda, Massimo Violante	Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments.	DFT	2002	DBLP DOI BibTeX RDF
5	Érika F. Cota, Fernanda Lima 0001, Sana Rezgui, Luigi Carro, Raoul Velazco, Marcelo Lubaszewski, Ricardo Reis 0001	Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	integrated circuits radiation effects, aerospace testing, built-in-testing, microprocessor testing
5	Raoul Velazco, Régis Leveugle, Oscar Calvo	Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results.	DFT	2001	DBLP DOI BibTeX RDF	fuzzy logic, VHDL, fault injection
5	Seung H. Hwang, Gwan S. Choi	A Reliability Testing Environment for Off-the-Shelf Memory Subsystems.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
5	Alfredo Benso, Stefano Martinetto, Paolo Prinetto, Riccardo Mariani	An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications.	ICCD	2000	DBLP DOI BibTeX RDF
5	Vincent Pouget, Pascal Fouillat, Dean Lewis, Hervé Lapuyade, L. Sarger, F. M. Roche, S. Duzellier, R. Ecoffet	An Overview of the Applications of a Pulsed Laser System for SEU Testing.	IOLTW	2000	DBLP DOI BibTeX RDF
5	Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang 0001	Algorithms for transient three-dimensional mixed-level circuit and device simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
5	Ping-Kang Hsiung, Robert H. Thibadeau	Spacetime Visualization of Relativistic Effects.	ACM Conference on Computer Science	1990	DBLP DOI BibTeX RDF
5	Jue-Hsien Chern, John T. Maeda, Lawrence A. Arledge Jr., Ping Yang 0001	SIERRA: a 3-D device simulator for reliability modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
5	Maciej Koutny	Adequacy-Preserving Transformations of COSY Path Programs.	Concurrency	1988	DBLP DOI BibTeX RDF