Search results for "superscalar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Yuh-Horng Shiau, Chung-Ping Chung	Effects and Handling of Instruction Class Contention in Superscalar Processing.	Int. J. High Speed Comput.	1994	DBLP DOI BibTeX RDF
17	Roger Collins, Gordon B. Steven	An explicitly declared delayed-branch mechanism for a superscalar architecture.	Microprocess. Microprogramming	1994	DBLP DOI BibTeX RDF
17	Brad Burgess, Mike Alexander, Ying-wai Ho, Suzanne Plummer Litch, Soummya Mallick, Deene Ogden, Sung-Ho Park, Jeff Slaton	The PowerPC 603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor.	COMPCON	1994	DBLP DOI BibTeX RDF
17	Eric Reiher, Herbert H. J. Hum, Ajit Singh	Simulating networks of superscalar processors.	Annual Simulation Symposium	1994	DBLP DOI BibTeX RDF
17	Christian Iseli, Eduardo Sanchez	A Superscalar and Reconfigurable Processor.	FPL	1994	DBLP DOI BibTeX RDF
17	Ko-Yang Wang	Precise Compile-Time Performance Prediction for Superscalar-Based Computers.	PLDI	1994	DBLP DOI BibTeX RDF	IBM RS/6000
17	Alain Greiner, Luis Lucas, Franck Wajsbürt, Laurent Winckel	Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
17	Masahito Matsuo, Hiroyuki Kondo, Yukari Takata, Souichi Kobayashi, Mitsugu Satoh, Toyohiko Yoshida, Yuichi Saitoh, Jun-ichi Hinata	A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface.	ICCD	1994	DBLP DOI BibTeX RDF
17	H. A. Rizvi, James B. Sinclair, J. Robert Jump, J. Carson	Execution-Driven Simulation of a Superscalar Processor.	HICSS (1)	1994	DBLP BibTeX RDF
17	Steven Wallace, Nader Bagherzadeh	Performance Issues of a Superscalar Microprocessor.	ICPP (1)	1994	DBLP DOI BibTeX RDF
17	Shyh-Kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu	An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures.	ICPP (1)	1994	DBLP DOI BibTeX RDF
17	Atsushi Inoue, Kenji Takeda	Performance evaluation for various configuration of superscalar processors.	SIGARCH Comput. Archit. News	1993	DBLP DOI BibTeX RDF
17	Nasr Ullah, Matt Holle	The MC88110 implementation of precise exceptions in a superscalar architecture.	SIGARCH Comput. Archit. News	1993	DBLP DOI BibTeX RDF
17	Kunio Uchiyama, Fumio Arakawa, Susumu Narita, Hirokazu Aoki, Ikuya Kawasaki, Shigezumi Matsui, Mitsuyoshi Yamamoto, Norio Nakagawa, Ikuo Kudo	The Gmicro/500 superscalar microprocessor with branch buffers.	IEEE Micro	1993	DBLP DOI BibTeX RDF
17	Wen-mei W. Hwu, Scott A. Mahlke, William Y. Chen, Pohua P. Chang, Nancy J. Warter, Roger A. Bringmann, Roland G. Ouellette, Richard E. Hank, Tokuzo Kiyohara, Grant E. Haab, John G. Holm, Daniel M. Lavery	The superblock: An effective technique for VLIW and superscalar compilation.	J. Supercomput.	1993	DBLP DOI BibTeX RDF
17	Shlomo Weiss	Optimizing a superscalar machine to run vector code.	IEEE Parallel Distributed Technol. Syst. Appl.	1993	DBLP DOI BibTeX RDF
17	Hong Chich Chou, Chung-Ping Chung	Modeling of Superscalar Instruction Scheduling and Analysis of a Heuristic Scheduling Algorithm.	BIT	1993	DBLP DOI BibTeX RDF
17	Edil S. T. Fernandes, Fernando M. B. Barbosa, David M. Simpson 0001	Evaluating the Cost of conditional branches on the performance of superscalar machines.	Microprocess. Microprogramming	1993	DBLP DOI BibTeX RDF
17	Fleur L. Steven, Rod Adams, Gordon B. Steven, L. Wang, D. J. Whale	Addressing mechanisms for VLIW and superscalar processors.	Microprocess. Microprogramming	1993	DBLP DOI BibTeX RDF
17	Yen-Jen Oyang	Exploiting multi-way branches to boost superscalar processor performance.	Microprocess. Microprogramming	1993	DBLP DOI BibTeX RDF
17	Jin-Ching Chung	Modeling and Evaluation of a Superscalar Architecture.	MASCOTS	1993	DBLP BibTeX RDF
17	Matthew K. Farrens, Pius Ng, Phil Nico	A comparision of superscalar and decoupled access/execute architectures.	MICRO	1993	DBLP DOI BibTeX RDF
17	Trung A. Diep, John Paul Shen, Mike Phillip	EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors.	MICRO	1993	DBLP DOI BibTeX RDF
17	Tse-Yu Yeh, Yale N. Patt	Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors.	MICRO	1993	DBLP DOI BibTeX RDF
17	Andrew Wolfe, Rodney Boleyn	Two-ported cache alternatives for superscalar processors.	MICRO	1993	DBLP DOI BibTeX RDF
17	John Lenell, Nader Bagherzadeh	A Performance Comparison of Several Superscalar Processor Models with a VLIW Processor.	IPPS	1993	DBLP DOI BibTeX RDF
17	Rodney Boleyn, James Debardelaben, Vivek Tiwari, Andrew Wolfe	A Split Data Cache for Superscalar Processors.	ICCD	1993	DBLP DOI BibTeX RDF
17	Christian Iseli, Eduardo Sanchez	Beyond Superscalar Using FPGAs.	ICCD	1993	DBLP DOI BibTeX RDF
17	Soo-Mook Moon, Kemal Ebcioglu, Ashok K. Agrawala	Selective Scheduling Framework for Speculative Operations in VLIW and Superscalar Processors.	Architectures and Compilation Techniques for Fine and Medium Grain Parallelism	1993	DBLP BibTeX RDF
17	Soo-Mook Moon, Kemal Ebcioglu	On Performance, Efficiency of VLIW and Superscalar.	ICPP (2)	1993	DBLP DOI BibTeX RDF
17	Daejoon Hwang, Seung Ho Cho, Y. D. Kim, Sangyong Han	Exploiting Spatial and Temporal Parallelism in the Multithreaded Node Architecture Implemented on Superscalar RISC Processors.	ICPP (1)	1993	DBLP DOI BibTeX RDF
17	James K. Pickett, David G. Meyer	Enhanced superscalar hardware: the schedule table.	SC	1993	DBLP DOI BibTeX RDF	MIPS R2000
17	Tse-Yu Yeh	Two-level adaptive branch prediction and instruction fetch mechanisms for high performance superscalar processors.		1993	RDF
17	Michael Laird	A comparison of three current superscalar designs.	SIGARCH Comput. Archit. News	1992	DBLP DOI BibTeX RDF
17	Keith Diefendorff, Michael Allen	Organization of the Motorola 88110 superscalar RISC microprocessor.	IEEE Micro	1992	DBLP DOI BibTeX RDF
17	Yuh-Horng Shiau, Chung-Ping Chung	Adoptability and effectiveness of microcode compaction algorithms in superscalar processing.	Parallel Comput.	1992	DBLP DOI BibTeX RDF
17	Takaya Arita, Hiroaki Ito, Masahiro Sowa	Performance of the PN superscalar processor as estimated by simulation.	Syst. Comput. Jpn.	1992	DBLP DOI BibTeX RDF
17	Chih-Po Wen	Improving instruction supply efficiency in superscalar architectures using instruction trace buffers.	SAC	1992	DBLP DOI BibTeX RDF
17	Thang Tran, Chuan-lin Wu	Limitation of superscalar microprocessor performance.	MICRO	1992	DBLP DOI BibTeX RDF
17	Thomas M. Conte	Tradeoffs in processor/memory interfaces for superscalar processors.	MICRO	1992	DBLP DOI BibTeX RDF
17	Tokuzo Kiyohara, John C. Gyllenhaal	Code scheduling for VLIW/superscalar processors with limited register files.	MICRO	1992	DBLP DOI BibTeX RDF
17	Harry Dwyer, Hwa C. Torng	An out-of-order superscalar processor with speculative execution and fast, precise interrupts.	MICRO	1992	DBLP DOI BibTeX RDF
17	Takaaki Kato, Toshihisa Ono, Nader Bagherzadeh	Performance analysis and design methodology for a scalable superscalar architecture.	MICRO	1992	DBLP DOI BibTeX RDF
17	Benoît Dupont de Dinechin	StaCS: a Static Control Superscalar architecture.	MICRO	1992	DBLP DOI BibTeX RDF
17	Suresh Srinivas, R. Kent Dybvig	Superscalar Floating-Point Vector Computation in Scheme.	CONPAR	1992	DBLP DOI BibTeX RDF
17	Thomas M. Conte, Wen-mei W. Hwu	Systematic prototyping of superscalar computer architectures.	RSP	1992	DBLP DOI BibTeX RDF
17	Takaaki Kato, Koji Suginuma, Nader Bagherzadeh	On Design and Performance Analysis of a Superscalar Architecture.	ICPP (1)	1992	DBLP BibTeX RDF
17	Kisaburo Nakazawa, Hiroshi Nakamura, Hiromitsu Imori, Shun Kawabe	Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline.	SC	1992	DBLP DOI BibTeX RDF
17	Scott A. Mahlke, William Y. Chen, John C. Gyllenhaal, Wen-mei W. Hwu	Compiler Code Transformations for Superscalar-Based High Performance Systems.	SC	1992	DBLP DOI BibTeX RDF
17	Feipei Lai, Meng-chou Chang	Enhancing boosting with semantic register in a superscalar processor.	ISCA	1992	DBLP DOI BibTeX RDF
17	Yen-Jen Oyang, Chun-Hung Wen, Ching-Chuan Chiang, Ching-Te Lin, Yu-Fen Chen, Shu-May Lin, Chao-Yi Fang, Fu-Li Chen, Chou-Yu Ku	Major Architectural Features of the Spectra-I Superscalar Microprocessor.	J. Inf. Sci. Eng.	1991	DBLP BibTeX RDF
17	Takaya Arita, Masahiro Sowa	High Speed Synchronization for a Statically Scheduled Superscalar Processor.	Int. J. High Speed Comput.	1991	DBLP DOI BibTeX RDF
17	Mike Johnson	Superscalar microprocessor design.		1991	RDF
17	Steve McGeady, Randy Steck, Glenn Hinton, Atiq Bajwa	Performance enhancements in the superscalar i960MM embedded microprocessor.	Compcon	1991	DBLP DOI BibTeX RDF
17	Lee F. Hanson, Nathan A. Brookwood	The C400 superscalar/superpipelined RISC design.	Compcon	1991	DBLP DOI BibTeX RDF
17	William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu	Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching.	MICRO	1991	DBLP DOI BibTeX RDF
17	David Bernstein, Michael Rodeh	Global Instruction Scheduling for Superscalar Machines.	PLDI	1991	DBLP DOI BibTeX RDF
17	M. Hanawa, Tadahiko Nishimukai, O. Nishii, Masato Suzuki, K. Yano, M. Hiraki, S. Shukuri, T. Nishida	On-Chip Multiple Superscalar Processors with Secondary Cache Memories.	ICCD	1991	DBLP DOI BibTeX RDF
17	George E. Daddis Jr., Hwa C. Torng	The Concurrent Execution of Multiple Instruction Streams on Superscalar Processors.	ICPP (1)	1991	DBLP BibTeX RDF
17	Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota	OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications.	ISCA	1991	DBLP DOI BibTeX RDF
17	Roland L. Lee, Alex Y. Kwok, Faye A. Briggs	The Floating-Point Performance of a Superscalar SPARC Processor.	ASPLOS	1991	DBLP DOI BibTeX RDF
17	Gurindar S. Sohi, Manoj Franklin	High-Bandwidth Data Memory Systems for Superscalar Processors.	ASPLOS	1991	DBLP DOI BibTeX RDF
17	Yen-Jen Oyang, Chun-Hung Wen, Yu-Fen Chen, Shu-May Lin	The effect of employing advanced branching mechanisms in superscalar processors.	SIGARCH Comput. Archit. News	1990	DBLP DOI BibTeX RDF
17	Steve McGeady	Inside Intel's i960CA superscalar processor.	Microprocess. Microsystems	1990	DBLP DOI BibTeX RDF
17	David N. Glass	Compile-time instruction scheduling for superscalar processors.	Compcon	1990	DBLP DOI BibTeX RDF
17	Steve McGeady	The i960CA SuperScalar implementation of the 80960 architecture.	Compcon	1990	DBLP DOI BibTeX RDF
17	David J. Lilja, Pen-Chung Yew	Comparing Parallelism Extraction Techniques: Superscalar Processors, Pipelined Processors, and Multiprocessors.	ICPP (1)	1990	DBLP BibTeX RDF
17	Michael D. Smith 0001, Monica S. Lam, Mark Horowitz	Boosting Beyond Static Scheduling in a Superscalar Processor.	ISCA	1990	DBLP DOI BibTeX RDF
17	Norman P. Jouppi	Superscalar vs. superpipelined machines.	SIGARCH Comput. Archit. News	1988	DBLP DOI BibTeX RDF
15	Avi Timor, Avi Mendelson, Yitzhak Birk, Neeraj Suri	Using Underutilized CPU Resources to Enhance Its Reliability.	IEEE Trans. Dependable Secur. Comput.	2010	DBLP DOI BibTeX RDF	double execution, fault tolerance, soft errors, microarchitecture, Transient faults, superscalar
15	Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg	EXACT: explicit dynamic-branch prediction with active updates.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	branch prediction, microarchitecture, superscalar processors
15	Weiwu Hu, Jian Wang	Making Effective Decisions in Computer Architects' Real-World: Lessons and Experiences with Godson-2 Processor Designs.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	correlation design, balanced design, Pico-architecture design, work-on-silicon, optimized design, superscalar architecture
15	Gabriel H. Loh	A modular 3d processor for flexible product design and technology migration.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	modular, superscalar, 3d-integration
15	Oliverio J. Santana, Alex Ramírez, Mateo Valero	Enlarging Instruction Streams.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Superscalar processor design, branch prediction, code optimization, instruction fetch, access latency
15	Robert Granat, Isak Jonsson, Bo Kågström	Recursive Blocked Algorithms for Solving Periodic Triangular Sylvester-Type Matrix Equations.	PARA	2006	DBLP DOI BibTeX RDF	Sylvester-type matrix equations, periodic matrix equations, recursion, blocking, superscalar, level 3 BLAS
15	Weiwu Hu, Fuxin Zhang, Zusong Li	Microarchitecture of the Godson-2 Processor.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	superscalar pipeline, dynamic scheduling non-blocking cache, load speculation, branch prediction, out-of-order execution, register renaming
15	Steve Haga, Natasha Reeves, Rajeev Barua, Diana Marculescu	Dynamic Functional Unit Assignment for Low Power.	J. Supercomput.	2005	DBLP DOI BibTeX RDF	bit patterns, functional unit assignment, low power, hamming distance, superscalar, dynamic power
15	Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran	Dual-pipeline heterogeneous ASIP design.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	dual-pipeline, instruction set generation, ASIP, superscalar
15	Noureddine Chabini, Wayne H. Wolf	An approach for integrating basic retiming and software pipelining.	EMSOFT	2004	DBLP DOI BibTeX RDF	embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size
15	Michel Dubois 0001	Fighting the memory wall with assisted execution.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	prefetching, cache memories, superscalar processors, simultaneous multithreading, latency tolerance
15	Deependra Talla, Lizy Kurian John, Doug Burger	Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	bottlenecks in SIMD extensions, hardware address generation, low-overhead looping, superscalar general-purpose processors, performance evaluation, workload characterization, subword parallelism, Media processing, data reorganization
15	André Seznec, Nicolas Sendrier	HAVEGE: A user-level software heuristic for generating empirically strong random numbers.	ACM Trans. Model. Comput. Simul.	2003	DBLP DOI BibTeX RDF	hardware clock counters, Cryptography, random number generation, superscalar processor
15	Daniel Ortega, Eduard Ayguadé, Mateo Valero	Dynamic memory instruction bypassing.	ICS	2003	DBLP DOI BibTeX RDF	on-chip memory management, superscalar processors
15	Marco Antonio Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero	A Simple Low-Energy Instruction Wakeup Mechanism.	ISHPC	2003	DBLP DOI BibTeX RDF	Instruction wake up, Low power, Superscalar processors, Out of order execution, CAM, Instruction window
15	Isak Jonsson, Bo Kågström	Recursive blocked algorithms for solving triangular systems - Part II: two-sided and generalized Sylvester and Lyapunov matrix equations.	ACM Trans. Math. Softw.	2002	DBLP DOI BibTeX RDF	SMP parallelization, generalized Sylvester and Lyapunov, standard discrete-time Sylvester and Lyapunov, recursion, superscalar, LAPACK, level-3 BLAS, GEMM-based, SLICOT, Matrix equations, automatic blocking
15	Soner Önder	Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets.	IEEE PACT	2002	DBLP DOI BibTeX RDF	load speculation, memory dependence prediction, store sets, wide issue superscalar, speculative execution
15	Haris Lekatsas, Wayne H. Wolf, Yuan Xie 0001	Code Compression for VLIW Processors Using Variable-to-Fixed Coding.	ISSS	2002	DBLP DOI BibTeX RDF	assembly-level analysis, performance estimation, superscalar architectures
15	Josep Llosa, Eduard Ayguadé, Antonio González 0001, Mateo Valero, Jason Eckhardt	Lifetime-Sensitive Modulo Scheduling in a Production Environment.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	register requirements, software pipelining, VLIW, instruction scheduling, loop scheduling, Fine grain parallelism, superscalar architectures
15	Dietmar Fey, Marko Degenkolb	Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	optoelectronic VLSI, signed-digit arithmetic, pipeline processing, optical interconnects, superscalar architectures
15	Umesh Krishnaswamy, Isaac D. Scherson	A Framework for Computer Performance Evaluation Using Benchmark Sets.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Computer performance evaluation, benchmark sets, performance vectors, performance modeling, superscalar processors, vector computers
15	Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen	A Buffer-Oriented Methodology for Microarchitecture Validation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	processor validation, superscalar microarchitecture, design validation
15	Ramon Canal, Antonio González 0001	A low-complexity issue logic.	ICS	2000	DBLP DOI BibTeX RDF	in-order issue, instruction issue logic, wide-issue superscalar, out-of-order issue
15	James J. Carrig Jr., Gerard G. L. Meyer	A parameterized ordering for cache-, register- and pipeline-efficient Givens QR decomposition.	Adv. Comput. Math.	1999	DBLP DOI BibTeX RDF	Givens, 65F25, superscalar processors, 65F05, 65Y10, QR algorithm
15	Derek L. Howard, Mikko H. Lipasti	The Effect of Program Optimization on Trace Cache Efficiency.	IEEE PACT	1999	DBLP DOI BibTeX RDF	compiler optimization, Microarchitecture, superscalar processors, trace cache
15	Emre Özer 0001, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte	A Fast Interrupt Handling Scheme for VLIW Processors.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Interrupt, VLIW, Embedded Processors, ILP, Superscalar, Out-of-order Issue
15	Jared Stark, Paul Racunas, Yale N. Patt	Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order.	MICRO	1997	DBLP DOI BibTeX RDF	instruction supply, superscalar processors, out-of-order execution
15	Chung-Ho Chen, Akida Wu	Microarchitecture Support for Improving the Performance of Load Target Prediction.	MICRO	1997	DBLP DOI BibTeX RDF	load target prediction, load-use stall, speculative data access, superscalar procesor, pipeline
15	Kemal Ebcioglu, Erik R. Altman	DAISY: Dynamic Compilation for 100% Architectural Compatibility.	ISCA	1997	DBLP DOI BibTeX RDF	object code compatible VLIW, instruction-level parallelism, superscalar, binary translation, dynamic compilation
15	Nelson L. Passos, Edwin Hsing-Mean Sha	Achieving Full Parallelism Using Multidimensional Retiming.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	multidimensional data-flow graphs, instruction level parallelism, VLIW, Retiming, loop transformation, superscalar, nested loops
15	Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao	A Framework for Resource-Constrained Rate-Optimal Software Pipelining.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	superscalar and VLIW architectures, Instruction-level parallelism, integer linear programming, software pipelining, instruction scheduling