Search results for "wiring"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Makoto Shimojo, Takuma Araki, Seiichi Teshigawara, Aiguo Ming, Masatoshi Ishikawa	A net-structure tactile sensor covering free-form surface and ensuring high-speed response.	IROS	2007	DBLP DOI BibTeX RDF
9	Charbel J. Akl, Magdy A. Bayoumi	Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects.	ASP-DAC	2007	DBLP DOI BibTeX RDF	transition skew coding, global on-chip interconnects, bus encoding technique, encoding latencies, decoding latencies, 90 nm
9	Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu	Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency.	SiPS	2007	DBLP DOI BibTeX RDF
9	Cheng Wang, Chunjiang Zhao 0001, Xiaojun Qiao, Xin Zhang, Yunhe Zhang	The Design of Wireless Sensor Networks Node for Measuring the Greenhouse's Environment Parameters.	CCTA	2007	DBLP DOI BibTeX RDF	environment parameters, wireless sensor networks, node, greenhouse, msp430
9	Sebastian Voss	Scheduling in Time-Triggered Networks.	OTM Workshops (2)	2007	DBLP DOI BibTeX RDF
9	Daniel Oberhoff, Marina Kolesnik	Neural Object Recognition by Hierarchical Learning and Extraction of Essential Shapes.	BVAI	2007	DBLP DOI BibTeX RDF
9	Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri	A methodology for interconnect dimension determination.	ISPD	2007	DBLP DOI BibTeX RDF
9	Hsing-bung Chen, Gary Grider, Parks Fields	A Cost-Effective, High Bandwidth Server I/O network Architecture for Cluster Systems.	IPDPS	2007	DBLP DOI BibTeX RDF
9	Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Mohammad M. Mojarradi, Srinivas Katkoori, Taher Daud	Adaptive and Evolvable Analog Electronics for Space Applications.	ICES	2007	DBLP DOI BibTeX RDF	Adaptive Hardware, Field Programmable Arrays
9	Luís Soares Barbosa, Jácome Cunha, Joost Visser 0001	A type-level approach to component prototyping.	SYANCO	2007	DBLP DOI BibTeX RDF	type-level programming, Haskell, coalgebra, mealy machine, combinator library
9	Holger Klus, Dirk Niebuhr, Andreas Rausch	A component model for dynamic adaptive systems.	ESSPE	2007	DBLP DOI BibTeX RDF	component container, adaptation, component model, component composition, componentware
9	Saumitra M. Das, Konstantina Papagiannaki, Suman Banerjee 0001, Y. C. Tay	SWARM: self-organization of community wireless mesh networks.	CoNEXT	2007	DBLP DOI BibTeX RDF
9	Dariusz Koscielnik	The Structure of a Control Network Integrated with the S-bus of an ISDN Network.	ICN	2007	DBLP DOI BibTeX RDF	field network, controll network, S-bus, system integration
9	Holger Klus, Dirk Niebuhr, Andreas Rausch	Towards a Component Model supporting Proactive Configuration of Service-Oriented Systems.	ICEBE	2007	DBLP DOI BibTeX RDF
9	Miwa Nakanishi, Mugihiko Ozeki, Toshiya Akasaka, Yusaku Okada	Human factor requirements for Applying Augmented reality to manuals in actual work situations.	SMC	2007	DBLP DOI BibTeX RDF
9	Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao 0001	A novel technique for incremental analysis of on-chip power distribution networks.	ICCAD	2007	DBLP DOI BibTeX RDF
9	Akira Mochizuki, Masatomo Miura, Takahiro Hanyu	High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction.	ISMVL	2007	DBLP DOI BibTeX RDF
9	Yasushi Yuminaka, Kazuyoshi Yamamura	Equalization Techniques for Multiple-Valued Data Transmission and Their Application.	ISMVL	2007	DBLP DOI BibTeX RDF
9	Yasutoshi Makino, Hiroyuki Shinoda	Comfortable Wristband Interface Measuring Myoelectric Pattern.	WHC	2007	DBLP DOI BibTeX RDF
9	Sheng Sun, Carl Sechen	Post-layout comparison of high performance 64b static adders in energy-delay space.	ICCD	2007	DBLP DOI BibTeX RDF
9	Nobuyuki Yamasaki, Ikuo Magaki, Tsutomu Itou	Prioritized SMT Architecture with IPC Control Method for Real-Time Processing.	IEEE Real-Time and Embedded Technology and Applications Symposium	2007	DBLP DOI BibTeX RDF
9	Pietro Michiardi, Paul Marrow, Richard Tateson, Fabrice Saffre	Aggregation Dynamics in Service Overlay Networks.	SASO	2007	DBLP DOI BibTeX RDF
9	Santosh Shah, Arani Sinha, Li Song, Narain D. Arora	On-Chip Inductance in X Architecture Enabled Design.	ISQED	2007	DBLP DOI BibTeX RDF
9	Hongjie Bai, Sheqin Dong, Xianlong Hong	Congestion Driven Buffer Planning for X-Architecture.	ISQED	2007	DBLP DOI BibTeX RDF
9	Javid Jaffari, Mohab Anis	Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model.	ISQED	2007	DBLP DOI BibTeX RDF
9	Peng Li, Simon Marlow, Simon L. Peyton Jones, Andrew P. Tolmach	Lightweight concurrency primitives for GHC.	Haskell	2007	DBLP DOI BibTeX RDF	concurrency, transactional memory, haskell, thread
9	Leonard G. C. Hamey, Timothy Watkins, Simon Wong Too Yen	Pancam: In-Service Inspection of Locomotive Pantographs.	DICTA	2007	DBLP DOI BibTeX RDF
9	Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie 0001, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das	A novel dimensionally-decomposed router for on-chip communication in 3D architectures.	ISCA	2007	DBLP DOI BibTeX RDF	3D architecture, 3D integration, network-on-chip (NoC)
9	Hiroyuki Torikai	Fundamental Analysis of a Digital Spiking Neuron for Its Spike-Based Coding.	ICONIP (2)	2007	DBLP DOI BibTeX RDF
9	Roman Obermaisser	Reuse of CAN-Based Legacy Applications in Time-Triggered Architectures.	IEEE Trans. Ind. Informatics	2006	DBLP DOI BibTeX RDF
9	Marc Vass, Clifford A. Shaffer, Naren Ramakrishnan, Layne T. Watson, John J. Tyson	The JigCell Model Builder: A Spreadsheet Interface for Creating Biochemical Reaction Network Models.	IEEE ACM Trans. Comput. Biol. Bioinform.	2006	DBLP DOI BibTeX RDF	Biochemical reaction networks, user interface paradigms, modeling, bioinformatics
9	Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano	A Simple Data Transfer Technique Using Local Address for Networks-on-Chips.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	table-lookup routing, interconnection networks, Networks-on-chips, streaming processing, reconfigurable systems, on-chip interconnects
9	Qinghua Liu, Malgorzata Marek-Sadowska	Semi-Individual Wire-Length Prediction With Application to Logic Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda	Impact of stress-induced backflow on full-chip electromigration risk assessment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	Stefano Galli, Thomas C. Banwell	A deterministic frequency-domain model for the indoor power line transfer function.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
9	Marc Kuhn, Stefan Berger, Ingmar Hammerström, Armin Wittneben	Power line enhanced cooperative wireless communications.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
9	Fadi N. Karameh, Munther A. Dahleh, Emery N. Brown, Steve G. Massaquoi	Modeling the contribution of lamina 5 neuronal and network dynamics to low frequency EEG phenomena.	Biol. Cybern.	2006	DBLP DOI BibTeX RDF
9	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.	ISVLSI	2006	DBLP DOI BibTeX RDF
9	Anne-Claude Gavin	Global Interaction Networks Probed by Mass Spectrometry.	RECOMB	2006	DBLP DOI BibTeX RDF
9	Yohei Matsumoto, Hanpei Koike, Akira Masaki	FPGAs with multidimensional mesh topology.	FPGA	2006	DBLP DOI BibTeX RDF
9	Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez	A multilevel hierarchical interconnection structure for FPGA.	FPGA	2006	DBLP DOI BibTeX RDF
9	Christian Beaulieu	The biological basis of diffusion tractography.	ISBI	2006	DBLP DOI BibTeX RDF
9	J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne	Analysis and modeling of power grid transmission lines.	DATE	2006	DBLP DOI BibTeX RDF
9	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Constraint-driven bus matrix synthesis for MPSoC.	ASP-DAC	2006	DBLP DOI BibTeX RDF
9	Eric Wade, H. Harry Asada	DC Behavior of Conductive Fabric Networks with Application to Wearable Sensor Nodes.	BSN	2006	DBLP DOI BibTeX RDF
9	Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen	Efficient generation of short and fast repeater tree topologies.	ISPD	2006	DBLP DOI BibTeX RDF	inverter tree, repeater tree, buffering, tree topology, rectilinear Steiner tree
9	Valerio Plessi, Filippo Bastianini, Sahra Sedigh-Ali	An Autonomous and AdaptableWireless Device for Flood Monitoring.	COMPSAC (2)	2006	DBLP DOI BibTeX RDF
9	Roman Obermaisser, Philipp Peti	Realization of virtual networks in the DECOS integrated architecture.	IPDPS	2006	DBLP DOI BibTeX RDF
9	Jun Xu, Reza Sotudeh, Mark B. Josephs	Asynchronous Packet-Switching for Networks-on-Chip.	ACSD	2006	DBLP DOI BibTeX RDF
9	Nachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, André DeHon	Packet Switched vs. Time Multiplexed FPGA Overlay Networks.	FCCM	2006	DBLP DOI BibTeX RDF
9	Sungyun Jung, Sung-oh Yang, Kwang-Ryul Baek	Study on Inter-operability Unit for an Automobile Network.	ICIC (2)	2006	DBLP DOI BibTeX RDF
9	Zhongsheng Hua, Feihua Huang	A Hybrid Heuristic for PWB Capacity Expansion Problem.	ICIC (1)	2006	DBLP DOI BibTeX RDF
9	Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez	Performances improvement of FPGA using novel multilevel hierarchical interconnection structure.	ICCAD	2006	DBLP DOI BibTeX RDF
9	Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Designing application-specific networks on chips with floorplan information.	ICCAD	2006	DBLP DOI BibTeX RDF	networks on chips, topology, floorplan, deadlock-free routing
9	Dirk Müller 0003	Optimizing yield in global routing.	ICCAD	2006	DBLP DOI BibTeX RDF	Steiner tree packing, multi-commodity flows, yield optimization, VLSI routing
9	Prashant Saxena	The scaling of interconnect buffer needs.	SLIP	2006	DBLP DOI BibTeX RDF	interconnect, scaling, buffers, repeaters
9	J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne	Constant impedance scaling paradigm for interconnect synthesis.	SLIP	2006	DBLP DOI BibTeX RDF	transmission lines, interconnect optimization, global interconnects
9	Martin Siebenhaller	Partitioned Drawings.	GD	2006	DBLP DOI BibTeX RDF
9	Markus Lumpe, Jean-Guy Schneider	On the Integration of Classboxes into C#.	SC@ETAPS	2006	DBLP DOI BibTeX RDF
9	Jun Ohta, Takahashi Tokuda, Keiichiro Kagawa, Akihiro Uehara, Yasuo Terasawa, Kenzo Shodo, Takashi Fujikado, Yasuo Tano	Toward 1000-ch electrode array based on distributed microchip architecture for retinal prosthesis.	ISCAS	2006	DBLP DOI BibTeX RDF
9	S. P. Shang, Xiaodong Hu 0001, Tong Jing	Average lengths of wire routing under M-architecture and X-architecture.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Samy M. Boshra, Hazem M. Abbas, Ahmed M. Darwish 0001, Ihab E. Talkhan	Performance and routability improvements for routability-driven FPGA routers.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Hsin-Hsiung Huang, Yung-Ching Chen, Tsai-Ming Hsieh	A congestion-driven buffer planner with space reservation.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos	An Energy-Delay Efficient Subword Permutation Unit.	ASAP	2006	DBLP DOI BibTeX RDF
9	Xu Zhang, Xiaohong Jiang 0001, Susumu Horiguchi	A non-orthogonal clock distribution network and its performance evaluation in presence of process variations and inductive effects.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	H-Tree, X Architecture, performance evluation, variant X-Tree, clock distribution network
9	Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal	Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	measurement, process variations, extraction, VLSI interconnects
9	Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys	Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects.	ISQED	2006	DBLP DOI BibTeX RDF
9	Christoph Heller, Josef Schalk, Stefan Schneele, Maria Sorea, Sebastian Voss	Flexible Communication Architecture for Dependable Time-Triggered Systems.	WADS	2006	DBLP DOI BibTeX RDF
9	Masashi Toda, Junichi Akita, Shigeru Sakurazawa, Keisuke Yanagihara, Mihoko Kunita, Kunio Iwata	Wearable Biomedical Monitoring System Using TextileNet.	SWC	2006	DBLP DOI BibTeX RDF
9	Simon Ogg, Bashir M. Al-Hashimi	Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal.	VLSI Design	2006	DBLP DOI BibTeX RDF
9	Mireille Grégoire, Elmar Schömer	Interactive simulation of one-dimensional flexible parts.	Symposium on Solid and Physical Modeling	2006	DBLP DOI BibTeX RDF	cable simulation, cosserat model, modelling of torsion
9	Massoud Masoumi, Farshid Raissi, Mahmoud Ahmadian	NanoCMOS-Molecular Realization of Rijndael.	CHES	2006	DBLP DOI BibTeX RDF	VLSI realization, CMOL, Rijndael
9	Jin-Tai Yan, Zhi-Wei Chen, Chia-Wei Wu, Ming-Yuen Wu	Optimal Network Analysis in Hierarchical Power Quad-Grids.	APCCAS	2006	DBLP DOI BibTeX RDF
9	A. B. Aljunaid, I. AbuElMaaly, Assim Sagahyroon	Using ANN To Predict The Best HUB Location.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Chirag S. Patel	Silicon carrier for computer systems.	DAC	2006	DBLP DOI BibTeX RDF	chip-package co-design, electrical modeling, micro-bumps, silicon carrier, computer system, CMOS scaling, system on package
9	Kaustav Banerjee, Navin Srivastava	Are carbon nanotubes the future of VLSI interconnections?	DAC	2006	DBLP DOI BibTeX RDF	VLSI, interconnects, carbon nanotubes
9	Magnus J. E. Richardson, Ofer Melamed, Gilad Silberberg, Wulfram Gerstner, Henry Markram	Short-Term Synaptic Plasticity Orchestrates the Response of Pyramidal Cells and Interneurons to Population Bursts.	J. Comput. Neurosci.	2005	DBLP DOI BibTeX RDF	population bursts, cortical microcircuit, dynamic synapses, interneurons
9	Ajay Joshi, Jeffrey A. Davis	Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI).	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
9	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
9	Friedrich W. Kistermann	Hollerith Punched Card System Development (1905-1913).	IEEE Ann. Hist. Comput.	2005	DBLP DOI BibTeX RDF
9	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-independent testing of FPGA interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
9	Jaskirat Singh, Sachin S. Sapatnekar	Congestion-aware topology optimization of structured power/ground networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
9	Peter Kornerup	Reviewing 4-to-2 Adders for Multi-Operand Addition.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	redundant adders, digit sets, digit encodings, multiplier trees
9	William H. Robinson, D. Scott Wills	Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	focal plane processing, digital pixel, area-time efficiency, energy efficiency, single-instruction multiple-data (SIMD), area efficiency
9	Giorgos Dimitrakopoulos, Dimitris Nikolos	Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing.	PATMOS	2005	DBLP DOI BibTeX RDF
9	Qinghua Liu, Malgorzata Marek-Sadowska	Wire length prediction-based technology mapping and fanout optimization.	ISPD	2005	DBLP DOI BibTeX RDF	prediction, congestion, wire length
9	Hongkyu Kim, D. Scott Wills, Linda M. Wills	Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport.	IPDPS	2005	DBLP DOI BibTeX RDF
9	Sharareh Babvey, José Alberto Fernández-Zepeda, Anu G. Bourgeois, Steven W. McLaughlin	An Efficient R-Mesh Implementation of LDPC Codes Message-Passing Decoder.	IPDPS	2005	DBLP DOI BibTeX RDF
9	Mehrdad Reshadi, Daniel Gajski	A cycle-accurate compilation algorithm for custom pipelined datapaths.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	NISC, cycle-accurate compiler, scheduling
9	Sharmila Ravula, Ji Eun Kim, Brad Petrus, Christoph Stoermer	Quality Attributes in Wireless Sensor Networks.	SEUS	2005	DBLP DOI BibTeX RDF
9	Kyung-Bae Chang, Il-Joo Shim, Tae-Kook Kim, Gwi-Tae Park	System Integration Using Embedded Web Server and Wireless Communication.	DCOSS	2005	DBLP DOI BibTeX RDF
9	J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne	Package level interconnect options.	SLIP	2005	DBLP DOI BibTeX RDF	performance metrics, package, transmission lines, global interconnects
9	Ron Ho	High-performance ULSI: the real limiter to interconnect scaling.	SLIP	2005	DBLP DOI BibTeX RDF	VLSI, wireless, 3D, scaling, proximity, repeaters, wires
9	Sharareh Babvey, Anu G. Bourgeois, José Alberto Fernández-Zepeda, Steven W. McLaughlin	A Parallel Implementation of the Message-Passing Decoder of LDPC Codes Using a Reconfigurable Optical Model.	SNPD	2005	DBLP DOI BibTeX RDF	optical buses, message-passing decoder, Reconfigurable architectures, LDPC codes
9	Jürgen Fischer, Philip Teichmann, Doris Schmitt-Landsiedel	Scaling trends in adiabatic logic.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	low power, energy recovery, adiabatic computing
9	Hsin-Chou Chi, Chia-Ming Wu	Efficient Switches for Network-on-Chip Based Embedded Systems.	EUC	2005	DBLP DOI BibTeX RDF
9	Ajay Joshi, Jeffrey A. Davis	Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	interconnect sharing, time division, wave-pipelining
9	Navin Srivastava, Xiaoning Qi, Kaustav Banerjee	Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
9	Atul Katoch, Maurice Meijer, Sanjeev K. Jain	Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication.	VLSI Design	2005	DBLP DOI BibTeX RDF