Search results for "DDECS"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Sebastian Arming, Roman Fenkhuber, Thomas Handl	Data compression in hardware - The Burrows-Wheeler approach.	DDECS	2010	DBLP DOI BibTeX RDF
1	Farid Lahrach, Abderrazek Abdaoui, Abderrahim Doumar, Eric Châtelet	A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks.	DDECS	2010	DBLP DOI BibTeX RDF
1	Carlos Leong, Pedro Machado, Vasco Bexiga, João Paulo Teixeira 0001, Isabel C. Teixeira, José C. Silva, Pedro Lousã, João Varela	Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems.	DDECS	2010	DBLP DOI BibTeX RDF
1	Tomas Mazanec, Antonin Hermanek, Jan Kamenický	Blind image deconvolution algorithm on NVIDIA CUDA platform.	DDECS	2010	DBLP DOI BibTeX RDF
1	Ad J. van de Goor, Said Hamdioui, Georgi Gaydadjiev	Using a CISC microcontroller to test embedded memories.	DDECS	2010	DBLP DOI BibTeX RDF
1	Tobias Koal, Heinrich Theodor Vierhaus	A software-based self-test and hardware reconfiguration solution for VLIW processors.	DDECS	2010	DBLP DOI BibTeX RDF
1	Martin Straka, Jan Kastil, Zdenek Kotásek	Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs.	DDECS	2010	DBLP DOI BibTeX RDF
1	Martin Krammer, Federico Clazzer, Eric Armengaud, Michael Karner, Christian Steger, Reinhold Weiss	Exploration of the FlexRay signal integrity using a combined prototyping and simulation approach.	DDECS	2010	DBLP DOI BibTeX RDF
1	Liviu Agnola, Mircea Vladutiu, Mihai Udrescu	Self-Adaptive mechanism for cache memory reliability improvement.	DDECS	2010	DBLP DOI BibTeX RDF
1	Tobias Koal, Heinrich Theodor Vierhaus	Combining de-stressing and self repair for long-term dependable systems.	DDECS	2010	DBLP DOI BibTeX RDF
1	Danilo Ravotto, Ernesto Sánchez 0001, Matteo Sonza Reorda	A hardware accelerated framework for the generation of design validation programs for SMT processors.	DDECS	2010	DBLP DOI BibTeX RDF
1	Kurt Schweiger, Horst Zimmermann	Highly linear down-conversion mixer in 65nm CMOS for a high supply voltage of 2.5V.	DDECS	2010	DBLP DOI BibTeX RDF
1	Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet	Synthesis of asynchronous monitors for critical electronic systems.	DDECS	2010	DBLP DOI BibTeX RDF
1	Václav Simek, Richard Ruzicka, Lukás Sekanina	On analysis of fabricated polymorphic circuits.	DDECS	2010	DBLP DOI BibTeX RDF
1	Tetsuya Iizuka, Toru Nakura, Kunihiro Asada	Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects.	DDECS	2010	DBLP DOI BibTeX RDF
1	Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang	A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop.	DDECS	2010	DBLP DOI BibTeX RDF
1	Marcus Jeitler, Jakob Lechner, Andreas Steininger	Enhancing pipelined processor architectures with fast autonomous recovery of transient faults.	DDECS	2010	DBLP DOI BibTeX RDF
1	Amr Helmy, Laurence Pierre, Axel Jantsch	Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing.	DDECS	2010	DBLP DOI BibTeX RDF
1	Mehmood-ur-Rehman Awan, Peter Koch 0001	Combined matched filter and arbitrary interpolator for symbol timing synchronization in SDR receivers.	DDECS	2010	DBLP DOI BibTeX RDF
1	Bo Han, Mengmeng Liu, Ning Ge	A 3-5GHz UWB CMOS receiver with digital control technique.	DDECS	2010	DBLP DOI BibTeX RDF
1	Filip Adamec, Tomas Fryza	Design - Time configurable processor basic structure.	DDECS	2010	DBLP DOI BibTeX RDF
1	Zheng Xie, Doug A. Edwards	Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits.	DDECS	2010	DBLP DOI BibTeX RDF
1	Stylianos Siskos	Noise determination of a current conveyor in an inverting voltage amplifier configuration.	DDECS	2010	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen	Partitioning methods for unicast/multicast traffic in 3D NoC architecture.	DDECS	2010	DBLP DOI BibTeX RDF
1	Fabian Khateb, Dalibor Biolek, Nabhan Khatib, Jiri Vavra	Utilizing the Bulk-driven technique in analog circuit design.	DDECS	2010	DBLP DOI BibTeX RDF
1	Rolf Drechsler, Görschwin Fey	Formal verification meets robustness checking - Techniques and challenges.	DDECS	2010	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao 0010, Mohammad Tehranipoor, Xiaoqing Wen	Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.	DDECS	2010	DBLP DOI BibTeX RDF
1	Yngvar Berg	Ultra low-voltage bidirectional current mirror using clocked semi-floating-gate transistors.	DDECS	2010	DBLP DOI BibTeX RDF
1	Tomás Urban, Ondrej Subrt, Pravoslav Martínek	Versatile sub-bandgap reference IP core.	DDECS	2010	DBLP DOI BibTeX RDF
1	Thomas C. P. Chau, David W. L. Wu, Yanqing Ai, Brian P. W. Chan, Sam M. H. Ho, Oscar K. L. Lau, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Philip Heng Wai Leong	Design of a single layer programmable Structured ASIC library.	DDECS	2010	DBLP DOI BibTeX RDF
1	Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier	Fault diagnosis of crosstalk induced glitches and delay faults.	DDECS	2010	DBLP DOI BibTeX RDF
1	Jan Korenek, Vlastimil Kosar	Efficient mapping of nondeterministic automata to FPGA for fast regular expression matching.	DDECS	2010	DBLP DOI BibTeX RDF
1	Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel	Reduction of power dissipation through parallel optimization of test vector and scan register sequences.	DDECS	2010	DBLP DOI BibTeX RDF
1	Snorre Aunet, Amir Hasanbegovic	Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOS.	DDECS	2010	DBLP DOI BibTeX RDF
1	Tatjana R. Nikolic, Mile K. Stojcev, Zoran Stamenkovic	Wrapper design for a CDMA bus in SOC.	DDECS	2010	DBLP DOI BibTeX RDF
1	Heimo Uhrmann, Lukas Dörrer, Franz Kuttner, Kurt Schweiger, Horst Zimmermann	A mixer-filter combination of a direct conversion receiver for DVB-H applications in 65nm CMOS.	DDECS	2010	DBLP DOI BibTeX RDF
1	Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre	Ensuring high testability without degrading security: Embedded tutorial on "test and security".	DDECS	2010	DBLP DOI BibTeX RDF
1	Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki	Evaluation of transition untestable faults using a multi-cycle capture test generation method.	DDECS	2010	DBLP DOI BibTeX RDF
1	Bo Yang 0009, Thomas Canhao Xu, Tero Säntti, Juha Plosila	Tree-model based mapping for energy-efficient and low-latency Network-on-Chip.	DDECS	2010	DBLP DOI BibTeX RDF
1	Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler	Window optimization of reversible and quantum circuits.	DDECS	2010	DBLP DOI BibTeX RDF
1	Libor Majer, Viera Stopjaková	The novel approach to wideband RFIC receivers in standard CMOS process.	DDECS	2010	DBLP DOI BibTeX RDF
1	Nicola Campanelli, Tamas Kerekes, Paolo Bernardi, Mauricio de Carvalho, Alessandro Panariti, Matteo Sonza Reorda, Davide Appello, Mario Barone	Cumulative embedded memory failure bitmap display & analysis.	DDECS	2010	DBLP DOI BibTeX RDF
1	Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto	SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design.	DDECS	2010	DBLP DOI BibTeX RDF
1	Mario Schölzel	Software-based self-repair of statically scheduled superscalar data paths.	DDECS	2010	DBLP DOI BibTeX RDF
1	Viktor Pus, Juraj Blaho, Jan Korenek	Memory optimizations for packet classification algorithms in FPGA.	DDECS	2010	DBLP DOI BibTeX RDF
1	Ali Azarpeyvand, Mostafa E. Salehi, Farshad Firouzi, Amir Yazdanbakhsh, Sied Mehdi Fakhraie	Instruction reliability analysis for embedded processors.	DDECS	2010	DBLP DOI BibTeX RDF
1	Jiri Halak, Sven Ubik, Petr Zejdl	Receiver synchronization in video streaming with short latency over asynchronous networks.	DDECS	2010	DBLP DOI BibTeX RDF
1	Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann (eds.)	13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010	DDECS	2010	DBLP BibTeX RDF
1	Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka	How to reduce size of a signature-based diagnostic dictionary used for testing of connections.	DDECS	2010	DBLP DOI BibTeX RDF
1	Yngvar Berg, Omid Mirmotahari	Low voltage precharge CMOS logic.	DDECS	2009	DBLP DOI BibTeX RDF
1	Qing K. Zhu, Vincent Bars	Simulation and planning method for on-chip power distribution - An industry perspective.	DDECS	2009	DBLP DOI BibTeX RDF
1	Heimo Uhrmann, Franz Schlögl, Kurt Schweiger, Horst Zimmermann	A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOS.	DDECS	2009	DBLP DOI BibTeX RDF
1	Miloslav Kubar, Ondrej Subrt, Pravoslav Martínek, Jiri Jakovenko	Experience in Virtual Testing of RSD cyclic A/D converters.	DDECS	2009	DBLP DOI BibTeX RDF
1	Davide Bresolin, Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Tiziano Villa	The impact of EFSM composition on functional ATPG.	DDECS	2009	DBLP DOI BibTeX RDF
1	Stanislaw Deniziak, Robert Tomaszewski	Contention-avoiding custom topology generation for network-on-chip.	DDECS	2009	DBLP DOI BibTeX RDF
1	Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz	Enhanced LEON3 core for superscalar processing.	DDECS	2009	DBLP DOI BibTeX RDF
1	Farhad Alibeygi Parsan, Ahmad Ayatollahi, Adib Abrishamifar	Investigating the linearity of MOSFET-only switched-capacitor DeltaSigma modulators under low-voltage condition.	DDECS	2009	DBLP DOI BibTeX RDF
1	Grzegorz Borowik, Tadeusz Luba, Bogdan J. Falkowski	Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories.	DDECS	2009	DBLP DOI BibTeX RDF
1	Petr Kobierský, Jan Korenek, Libor Polcak	Packet header analysis and field extraction for multigigabit networks.	DDECS	2009	DBLP DOI BibTeX RDF
1	András Timár, György Bognár	Contactless characterization of MEMS devices using optical microscopy.	DDECS	2009	DBLP DOI BibTeX RDF
1	Daniel Tille, Rolf Drechsler	A fast untestability proof for SAT-based ATPG.	DDECS	2009	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean-Michel Portal, Hassen Aziza	An on-line testing scheme for repairing purposes in Flash memories.	DDECS	2009	DBLP DOI BibTeX RDF
1	Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz	Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS.	DDECS	2009	DBLP DOI BibTeX RDF
1	Alberto Yufera, Adoración Rueda	A CMOS bio-impedance measurement system.	DDECS	2009	DBLP DOI BibTeX RDF
1	Flavius Opritoiu, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan	Round-level concurrent error detection applied to Advanced Encryption Standard.	DDECS	2009	DBLP DOI BibTeX RDF
1	Martin Donoval, Martin Daricek, Juraj Marek, Viera Stopjaková	Power devices current monitoring using horizontal and vertical magnetic force sensor.	DDECS	2009	DBLP DOI BibTeX RDF
1	Yngvar Berg, Omid Mirmotahari	Ultra low-voltage switched current mirror.	DDECS	2009	DBLP DOI BibTeX RDF
1	Yun-Che Wen	Test scheme for switched-capacitor circuits by digital analyses.	DDECS	2009	DBLP DOI BibTeX RDF
1	P. Balasubramanian 0001, David A. Edwards, Charlie Brej	Self-timed full adder designs based on hybrid input encoding.	DDECS	2009	DBLP DOI BibTeX RDF
1	Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz	MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio.	DDECS	2009	DBLP DOI BibTeX RDF
1	Martin Rozkovec, Ondrej Novák	Structural test of programmed FPGA circuits.	DDECS	2009	DBLP DOI BibTeX RDF
1	Stefan Kolodzinski, Edward Hrynkiewicz	An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions.	DDECS	2009	DBLP DOI BibTeX RDF
1	Kameswar Rao Vaddina, Ethiopia Nigussie, Pasi Liljeberg, Juha Plosila	Self-timed thermal sensing and monitoring of multicore systems.	DDECS	2009	DBLP DOI BibTeX RDF
1	Thomas Reinbacher, Martin Horauer, Bastian Schlich	Using 3-valued memory representation for state space reduction in embedded assembly code model checking.	DDECS	2009	DBLP DOI BibTeX RDF
1	Miroslav Manik, Elena Gramatová	Diagnosis of faulty units in regular graphs under the PMC model.	DDECS	2009	DBLP DOI BibTeX RDF
1	Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada	All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.	DDECS	2009	DBLP DOI BibTeX RDF
1	Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus	A scheme of logic self repair including local interconnects.	DDECS	2009	DBLP DOI BibTeX RDF
1	Hong-Yi Huang, Fu-Chien Tsai	Analysis and optimization of ring oscillator using sub-feedback scheme.	DDECS	2009	DBLP DOI BibTeX RDF
1	Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute	Comprehensive bridging fault diagnosis based on the SLAT paradigm.	DDECS	2009	DBLP DOI BibTeX RDF
1	Brendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann	An SOC platform for ADC test and measurement.	DDECS	2009	DBLP DOI BibTeX RDF
1	Anton Chichkov	Challenges for test and design for test.	DDECS	2009	DBLP DOI BibTeX RDF
1	Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou 0001	Improve clock gating through power-optimal enable function selection.	DDECS	2009	DBLP DOI BibTeX RDF
1	Georges G. E. Gielen	Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS.	DDECS	2009	DBLP DOI BibTeX RDF
1		Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic	DDECS	2009	DBLP BibTeX RDF
1	Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng	0.5V 160-MHz 260uW all digital phase-locked loop.	DDECS	2009	DBLP DOI BibTeX RDF
1	Florence Azaïs, Yves Bertrand, Michel Renovell	An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions.	DDECS	2009	DBLP DOI BibTeX RDF
1	Stanislaw Deniziak, Mariusz Wisniewski	A symbolic RTL synthesis for LUT-based FPGAs.	DDECS	2009	DBLP DOI BibTeX RDF
1	Yiorgos Sfikas, Yiorgos Tsiatouhas	Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing.	DDECS	2009	DBLP DOI BibTeX RDF
1	Piotr Jantos, Damian Grzechca, Jerzy Rutkowski	Global parametric faults identification with the use of Differential Evolution.	DDECS	2009	DBLP DOI BibTeX RDF
1	Kurt Schweiger, Heimo Uhrmann, Horst Zimmermann	Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS.	DDECS	2009	DBLP DOI BibTeX RDF
1	Juraj Brenkus, Viera Stopjaková, Ronny Vanhooren, Anton Chichkov	Comparison of different test strategies on a mixed-signal circuit.	DDECS	2009	DBLP DOI BibTeX RDF
1	Elke De Mulder, Wim Aerts, Bart Preneel, Ingrid Verbauwhede, Guy A. E. Vandenbosch	Case Study : A class E power amplifier for ISO-14443A.	DDECS	2009	DBLP DOI BibTeX RDF
1	Peter Tummeltshammer, Andreas Steininger	On the role of the power supply as an entry for common cause faults - An experimental analysis.	DDECS	2009	DBLP DOI BibTeX RDF
1	Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre	High-level symbolic simulation for automatic model extraction.	DDECS	2009	DBLP DOI BibTeX RDF
1	Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda	Measurement of power supply noise tolerance of self-timed processor.	DDECS	2009	DBLP DOI BibTeX RDF
1	Werner Friesenbichler, Thomas Panhofer, Martin Delvai	A comprehensive approach for soft error tolerant Four State Logic.	DDECS	2009	DBLP DOI BibTeX RDF
1	Y. C. Chang, Hsuan-Ling Kao, C. H. Kao, C. H. Yang, Jeffrey S. Fu, Nemai C. Karmakar, Li-Chun Chang	0.18 µm CMOS UWB LNA with new feedback configuration for optimization low noise, high gain and small area.	DDECS	2009	DBLP DOI BibTeX RDF
1	Lyl M. Ciganda, Francesco Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda	An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs.	DDECS	2009	DBLP DOI BibTeX RDF
1	Abhijit Chatterjee	Cognitive self-adaptive computing and communication systems: Test, control and adaptation.	DDECS	2009	DBLP DOI BibTeX RDF
1	Jinpeng Zhao, Qiang Zhou 0001, Yici Cai	Fast congestion-aware timing-driven placement for island FPGA.	DDECS	2009	DBLP DOI BibTeX RDF

Publications at "DDECS"( http://dblp.L3S.de/Venues/DDECS )