Search results for "DFT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Michelle L. La Haye, Cory Jung, David Chen, Glenn H. Chapman, Jozsef Dudas	Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron Technologies.	DFT	2006	DBLP DOI BibTeX RDF
1	Ying-Yen Chen, Jing-Jia Liou	Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method.	DFT	2006	DBLP DOI BibTeX RDF
1	Xiaojun Ma, Fabrizio Lombardi	Multi-Site and Multi-Probe Substrate Testing on an ATE.	DFT	2006	DBLP DOI BibTeX RDF	substrate testing, multi-probe, ATE, MCM, manufacturing test, multi-site
1	Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone	Reliability Analysis of Self-Repairable MEMS Accelerometer.	DFT	2006	DBLP DOI BibTeX RDF
1	Salvatore Pontarelli, Marco Ottavi, Vamsi Vankamamidi, Adelio Salsano, Fabrizio Lombardi	Reliability Evaluation of Repairable/Reconfigurable FPGAs.	DFT	2006	DBLP DOI BibTeX RDF
1	Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier	Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects.	DFT	2006	DBLP DOI BibTeX RDF	defective interconnects, defect’s severity, fault model, crosstalk, bridging fault
1	Yukiya Miura, Jiro Kato	Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics.	DFT	2006	DBLP DOI BibTeX RDF
1	Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito	Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.	DFT	2006	DBLP DOI BibTeX RDF
1	Nandakumar P. Venugopal, Nihal Shastry, Shambhu J. Upadhyaya	Effect of Process Variation on the Performance of Phase Frequency Detector.	DFT	2006	DBLP DOI BibTeX RDF	Phase Frequency Detector (PFD), NFET, PFET, process variation, Monte Carlo simulation, Jitter, Phase noise
1	Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito	Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters.	DFT	2006	DBLP DOI BibTeX RDF
1	Christian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter	Recovery Mechanisms for Dual Core Architectures.	DFT	2006	DBLP DOI BibTeX RDF
1	David F. Heidel	Single-Event-Upset Trends in Advanced CMOS Technologies.	DFT	2006	DBLP BibTeX RDF
1	Joonhyuk Yoo, Manoj Franklin	The Filter Checker: An Active Verification Management Approach.	DFT	2006	DBLP DOI BibTeX RDF
1	Lei Fang 0002, Michael S. Hsiao	Bilateral Testing of Nano-scale Fault-tolerant Circuits.	DFT	2006	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Scan-Based Delay Fault Tests for Diagnosis of Transition Faults.	DFT	2006	DBLP DOI BibTeX RDF
1	Yusuke Fukushima, Masaru Fukushi, Susumu Horiguchi	An Improved Reconfiguration Method for Degradable Processor Arrays Using Genetic Algorithm.	DFT	2006	DBLP DOI BibTeX RDF
1	Kyriakos Christou, Maria K. Michael, Spyros Tragoudas	Implicit Critical PDF Test Generation with Maximal Test Efficiency.	DFT	2006	DBLP DOI BibTeX RDF
1		21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA	DFT	2006	DBLP BibTeX RDF
1	Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya	A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells.	DFT	2006	DBLP DOI BibTeX RDF
1	Rui Gong, Wei Chen 0009, Fang Liu 0002, Kui Dai, Zhiying Wang 0003	Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique.	DFT	2006	DBLP DOI BibTeX RDF
1	Federico Rota, Shantanu Dutt, Sahithi Krishna	Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream.	DFT	2006	DBLP DOI BibTeX RDF
1	Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande	NoC Interconnect Yield Improvement Using Crosspoint Redundancy.	DFT	2006	DBLP DOI BibTeX RDF
1	Reza M. Rad, Mohammad Tehranipoor	A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices.	DFT	2006	DBLP DOI BibTeX RDF	Nanoscale Devices, Fault Tolerance, Test, Reconfiguration, Redundancy, Crossbar
1	Yuejian Wu, André Ivanov	Low Power SoC Memory BIST.	DFT	2006	DBLP DOI BibTeX RDF
1	Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim	Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects.	DFT	2006	DBLP DOI BibTeX RDF
1	Marco Ottavi, Salvatore Pontarelli, A. Leandri, Adelio Salsano	Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers.	DFT	2006	DBLP DOI BibTeX RDF
1	Yasser Sedaghat, Seyed Ghassem Miremadi, Mahdi Fazeli	A Software-Based Error Detection Technique Using Encoded Signatures.	DFT	2006	DBLP DOI BibTeX RDF
1	Tadayoshi Horita, Takurou Murata, Itsuo Takanami	A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network.	DFT	2006	DBLP DOI BibTeX RDF	weight fault, neuron fault, fault tolerance, FPGA, VHDL, multilayer neural network
1	Hossein Asadi 0001, Mehdi Baradaran Tahoori	Soft Error Modeling and Protection for Sequential Elements.	DFT	2005	DBLP DOI BibTeX RDF
1	Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano	FPGA oriented design of parity sharing RS codecs.	DFT	2005	DBLP DOI BibTeX RDF
1	Mahdi Fazeli, Reza Farivar 0003, Seyed Ghassem Miremadi	A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems.	DFT	2005	DBLP DOI BibTeX RDF
1	Mariam Momenzadeh, Jing Huang 0001, Fabrizio Lombardi	Defect Characterization and Tolerance of QCA Sequential Devices and Circuits.	DFT	2005	DBLP DOI BibTeX RDF
1	Michael Wieckowski, John C. Liobe, Quentin Diduck, Martin Margala	A New Test Methodology For DNL Error In Flash ADC's.	DFT	2005	DBLP DOI BibTeX RDF
1	In Suk Chong, Antonio Ortega	Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms.	DFT	2005	DBLP DOI BibTeX RDF
1	Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic	Securing Scan Design Using Lock and Key Technique.	DFT	2005	DBLP DOI BibTeX RDF
1	Dilip P. Vasudevan, Parag K. Lala	A Technique for Modular Design of Self-Checking Carry-Select Adder.	DFT	2005	DBLP DOI BibTeX RDF
1		20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA	DFT	2005	DBLP BibTeX RDF
1	Erik Schüler, Luigi Carro	Reliable Digital Circuits Design using Sigma-Delta Modulated Signals.	DFT	2005	DBLP DOI BibTeX RDF
1	Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz	On Generating Pseudo-Functional Delay Fault Tests for Scan Designs.	DFT	2005	DBLP DOI BibTeX RDF
1	Bhushan Vaidya, Mehdi Baradaran Tahoori	Delay Test Generation with All Reachable Output Propagation and Multiple Excitations.	DFT	2005	DBLP DOI BibTeX RDF
1	Jinkyu Lee 0005, Nur A. Touba	Low Power BIST Based on Scan Partitioning.	DFT	2005	DBLP DOI BibTeX RDF
1	Zhaojun Wo, Israel Koren, Maciej J. Ciesielski	An ILP Formulation for Yield-driven Architectural Synthesis.	DFT	2005	DBLP DOI BibTeX RDF
1		Copyright.	DFT	2005	DBLP DOI BibTeX RDF
1	Siavash Bayat Sarmadi, M. Anwar Hasan	Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme.	DFT	2005	DBLP DOI BibTeX RDF
1	Chunsheng Liu, Kugesh Veeraraghavant, Vikram Iyengar	Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems.	DFT	2005	DBLP DOI BibTeX RDF
1	Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone	Design and Analysis of Self-Repairable MEMS Accelerometer.	DFT	2005	DBLP DOI BibTeX RDF
1	Masaru Fukushi, Yusuke Fukushima, Susumu Horiguchi	A Genetic Approach for the Reconfiguration of Degradable Processor Arrays.	DFT	2005	DBLP DOI BibTeX RDF
1	Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh	Methodologies and Algorithms for Testing Switch-Based NoC Interconnects.	DFT	2005	DBLP DOI BibTeX RDF
1	Lei Wu 0009, D. M. H. Walker	A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits.	DFT	2005	DBLP DOI BibTeX RDF
1	Vladimir Ostrovsky, Ilya Levin	Implementation of Concurrent Checking Circuits by Independent Sub-circuits.	DFT	2005	DBLP DOI BibTeX RDF
1	Leonard Lee, Sean H. Wu, Charles H.-P. Wen, Li-C. Wang	On Generating Tests to Cover Diverse Worst-Case Timing Corners.	DFT	2005	DBLP DOI BibTeX RDF
1	Hyukjune Chung, Antonio Ortega	Analysis and Testing for Error Tolerant Motion Estimation.	DFT	2005	DBLP DOI BibTeX RDF
1	Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi	Data Dependent Jitter (DDJ) Characterization Methodology.	DFT	2005	DBLP DOI BibTeX RDF
1	David M. Horan, Richard A. Guinee	A Novel Pulse Echo Correlation Tool for Transmission Path Testing and Fault Finding using Pseudorandom Binary Sequences.	DFT	2005	DBLP DOI BibTeX RDF
1	B. Saillet, Jean-Michel Portal, Didier Née	Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring.	DFT	2005	DBLP DOI BibTeX RDF
1	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment.	DFT	2005	DBLP DOI BibTeX RDF
1	Roberto Gómez 0001, Alejandro Girón, Víctor H. Champac	Test of Interconnection Opens Considering Coupling Signals.	DFT	2005	DBLP DOI BibTeX RDF
1	Fang Yu 0001, Chung-Hung Tsai, Yao-Wen Huang, D. T. Lee, Hung-Yau Lin, Sy-Yen Kuo	Efficient Exact Spare Allocation via Boolean Satisfiability.	DFT	2005	DBLP DOI BibTeX RDF
1	Luca Sterpone, Massimo Violante	A design flow for protecting FPGA-based systems against single event upsets.	DFT	2005	DBLP DOI BibTeX RDF
1	Zachary D. Patitz, Nohpill Park, Minsu Choi, Fred J. Meyer	QCA-Based Majority Gate Design under Radius of Effect-Induced Faults.	DFT	2005	DBLP DOI BibTeX RDF
1	Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali	Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems.	DFT	2005	DBLP DOI BibTeX RDF
1	Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara	Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes.	DFT	2005	DBLP DOI BibTeX RDF
1	Mariam Momenzadeh, Marco Ottavi, Fabrizio Lombardi	Modeling QCA Defects at Molecular-level in Combinational Circuits.	DFT	2005	DBLP DOI BibTeX RDF	fault model, emerging technology, defect tolerance, QCA
1	Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto	A model of soft error effects in generic IP processors.	DFT	2005	DBLP DOI BibTeX RDF
1	Cory Jung, Mohammad Hadi Izadi, Michelle L. La Haye	Noise Analysis of Fault Tolerant Active Pixel Sensors.	DFT	2005	DBLP DOI BibTeX RDF
1	Nisar Ahmed, Mohammad Tehranipoor	Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique.	DFT	2005	DBLP DOI BibTeX RDF
1		Message from the Symposium Chairs.	DFT	2005	DBLP DOI BibTeX RDF
1	Jeetendra Kumar, Mehdi Baradaran Tahoori	A Low Power Soft Error Suppression Technique for Dynamic Logic.	DFT	2005	DBLP DOI BibTeX RDF
1	Chin-Lung Su, Yi-Ting Yeh, Cheng-Wen Wu	An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement.	DFT	2005	DBLP DOI BibTeX RDF
1		Title Page.	DFT	2005	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Recovery During Concurrent On-Line Testing of Identical Circuits.	DFT	2005	DBLP DOI BibTeX RDF
1	G. Cellere, Alessandro Paccagnella, Angelo Visconti, Mauro Bonanomi	Soft Errors induced by single heavy ions in Floating Gate memory arrays.	DFT	2005	DBLP DOI BibTeX RDF
1		Committees.	DFT	2005	DBLP DOI BibTeX RDF
1	Masato Kitakami, Manabu Sueishi	Fault-Tolerant Wormhole Switching with Backtracking Capability.	DFT	2005	DBLP DOI BibTeX RDF
1	Cecilia Metra, Martin Omaña 0001, Daniele Rossi 0001, José Manuel Cazeaux, T. M. Mak	The Other Side of the Timing Equation: a Result of Clock Faults.	DFT	2005	DBLP DOI BibTeX RDF
1	Glenn H. Chapman, Israel Koren, Zahava Koren, Jozsef Dudas, Cory Jung	On-Line Identification of Faults in Fault-Tolerant Imagers.	DFT	2005	DBLP DOI BibTeX RDF
1	Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors.	DFT	2005	DBLP DOI BibTeX RDF
1	Haruhiko Kaneko	Error Control Coding for Semiconductor Memory Systems in the Space Radiation Environment.	DFT	2005	DBLP DOI BibTeX RDF
1	Miltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis	Software-Based Self-Test for Pipelined Processors: A Case Study.	DFT	2005	DBLP DOI BibTeX RDF
1	Enkelejda Tafaj, Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty	Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling.	DFT	2005	DBLP DOI BibTeX RDF
1	Wei Zhang 0002	Computing Cache Vulnerability to Transient Errors and Its Implication.	DFT	2005	DBLP DOI BibTeX RDF
1	Shaolei Quan, Meng-Yao Liu, Chin-Long Wey	Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress.	DFT	2005	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda	Should Illinois-Scan Based Architectures be Centralized or Distributed?	DFT	2005	DBLP DOI BibTeX RDF
1	Jia Di, Parag K. Lala, Dilip P. Vasudevan	On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.	DFT	2005	DBLP DOI BibTeX RDF
1	Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano	A Self Checking Reed Solomon Encoder: Design and Analysis.	DFT	2005	DBLP DOI BibTeX RDF
1	Kyung Ki Kim, Jing Huang 0001, Yong-Bin Kim, Fabrizio Lombardi	On the Modeling and Analysis of Jitter in ATE Using Matlab.	DFT	2005	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori	Defects, Yield, and Design in Sublithographic Nano-electronics.	DFT	2005	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors.	DFT	2005	DBLP DOI BibTeX RDF
1	Song Peng, Rajit Manohar	Efficient Failure Detection in Pipelined Asynchronous Circuits.	DFT	2005	DBLP DOI BibTeX RDF
1	Yukiya Miura	Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test.	DFT	2005	DBLP DOI BibTeX RDF
1	Sadeka Ali, Gregory Briggs, Martin Margala	A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test.	DFT	2005	DBLP DOI BibTeX RDF
1	Daniele Rossi 0001, Martin Omaña 0001, Fabio Toma, Cecilia Metra	Multiple Transient Faults in Logic: An Issue for Next Generation ICs.	DFT	2005	DBLP DOI BibTeX RDF
1	Mohammad Tehranipoor	Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure.	DFT	2005	DBLP DOI BibTeX RDF
1	Samuel I. Ward, Chris Schattauer, Nur A. Touba	Using Statistical Transformations to Improve Compression for Linear Decompressors.	DFT	2005	DBLP DOI BibTeX RDF
1	Luca Breveglieri, Israel Koren, Paolo Maistri	Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard.	DFT	2005	DBLP DOI BibTeX RDF
1	Tejasvi Das, Anand Gopalan, Clyde Washburn, P. R. Mukund	Dynamic Input Match Correction in RF Low Noise Amplifiers.	DFT	2004	DBLP DOI BibTeX RDF
1	Shi-Yu Huang	A Fading Algorithm For Sequential Fault Diagnosis.	DFT	2004	DBLP DOI BibTeX RDF
1		19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings	DFT	2004	DBLP BibTeX RDF
1	Yinhe Han 0001, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001, Anshuman Chandra	Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.	DFT	2004	DBLP DOI BibTeX RDF
1	Ireneusz Gosciniak	A New Approach to Linear Connections Building BIST Structure Based on CSTP Structure.	DFT	2004	DBLP DOI BibTeX RDF

Publications at "DFT"( http://dblp.L3S.de/Venues/DFT )