Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Aarti Gupta, Zijiang Yang 0006, Pranav Ashar, Anubhav Gupta 0001 |
SAT-Based Image Computation with Application in Reachability Analysis. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Jun Sawada, Warren A. Hunt Jr. |
Hardware Modeling Using Function Encapsulation. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Warren A. Hunt Jr., Steven D. Johnson (eds.) |
Formal Methods in Computer-Aided Design, Third International Conference, FMCAD 2000, Austin, Texas, USA, November 1-3, 2000, Proceedings |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Per Bjesse, Koen Claessen |
SAT-Based Verification without State Space Traversal. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Rajeev Alur, Radu Grosu, Bow-Yaw Wang |
Automated Refinement Checking for Asynchronous Processes. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Mark E. Dean |
Trends in Computing. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Nancy A. Day, Mark D. Aagaard, Byron Cook |
Combining Stream-Based and State-Based Verification Techniques. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Panagiotis Manolios |
Correctness of Pipelined Machines. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Mary Sheeran, Satnam Singh, Gunnar Stålmarck |
Checking Safety Properties Using Induction and a SAT-Solver. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Antonio Cerone, George J. Milne |
A Methodology for the Formal Analysis of Asynchronous Micropipelines. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Robert Beers, Rajnish Ghughal, Mark D. Aagaard |
Applications of Hierarchical Verification in Model Checking. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Alex Tsow, Steven D. Johnson |
Visualizing System Factorizations with Behavior Tables. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Randal E. Bryant, Pankaj Chauhan, Edmund M. Clarke, Amit Goel |
A Theory of Consistency for Modular Synchronous Systems. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Roderick Bloem, Harold N. Gabow, Fabio Somenzi |
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Wolfgang Reif, Jürgen Ruf, Gerhard Schellhorn, Tobias Vollmer |
Do You Trust Your Model Checker? |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Mary Sheeran, Gunnar Stålmarck |
A Tutorial on Stålmarcks's Proof Procedure for Propositional Logic. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Amir Pnueli, Tamarah Arons |
Verification of Data-Insensitive CIrcuits: An In-Order-Retirement Case Study. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Jeffrey X. Su, David L. Dill, Jens U. Skakkebæk |
Formally Verifying Data and Control with Weak Reachability Invariants. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Macha Nikolskaïa, Antoine Rauzy, David James Sherman |
Almana: A BDD Minimization Tool Integrating Heuristic and Rewriting Methods. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Klaus Schneider 0001 |
Model Checking on Product Structures. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Ganesh Gopalakrishnan, Phillip J. Windley (eds.) |
Formal Methods in Computer-Aided Design, Second International Conference, FMCAD '98, Palo Alto, California, USA, November 4-6, 1998, Proceedings |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | J Strother Moore |
Symbolic Simulation: An ACL2 Approach. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Jürgen Ruf, Thomas Kropf |
Using MTBDDs for Compostion and Model Checking of Real-Time Systems. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Justin E. Harlow III, Franc Brglez |
Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | James H. Kukula, Thomas R. Shiple, Adnan Aziz |
Techniques for Implicit State Enumeration of EFSMs. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | F. Keith Hanna |
Automatic Verification of Mixed-Level Logic Circuits. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Abdelillah Mokkedem, Ravi Hosabettu, Ganesh Gopalakrishnan |
Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | M. Oliver Möller, Harald Rueß |
Solving Bit-Vector Equations. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Kenneth L. McMillan |
Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification (abstract). |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Miroslav N. Velev, Randal E. Bryant |
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Nazanin Mansouri, Ranga Vemuri |
A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Kim Milvang-Jensen, Alan J. Hu |
BDDNOW: A Parallel BDD Package. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Robert B. Jones, Jens U. Skakkebæk, David L. Dill |
Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Gila Kamhi, Limor Fix, Ziv Binyamini |
Symbolic Model Checking Visualization. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | C. Norris Ip |
Generalized Reversible Rules. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Sofiène Tahar, Paul Curzon, Jianping Lu |
Three Approaches to Hardware Verification: HOL, MDG and VIS Compared. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Ratan Nalumasu, Ganesh Gopalakrishnan |
PV: An Explicit Enumeration Model-Checker. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Carl-Johan H. Seger |
Formal Methods in CAD from an Industrial Perspective (abstract). |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran |
An Assume-Guarantee Rule for Checking Simulation. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | David A. Greve |
Symbolic Simulation of the JEM1 Microprocessor. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | David Déharbe, Subash Shankar, Edmund M. Clarke |
Model Checking VHDL with CV. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Shiu-Kai Chin, Jang Dae Kim |
An Instruction Set Process Calculus. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Sela Mador-Haim, Limor Fix |
Input Elimination and Abstraction in Model Checking. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Sergey Berezin, Armin Biere, Edmund M. Clarke, Yunshan Zhu |
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Ásgeir Th. Eiríksson |
The Formal Design of 1M-gate ASICs. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Fen Jin, Henrik Hulgaard, Eduard Cerny |
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Annette Bunker, Trent N. Larson, Michael D. Jones, Phillip J. Windley |
Alexandria: A Tool for Hierarchical Verification. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Bwolen Yang, Randal E. Bryant, David R. O'Hallaron, Armin Biere, Olivier Coudert, Geert Janssen, Rajeev K. Ranjan 0001, Fabio Somenzi |
A Performance Study of BDD-Based Model Checking. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Thomas Lock, Michael Mendler, Matthias Mutz |
Combined Formal Post- and Presynthesis Verification in High Level Synthesis. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Kathi Fisler, Moshe Y. Vardi |
Bisimulation Minimization in an Automata-Theoretic Verification Framework. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Laurent Arditi |
BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Naren Narasimhan, Ranga Vemuri |
Specification of Control Flow Properties for Verification of Synthesized VHDL Designs. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Clark W. Barrett, David L. Dill, Jeremy R. Levitt |
Validity Checking for Combinations of Theories with Equality. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Phillip J. Windley, Jerry R. Burch |
Mechanically Checking a Lemma Used in an Automatic Verification Tool. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Christoph Meinel, Thorsten Theobald |
Local Encoding Transformations for Optimizing OBDD-Representations of Finite State Machines. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Yirng-An Chen, Edmund M. Clarke, Pei-Hsin Ho, Yatin Vasant Hoskote, Timothy Kam, Manpreet Khaira, John W. O'Leary, Xudong Zhao 0005 |
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan 0001, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa |
VIS. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Geist, Monica Farkas, Avner Landver, Yossi Lichtenstein, Shmuel Ur, Yaron Wolfsthal |
Coverage-Directed Test Generation Using Symbolic Techniques. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Anthony C. J. Fox, Neal A. Harman |
An Algebraic Model of Correctness for Superscalar Microprocessors. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Mark Bickford, Damir Jamsek |
Formal Specification and Verification of VHDL. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Alok Jain, Kyle L. Nelson, Randal E. Bryant |
Verifying Nondeterministic Implementations of Deterministic Systems. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Dominique Borrione, H. Bouamama, David Déharbe, C. Le Faou, Ayman M. Wahba |
HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Ramayya Kumar, Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid |
Formal Synthesis in Circuit Design - A Classification and Survey. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Jawahar Jain, Amit Narayan, C. Coelho 0001, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita |
Decomposition Techniques for Efficient ROBDD Construction. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Jeffrey X. Su, David L. Dill, Clark W. Barrett |
Automatic Generation of Invariants in Processor Verification. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Bishop Brock, Matt Kaufmann, J Strother Moore |
ACL2 Theorems About Commercial Microprocessors. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Ramin Hojati, Adrian J. Isles, Desmond Kirkpatrick, Robert K. Brayton |
Verification Using Uninterpreted Functions and Finite Instantiations. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Kavita Ravi, Abelardo Pardo, Gary D. Hachtel, Fabio Somenzi |
Modular Verification of Multipliers. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Kurt Keutzer |
The Need for Formal Methods for Integrated Circuit Design. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | John Harrison 0001 |
HOL Light: A Tutorial Introduction. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Francisco J. Cantu, Alan Bundy, Alan Smaill, David A. Basin |
Experiments in Automating Hardware Verification Using Inductive Proof Planning. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Robert B. Jones, Carl-Johan H. Seger, David L. Dill |
Self-Consistency Checking. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Mandayam K. Srivas, Albert John Camilleri (eds.) |
Formal Methods in Computer-Aided Design, First International Conference, FMCAD '96, Palo Alto, California, USA, November 6-8, 1996, Proceedings |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Klaus Schneider 0001, Thomas Kropf |
A Unified Approach for Combining Different Formalisms for Hardware Verification. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Lewin 0001, Dean H. Lorenz, Shmuel Ur |
A Methodology for Processor Implementation Verification. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Ellen Sentovich |
A Brief Study of BDD Package Performance. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Harald Rueß |
Hierarchical Verification of Two-Dimensional High-Speed Multiplication in PVS: A Case Study. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Tomohiro Yoneda, Hideyuki Hatori, Atsushi Takahara, Shin-ichi Minato |
BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | David Cyrluk |
Inverting the Abstraction Mapping: A Methodology for Hardware Verification. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Paul S. Miner, James F. Leathrum |
Verification of IEEE Compliant Subtractive Division Algorithms. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Zijian Zhou 0001, Xiaoyu Song, Sofiène Tahar, Eduard Cerny, Francisco Corella, Michel Langevin |
Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Bhaskar Bose, M. Esen Tuna, Venkatesh Choppella |
A Tutorial on Digital Design Derivation Using DRS. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Natarajan Shankar |
PVS: Combining Specification, Proof Checking, and Model Checking. |
FMCAD |
1996 |
DBLP DOI BibTeX RDF |
|