Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link
26	Sajjad Taheri, Payman Behnam, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alexandru Nicolau	AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms.	FPGA	2019	DBLP DOI BibTeX RDF
26	Yun Zhou, Dries Vercruyce, Dirk Stroobandt	MODA-PSO: Towards Fast Hard Block Legalization for Analytical FPGA Placement.	FPGA	2019	DBLP DOI BibTeX RDF
26	Andrew M. Keller, Michael J. Wirthlin	Impact of Soft Errors on Large-Scale FPGA Cloud Computing.	FPGA	2019	DBLP DOI BibTeX RDF
26	Zhucheng Tang, Guojie Luo, Ming Jiang 0001	FTConv: FPGA Acceleration for Transposed Convolution Layers in Deep Neural Networks.	FPGA	2019	DBLP DOI BibTeX RDF
26	Tushar Garg, Saud Wasly, Rodolfo Pellizzoni, Nachiket Kapre	HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOs.	FPGA	2019	DBLP DOI BibTeX RDF
26	Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual	Scalable High Performance SDN Switch Architecture on FPGA for Core Networks.	FPGA	2019	DBLP DOI BibTeX RDF
26	Zheming Jin, Hal Finkel	Nuclear Reactor Simulations on OpenCL FPGA Platform.	FPGA	2019	DBLP DOI BibTeX RDF
26	Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang	Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System.	FPGA	2019	DBLP DOI BibTeX RDF
26	Jiafeng Xie, Chiou-Yng Lee	Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity.	FPGA	2019	DBLP DOI BibTeX RDF
26	Maciej Besta, Marc Fischer, Tal Ben-Nun, Johannes de Fine Licht, Torsten Hoefler	Substream-Centric Maximum Matchings on FPGA.	FPGA	2019	DBLP DOI BibTeX RDF
26	Lansong Diao, Zhao Jiang, Hao Liang, Chang'an Ye, Kai Chen 0008, Li Ding, Shunli Dou, Meng Sun, Lixue Xia, Jiansong Zhang, Wei Lin 0016	PAI-FCNN: FPGA Based CNN Inference System.	FPGA	2019	DBLP DOI BibTeX RDF
26	Katie Lim, Jonathan Balkind, David Wentzlaff	JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores.	FPGA	2019	DBLP DOI BibTeX RDF
26	Jyotikrishna Dass, Yashwardhan Narawane, Rabi N. Mahapatra, Vivek Sarin	FPGA-based Distributed Edge Training of SVM.	FPGA	2019	DBLP DOI BibTeX RDF
26	Chia-Wei Chang, Zi-Qi Zhong, Jing-Jia Liou	A FPGA Implementation of Farneback Optical Flow by High-Level Synthesis.	FPGA	2019	DBLP DOI BibTeX RDF
26	Tom J. Mannos, Brian Dziki, Moslema Sharif	Fault Testing a Synthesizable Embedded Processor at Gate Level using UltraScale FPGA Emulation.	FPGA	2019	DBLP DOI BibTeX RDF
26	Cheng Fu, Shilin Zhu, Hao Su 0001, Ching-En Lee, Jishen Zhao	Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA.	FPGA	2019	DBLP DOI BibTeX RDF
26	Carl-Johannes Johnsen, Kenneth Skovhede	Building FPGA State Machines from Sequential Code.	FPGA	2019	DBLP DOI BibTeX RDF
26	Venkat Konda	Flat FPGA Fabrics Derived from 2D-Benes-BFT-Pyramid Networks with Optimizations and Enhancements.	FPGA	2019	DBLP DOI BibTeX RDF
26	Shijie Cao, Chen Zhang 0001, Zhuliang Yao, Wencong Xiao, Lanshun Nie, De-chen Zhan, Yunxin Liu, Ming Wu 0007, Lintao Zhang	Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced Sparsity.	FPGA	2019	DBLP DOI BibTeX RDF
26	Anping He, Jinlin Zhang, Lvying Yu, Pengfei Li, Lian Li	How to Accelerate FPGA Application in an Asynchronous Way?	FPGA	2019	DBLP DOI BibTeX RDF
26	Kaiyuan Guo, Shuang Liang 0010, Jincheng Yu, Xuefei Ning, Wenshuo Li, Yu Wang 0002, Huazhong Yang	Compressed CNN Training with FPGA-based Accelerator.	FPGA	2019	DBLP DOI BibTeX RDF
26	Sahand Salamat, Mohsen Imani, Behnam Khaleghi, Tajana Rosing	F5-HD: Fast Flexible FPGA-based Framework for Refreshing Hyperdimensional Computing.	FPGA	2019	DBLP DOI BibTeX RDF
26	Zhiyuan Shao, Ruoshi Li, Diqing Hu, Xiaofei Liao, Hai Jin 0001	Improving Performance of Graph Processing on FPGA-DRAM Platform by Two-level Vertex Caching.	FPGA	2019	DBLP DOI BibTeX RDF
26	Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato	An FPGA-based Fine Tuning Accelerator for a Sparse CNN.	FPGA	2019	DBLP DOI BibTeX RDF
26	Elham Azari, Aykut Dengi, Sarma B. K. Vrudhula	An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing.	FPGA	2019	DBLP DOI BibTeX RDF
26	Dan Cristian Turicu, Octavian Cret, Lucia Vacariu	Storage Mirroring for Bare-Metal Systems on FPGA Devices.	FPGA	2019	DBLP DOI BibTeX RDF
26	Lu Jing, Jun Liu, FuHai Yu	A Deep Learning Inference Accelerator Based on Model Compression on FPGA.	FPGA	2019	DBLP DOI BibTeX RDF
26	Venkat Konda	Hierarchical FPGA Fabrics using 2D-Benes-BFT-Pyramid Network Layouts with Optimizations.	FPGA	2019	DBLP DOI BibTeX RDF
26	Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton	On-chip FPGA Debug Instrumentation for Machine Learning Applications.	FPGA	2019	DBLP DOI BibTeX RDF
26	Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong	A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.	FPGA	2018	DBLP DOI BibTeX RDF
26	Ning Mao, Zhihong Huang, Xing Wei, He Zhao, Xinkai Di, Le Yu, Haigang Yang	A Self-adaptation Method of Fitting Convolutional Neural Network into FPGA: Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Jason Cong, Zhenman Fang, Yao Hu, Di Wu 0010	K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Stephen M. Williams, Mingjie Lin	Architecture and Circuit Design of an All-Spintronic FPGA.	FPGA	2018	DBLP DOI BibTeX RDF
26	Wenyi Feng, Jonathan W. Greene, Alan Mishchenko	Improving FPGA Performance with a S44 LUT Structure.	FPGA	2018	DBLP DOI BibTeX RDF
26	Ho-Cheung Ng, Shuanglong Liu, Wayne Luk	ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development.	FPGA	2018	DBLP DOI BibTeX RDF
26	Zheming Jin, Kazutomo Yoshii	Optimizations of Sequence Alignment on FPGA: A Case Study of Extended Sequence Alignment (Abstact Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Juexiao Su, Lei He 0001	Solving Satisfiability Problem on Quantum Annealer: A Lesson from FPGA CAD Tools: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Shuanglong Liu, Xinyu Niu, Wayne Luk	A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only.	FPGA	2018	DBLP DOI BibTeX RDF
26	Soroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li 0073	Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform.	FPGA	2018	DBLP DOI BibTeX RDF
26	Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek	Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.	FPGA	2018	DBLP DOI BibTeX RDF
26	Luka Daoud, Muhammad Kamran Latif, Nader Rafla 0001	SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Yankang Du, Qinrang Liu, Shuai Wei, Chen Gao	Software-Defined FPGA-Based Accelerator for Deep Convolutional Neural Networks: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang	Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA.	FPGA	2018	DBLP DOI BibTeX RDF
26	Nachiket Kapre, Tushar Krishna	FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Jan Dürre, Dario Paradzik, Holger Blume	A HOG-based Real-time and Multi-scale Pedestrian Detector Demonstration System on FPGA.	FPGA	2018	DBLP DOI BibTeX RDF
26	Daisuke Suzuki, Takahiro Hanyu	Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Jialiang Zhang, Jing Li 0073	Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform.	FPGA	2018	DBLP DOI BibTeX RDF
26	Zheming Jin, Hal Finkel	Evaluation of OpenCL Performance-oriented Optimizations for Streaming Kernels on the FPGA: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Greg Stitt, Abhay Gupta, Madison N. Emas, David Wilson 0004, Austin Baylis	Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems.	FPGA	2018	DBLP DOI BibTeX RDF
26	Weikang Qiao, Jieqiong Du, Zhenman Fang, Libo Wang, Michael Lo, Mau-Chung Frank Chang, Jason Cong	High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Zhe Chen, Andrew Howe, Hugh T. Blair, Jason Cong	FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato	A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA.	FPGA	2018	DBLP DOI BibTeX RDF
26	Shijie Zhou 0001, Rajgopal Kannan, Yu Min, Viktor K. Prasanna	FASTCF: FPGA-based Accelerator for STochastic-Gradient-Descent-based Collaborative Filtering.	FPGA	2018	DBLP DOI BibTeX RDF
26	Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, Li Jiang 0002	A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Gai Liu, Ecenur Ustun, Shaojie Xiang, Chang Xu 0005, Guojie Luo, Zhiru Zhang	DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Sean Fox, David Boland, Philip Heng Wai Leong	FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method.	FPGA	2018	DBLP DOI BibTeX RDF
26	Ruizhe Zhao, Xinyu Niu, Wayne Luk	Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only).	FPGA	2018	DBLP DOI BibTeX RDF
26	Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton	Architecture Exploration for HLS-Oriented FPGA Debug Overlays.	FPGA	2018	DBLP DOI BibTeX RDF
26	Jialiang Zhang, Jing Li	Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network.	FPGA	2017	DBLP BibTeX RDF
26	Chi Zhang 0022, Viktor K. Prasanna	Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System.	FPGA	2017	DBLP BibTeX RDF
26	Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer	Automatic Construction of Program-Optimized FPGA Memory Networks.	FPGA	2017	DBLP BibTeX RDF
26	Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang	NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element.	FPGA	2017	DBLP BibTeX RDF
26	Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois	An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
26	Srinivas Siripurapu, Aman Gayasen, Padmini Gopalakrishnan, Nitin Chandrachoodan	FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
26	Xin Fang 0001, Stratis Ioannidis, Miriam Leeser	Secure Function Evaluation Using an FPGA Overlay Architecture.	FPGA	2017	DBLP BibTeX RDF
26	Jialiang Zhang, Soroosh Khoram, Jing Li 0073	Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search.	FPGA	2017	DBLP BibTeX RDF
26	Haoyang Wu, Tao Wang 0004, Zhiwei Li, Boyan Ding, Xiaoguang Li, Tianfu Jiang, Jun Liu 0063, Songwu Lu	GRT 2.0: An FPGA-based SDR Platform for Cognitive Radio Networks (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
26	Minghua Shen, Guojie Luo	Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic Expansion.	FPGA	2017	DBLP BibTeX RDF
26	Xiaoyu Ma, Dan Zhang 0004, Derek Chiou	FPGA-Accelerated Transactional Execution of Graph Workloads.	FPGA	2017	DBLP BibTeX RDF
26	Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura	A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
26	Emanuele Pezzotti, Alex Iacobucci, Gregory Nash, Umer I. Cheema, Paolo Vinella, Rashid Ansari	FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic Resonance Imaging (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
26	Yufei Ma 0002, Yu Cao 0001, Sarma B. K. Vrudhula, Jae-sun Seo	Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.	FPGA	2017	DBLP BibTeX RDF
26	Chang Xu 0005, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, Zhiru Zhang	A Parallel Bandit-Based Approach for Autotuning FPGA Compilation.	FPGA	2017	DBLP BibTeX RDF
26	Yixing Li, Zichuan Liu, Kai Xu 0007, Hao Yu 0001, Fengbo Ren	A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
26	Guohao Dai, Tianhao Huang, Yuze Chi, Ningyi Xu, Yu Wang 0002, Huazhong Yang	ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture.	FPGA	2017	DBLP BibTeX RDF
26	Naif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow	Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center.	FPGA	2017	DBLP BibTeX RDF
26	Zhuolun He, Guojie Luo	FPGA Acceleration for Computational Glass-Free Displays.	FPGA	2017	DBLP BibTeX RDF
26	Yanqiang Liu, Yao Li 0004, Weilun Xiong, Meng Lai, Cheng Chen, Zhengwei Qi, Haibing Guan	Scala Based FPGA Design Flow (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
26	Jason Cong, Zhenman Fang, Muhuan Huang, Libo Wang, Di Wu 0010	CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
26	Gary William Grewal, Shawki Areibi, Matthew Westrik, Ziad Abuowaimer, Betty Zhao	A Machine Learning Framework for FPGA Placement (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
26	Song Han 0003, Junlong Kang, Huizi Mao, Yiming Hu, Xin Li, Yubin Li, Dongliang Xie, Hong Luo, Song Yao, Yu Wang 0002, Huazhong Yang, William (Bill) J. Dally	ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA.	FPGA	2017	DBLP BibTeX RDF
26	Mostafa Koraei, Magnus Jahre, S. Omid Fatemi	Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
26	Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet	Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
26	Chethan Kumar H. B, Prashant Ravi, Gourav Modi, Nachiket Kapre	120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board.	FPGA	2017	DBLP BibTeX RDF
26	Hanyang Xu, Jian Wang 0036, Meilai Jin	A FPGA prototype design emphasis on low power technique.	FPGA	2014	DBLP DOI BibTeX RDF
26	Tao Ai, Mir Adnan Ali, J. Gregory Steffan, Kalin Ovtcharov, Sarmad Zulfiqar, Steve Mann 0001	Producing high-quality real-time HDR video system with FPGA (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Lei Li, Jian Wang 0036, Jinmei Lai	Novel FPGA clock network with low latency and skew (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Zhibin Wang, Wenmin Yang, Jin Yu, Zhilei Chai	Implementing FPGA-based energy-efficient dense optical flow computation with high portability in C (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Sen Ma, David Andrews 0001	On energy efficiency and amdahl's law in FPGA based chip heterogeneous multiprocessor systems (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue	Memory block based scan-BIST architecture for application-dependent FPGA testing.	FPGA	2014	DBLP DOI BibTeX RDF
26	Safeen Huda, Jason Helge Anderson, Hirotaka Tamura	Optimizing effective interconnect capacitance for FPGA power reduction.	FPGA	2014	DBLP DOI BibTeX RDF
26	Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado	A power-efficient adaptive heapsort for fpga-based image coding application (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Yuliang Sun, Zilong Wang, Sitao Huang, Lanjun Wang, Yu Wang 0002, Rong Luo, Huazhong Yang	Accelerating frequent item counting with FPGA.	FPGA	2014	DBLP DOI BibTeX RDF
26	André Hahn Pereira, Vaughn Betz	Cad and routing architecture for interposer-based multi-FPGA systems.	FPGA	2014	DBLP DOI BibTeX RDF
26	Jian Gong, Jiahua Chen, Haoyang Wu, Fan Ye 0003, Songwu Lu, Jason Cong, Tao Wang 0004	EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Yu Wang 0136, Donghoon Yeo, Muhammad Sohail 0003, Hyunchul Shin	Control signal aware slice-level window based legalization method for FPGA placement (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Viktor Pus, Lukas Kekely, Tomás Závodník	Using DSP blocks to compute CRC hash in FPGA (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Georgios Smaragdos, Sebastián Isaza, Martijn F. van Eijk, Ioannis Sourdis, Christos Strydis	FPGA-based biophysically-meaningful modeling of olivocerebellar neurons.	FPGA	2014	DBLP DOI BibTeX RDF
26	Yu Bai 0004, Mohammed Alawad, Mingjie Lin	Optimally mitigating BTI-induced FPGA device aging with discriminative voltage scaling (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Qian Zhang 0020, Chenfei Ma, Qiang Xu 0001	On hybrid memory allocation for FPGA behavioral synthesis (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF