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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 429 occurrences of 291 keywords
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Results
Found 709 publication records. Showing 709 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
10 | Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung |
A C-Based RTL Design Verification Methodology for Complex Microprocessor. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
C |
10 | Wen-Jong Fang, Allen C.-H. Wu |
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
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10 | Tsung-Yi Wu, Youn-Long Lin |
Register minimization beyond sharing among variables. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1996 |
DBLP DOI BibTeX RDF |
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10 | Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer |
A Design For Test Perspective on I/O Management. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
I/O pads, High Level Synthesis, Design For Test, Boundary Scan |
10 | Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell |
Automated verification of temporal properties specified as state machines in VHDL. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
automated verification methodology, correctness specifications, Viper microprocessor, Mealy FSM, compatible states, formal specification, formal verification, high level synthesis, finite state machines, VHDL, sequential circuits, state machines, hardware description languages, microprocessor chips, synchronous sequential circuit, temporal properties, liveness properties |
10 | Vivek Chickermane, Jaushin Lee, Janak H. Patel |
Addressing design for testability at the architectural level. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
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10 | Hans Eveking |
Automatic Verification of Extensions of Hardware Descriptions. |
CAV |
1990 |
DBLP DOI BibTeX RDF |
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10 | S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter |
A Fast Signature Simulation Tool for Built-In Self-Testing Circuits. |
DAC |
1987 |
DBLP DOI BibTeX RDF |
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10 | Daniel S. Barclay, James R. Armstrong |
A heuristic chip-level test generation algorithm. |
DAC |
1986 |
DBLP DOI BibTeX RDF |
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Displaying result #701 - #709 of 709 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8] |
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