| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor, Wim Dehaene |
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability.  |
ISVLSI  |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammed Ceylan Morgül, Furkan Peker, Mustafa Altun |
Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinamra Benara, Suresh Purini |
Accurus: A Fast Convergence Technique for Accuracy Configurable Approximate Adder Circuits. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Te-Hsuan Chen, John P. Hayes |
Design of Division Circuits for Stochastic Computing. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Madhav Rao, Neha Oraon |
Analysis of Switching Energy and Delay for Magnetic Logic Devices. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test Set. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Alec Roelke, Mircea R. Stan |
Attacking an SRAM-Based PUF through Wearout. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Song Yao, Song Han 0003, Yu Wang 0002, Huazhong Yang |
Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao-Ting Shen, Fahim Rahman, Bicky Shakya, Mark M. Tehranipoor, Domenic Forte |
Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs). |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario Barbareschi, Federico Iannucci, Antonino Mazzeo |
A Pruning Technique for B&B Based Design Exploration of Approximate Computing Variants. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Bowen Zheng, Hengyi Liang, Qi Zhu 0002, Huafeng Yu, Chung-Wei Lin |
Next Generation Automotive Architecture Modeling and Exploration for Autonomous Driving. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Ranjan Trivedi, Susmita Dey Manasi |
A Comparative Study of Si/Ge and GaSb/InAs Tunnel FET-Based Cellular Neural Network. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Siva Nishok Dhanuskodi, Shahrzad Keshavarz, Daniel E. Holcomb |
LLPA: Logic State Based Leakage Power Analysis. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta 0001 |
Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Xuanle Ren, Ronald D. Blanton, Vítor Grade Tavares |
A Learning-Based Approach to Secure JTAG Against Unseen Scan-Based Attacks. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Honglan Jiang, Chengkun Shen, Pieter P. Jonker, Fabrizio Lombardi, Jie Han 0001 |
Adaptive Filter Design Using Stochastic Circuits. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Tso-Bing Juang, Ying-Ren Lee |
Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Solazzo, Emanuele Del Sozzo, Irene De Rose, Matteo De Silvestri, Gianluca C. Durelli, Marco D. Santambrogio |
Hardware Design Automation of Convolutional Neural Networks. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Attila Kinali, Florian Huemer, Christoph Lenzen 0001 |
Fault-Tolerant Clock Synchronization with High Precision. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaveh Shamsi, Wujie Wen, Yier Jin |
Hardware Security Challenges Beyond CMOS: Attacks and Remedies. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad, Vijay Singh, Kalyan S. Perumalla |
Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic Logic. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Johanna Sepúlveda |
Gossip NoC - Avoiding Timing Side-Channel Attacks through Traffic Management. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiajun Shi, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Csaba Andras Moritz |
On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Umar Albalawi, Saraju P. Mohanty, Elias Kougianos |
Energy-Efficient Design of the Secure Better Portable Graphics Compression Architecture for Trusted Image Communication in the IoT. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Tahghighi, Wei Zhang 0012, Sharad Sinha |
Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Chinmay Deshpande, Bilgiday Yuce, Nahid Farhady Ghalaty, Dinesh Ganta, Patrick Schaumont, Leyla Nazhandali |
A Configurable and Lightweight Timing Monitor for Fault Attack Detection. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Kumar Jaiswal, Hayden Kwok-Hay So |
Taylor Series Based Architecture for Quadruple Precision Floating Point Division. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Oana Boncalo, Ioana Mot |
Multi Clock Flooded LDPC Decoding Architecture with Reduced Memory and Interconnect. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Rafael Fao de Moura, Jeckson Dellagostin Souza, Luigi Carro, Antonio Carlos Schneider Beck, Mateus Beck Rutzig |
The Impact of Heterogeneity on a Reconfigurable Multicore System. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hengyang Zhao, Sheldon X.-D. Tan, Hai Wang 0002, Hai-Bao Chen |
Online Unusual Behavior Detection for Temperature Sensor Networks. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Junghoon Oh, Mineo Kaneko |
Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan Sebastian Piedrahita Giraldo, Luigi Carro, Stephan Wong, Antonio C. S. Beck |
Leveraging Compiler Support on VLIW Processors for Efficient Power Gating. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Marek Parfieniuk, Sang Yoon Park |
On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Avik Bose, Prasun Ghosal, Saraju P. Mohanty |
STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kibum Lee, S. Simon Wong |
Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Tan Nguyen, Yao Chen 0008, Kyle Rupnow, Swathi T. Gurumani, Deming Chen |
SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjay Singh Rajput, Ashish Singh, Ashwani Kumar Chandel, Rajeevan Chandel |
Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen |
Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahesh S. Murty, Rahul Shrestha |
VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasanna Kansakar, Arslan Munir |
A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishnu Unnikrishnan, Mark Vesterbacka |
Mixed-Signal Design Using Digital CAD. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kelvin Ly, Yier Jin |
Security Challenges in CPS and IoT: From End-Node to the System. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruizhe Cai, Ao Ren, Yanzhi Wang, Bo Yuan 0001 |
Memristor-Based Discrete Fourier Transform for Improving Performance and Energy Efficiency. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Tu, Visar Berisha, Yu Cao 0001, Jae-sun Seo |
Reducing the Model Order of Deep Neural Networks Using Information Theory. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ningxi Liu, Benton H. Calhoun |
Design Optimization of Register File Throughput and Energy Using a Virtual Prototyping (ViPro) Tool. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Papa-Sidi Ba, Sophie Dupuis, Palanichamy Manikandan, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre |
Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Cédric Marchand 0002, Lilian Bossuet, Abdelkarim Cherkaoui |
Design and Characterization of the TERO-PUF on SRAM FPGAs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanchang Chen, Xinghua Yang, Fei Qiao, Jie Han 0001, Qi Wei 0001, Huazhong Yang |
A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumitha George, Ahmedullah Aziz, Xueqing Li, Moon Seok Kim, Suman Datta, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan |
Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria Malik, Farnoud Farahmand, Paul Otto, Nima Akhlaghi, Tinoosh Mohsenin, Siddhartha Sikdar, Houman Homayoun |
Architecture Exploration for Energy-Efficient Embedded Vision Applications: From General Purpose Processor to Domain Specific Accelerator. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajshekar Kalayappan, Smruti R. Sarangi |
SecCheck: A Trustworthy System with Untrusted Components. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | B. Naresh Kumar Reddy, M. H. Vasantha, Kumar Y. B. Nithin |
A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sohail Ahasan, Saurav Maji, Kaushik Roy 0001, Mrigank Sharad |
Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaya Dofe, Yuejun Zhang, Qiaoyan Yu |
DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kelson Gent, Michael S. Hsiao |
Fast Multi-level Test Generation at the RTL. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Garrett S. Rose, Mesbah Uddin, Md. Badruddoja Majumder |
A Designer's Rationale for Nanoelectronic Hardware Security Primitives. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Maher Abdelrasoul, Mohammed Sharaf Sayed, Victor Goulart |
Scalable Integer DCT Architecture for HEVC Encoder. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Anjana Balachandran, Nandeesha Veeranna, Benjamin Carrión Schäfer |
On Time Redundancy of Fault Tolerant C-Based MPSoCs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Yaohua Wang, Xiaowen Chen, Dong Wang, Sheng Liu 0001 |
Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Gayathri Ananthanarayanan, Smruti R. Sarangi, M. Balakrishnan |
Leakage Power Aware Task Assignment Algorithms for Multicore Platforms. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Davit Mirzoyan, Ararat Khachatryan |
A New Process Variation Monitoring Circuit. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Monther Abusultan, Sunil P. Khatri |
A Ternary-Valued, Floating Gate Transistor-Based Circuit Design Approach. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Raghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, Yiorgos Tsiatouhas |
Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mesbah Uddin, Md. Badruddoja Majumder, Garrett S. Rose, Karsten Beckmann, Harika Manem, Zahiruddin Alamgir, Nathaniel C. Cady |
Techniques for Improved Reliability in Memristive Crossbar PUF Circuits. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingyu Li, Jiajun Shi, Mostafizur Rahman, Santosh Khasanvis, Sachin Bhat, Csaba Andras Moritz |
Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kapil Dev, Sherief Reda, Indrani Paul, Wei Huang 0004, Wayne P. Burleson |
Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Satyajit Das, Thomas Peyret, Kevin J. M. Martin, Gwenolé Corre, Mathieu Thevenin, Philippe Coussy |
A Scalable Design Approach to Efficiently Map Applications on CGRAs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ji Li 0006, Jeffrey T. Draper |
Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Anupam Chattopadhyay, Vikramkumar Pudi, Anubhab Baksi, Thambipillai Srikanthan |
FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Cunxi Yu, Maciej J. Ciesielski |
Formal Verification Using Don't-Care and Vanishing Polynomials. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Tiantao Lu, Zhiyuan Yang 0001, Ankur Srivastava 0001 |
Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Yousra Alkabani, Zach Koopmans, Haifeng Xu, Alex K. Jones, Rami G. Melhem |
Write Pulse Scaling for Energy Efficient STT-MRAM. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeongwoo Heo, Taewhan Kim |
Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhou Zhao, Ashok Srivastava, Lu Peng 0001, Saraju P. Mohanty |
A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Anirban Sengupta, Deepak Kachave |
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ioannis S. Stamelakos, Amin Khajeh, Ahmed M. Eltawil, Gianluca Palermo, Cristina Silvano, Fadi J. Kurdahi |
A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Dylan C. Stow, Itir Akgun, Russell Barnes, Peng Gu, Yuan Xie 0001 |
Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Bo Yuan 0001, Yanzhi Wang |
High-Accuracy FIR Filter Design Using Stochastic Computing. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanchan Manna, Chatla Swamy Sagar, Santanu Chattopadhyay, Indranil Sengupta 0001 |
Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Purushothaman |
MINLP Based Power Optimization for Pipelined ADC. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaolin Xu, Wayne P. Burleson, Daniel E. Holcomb |
Using Statistical Models to Improve the Reliability of Delay-Based PUFs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Niels Thole, Görschwin Fey, Alberto García Ortiz |
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark E. Dean, Christopher Daffron |
A VLSI Design for Neuromorphic Computing. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayed El Gendy, Ahmed Shalaby 0001, Mohammed Sharaf Sayed |
Low Cost VLSI Architecture for Sample Adaptive Offset Encoder in HEVC. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Pratima Chatterjee, Mayukh Sarkar, Prasun Ghosal |
Computing in Ribosomes: Performing Boolean Logic Using mRNA-Ribosome System. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Cunxi Yu, Maciej J. Ciesielski |
Analyzing Imprecise Adders Using BDDs - A Case Study. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Tosiron Adegbija, Ann Gordon-Ross |
Phase-Based Dynamic Instruction Window Optimization for Embedded Systems. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahdi Elghazali, Manoj Sachdev, Ajoy Opal |
A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Zheng Wang 0020, Alessandro Littarru, Emmanuel Ikechukwu Ugwu, Shazia Kanwal, Anupam Chattopadhyay |
Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Suman Deb, Anupam Chattopadhyay, Hao Yu 0001 |
Energy Optimization of Racetrack Memory-Based SIMON Block Cipher. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Faris S. Alghareb, Mingjie Lin, Ronald F. DeMara |
Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Heechun Park, Taewhan Kim |
Synthesizing Asynchronous Circuits toward Practical Use. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria I. Mera Collantes, Mohamed El Massad, Siddharth Garg |
Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Ahish, Dheeraj Sharma, M. H. Vasantha, Kumar Y. B. Nithin |
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Po-Tsang Chen, Ching-Yuan Yang |
A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless Communication Systems. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | F. Lalchhandama, Brojo Gopal Sapui, Kamalika Datta |
An Improved Approach for the Synthesis of Boolean Functions Using Memristor Based IMPLY and INVERSE-IMPLY Gates. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Divya Duvvuri, Vijaya Sankara Rao Pasupureddi |
An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell |
Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ensar Vahapoglu, Mustafa Altun |
Accurate Synthesis of Arithmetic Operations with Stochastic Logic. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Chenchen Liu, Qing Yang 0011, Bonan Yan, Jianlei Yang 0001, Xiaocong Du, Weijie Zhu, Hao Jiang 0014, Qing Wu 0002, Mark Barnell, Hai Li 0001 |
A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
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