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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 248 occurrences of 144 keywords
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Results
Found 778 publication records. Showing 778 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Chengmo Yang, Alex Orailoglu |
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
synchronization, interprocessor communication |
16 | Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano |
Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs. |
CPAIOR |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Klaus Waldschmidt, Jan Haase 0001, Andreas Hofmann, Markus Damm, Dennis Hauser |
Reliability-Aware Power Management Of Multi-Core Systems (MPSoCs). |
Dynamically Reconfigurable Architectures |
2006 |
DBLP BibTeX RDF |
|
16 | Giacomo Paci, Paul Marchal, Francesco Poletti, Luca Benini |
Exploring "temperature-aware" design in low-power MPSoCs. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Andrea Alimonda, Andrea Acquaviva, Salvatore Carta, Alessandro Pisano |
A control theoretic approach to run-time energy optimization of pipelined processing in MPSoCs. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Simon Schliecker, Matthias Ivers, Rolf Ernst |
Integrated analysis of communicating tasks in MPSoCs. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
multiprocessor performance analysis, real-time, memory accesses |
16 | Suresh Srinivasan, Raghavan Ramadoss, Narayanan Vijaykrishnan |
Process Variation Aware Parallelization Strategies for MPSoCs. |
SoCC |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Martino Ruggiero, Pari Gioia, Guerri Alessio, Luca Benini, Michela Milano, Davide Bertozzi, Alexandru Andrei |
A Cooperative, Accurate Solving Framework for Optimal Allocation, Scheduling and Frequency Selection on Energy-Efficient MPSoCs. |
SoC |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Mahmut T. Kandemir, Guilin Chen |
Locality-Aware Process Scheduling for Embedded MPSoCs. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Mirko Loghi, Massimo Poncino |
Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Guilin Chen, Mahmut T. Kandemir |
Code restructuring for improving cache performance of MPSoCs. |
ICCAD |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Cristiano C. de Araújo, Edna Barros, Rodolfo Azevedo, Guido Araujo |
Processor Centric Specification and Modelling of MPSoCs. |
FDL |
2005 |
DBLP BibTeX RDF |
|
16 | Sri Hari Krishna Narayanan, Özcan Özturk 0001, Mahmut T. Kandemir, Mustafa Karaköy |
Workload Clustering for Increasing Energy Savings on Embedded MPSoCs. |
SoCC |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano |
Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation. |
CP |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Martti Forsell |
ParLe - A Parallel Computing Learning Set for MPSOCs/NOCs. |
SoC |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano |
Allocation and Scheduling for MPSoCs via decomposition and no-good generation. |
IJCAI |
2005 |
DBLP BibTeX RDF |
|
16 | Taeweon Suh, Daehyun Kim 0001, Hsien-Hsin S. Lee |
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
heterogeneous, cache coherence, MPSoC, real-time and embedded systems, inter-processor communication |
14 | Yiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy de Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor |
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
embedded systems, MPSoC, memory optimization |
14 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli |
Abstraction of RTL IPs into embedded software. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
RTL IP reuse, embedded software generation |
14 | Jer-Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang |
New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
architecture model/template, model-driven design flow, multi-facet arbiter, granularity, design space, design model |
14 | Antonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto |
HW/SW methodologies for synchronization in FPGA multiprocessors. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fpga, synchronization, multiprocessors |
14 | Hao Shen, Frédéric Pétrot |
Novel task migration framework on configurable heterogeneous MPSoC platforms. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Luciano Ost, Guilherme Montez Guindani, Leandro Soares Indrusiak, Cezar Reinbrecht, Thiago Raupp da Rosa, Fernando Moraes 0001 |
A high abstraction, high accuracy power estimation model for networks-on-chip. |
SBCCI |
2009 |
DBLP DOI BibTeX RDF |
high abstraction modeling, networks-on-chip, power modeling |
14 | Leonel Tedesco, Fabien Clermidy, Fernando Moraes 0001 |
A path-load based adaptive routing algorithm for networks-on-chip. |
SBCCI |
2009 |
DBLP DOI BibTeX RDF |
quality of service, networks on chip, dynamic routing, traffic monitoring |
14 | Leonel Tedesco, Fabien Clermidy, Fernando Moraes 0001 |
A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
QoS, networks on chip, dynamic routing, traffic monitoring |
14 | Siddharth Garg, Diana Marculescu, Radu Marculescu, Ümit Y. Ogras |
Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
Networks-on-Chip, power management, performance bounds |
14 | Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Toshio Isomura, Kazuo Satou |
Trace-driven workload simulation method for Multiprocessor System-On-Chips. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
MPSoC architecture exploration, simulation, performance estimation, workload model |
14 | Xiang Xiao, Jaehwan John Lee |
A Novel O(1) Deadlock Detection Methodology for Multiunit Resource Systems and Its Hardware Implementation for System-on-Chip. |
IEEE Trans. Parallel Distributed Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt |
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Min Bao, Alexandru Andrei, Petru Eles, Zebo Peng |
Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Fabrizio Mulas, Michele Pittau, Marco Buttu, Salvatore Carta, Andrea Acquaviva, Luca Benini, David Atienza, Giovanni De Micheli |
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Philip K. F. Hölzenspies, Johann L. Hurink, Jan Kuper, Gerard J. M. Smit |
Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC). |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Eduardo Wenzel Brião, Daniel Barcelos, Flávio Rech Wagner |
Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Sudeep Pasricha, Nikil D. Dutt |
ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith Whisnant, Kenny C. Gross |
Temperature-aware MPSoC scheduling for reducing hot spots and gradients. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert |
Bio-inspiration helps computers: A new machine. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Diana Göhringer, Michael Hübner 0001, Volker Schatz, Jürgen Becker 0001 |
Runtime adaptive multi-processor system-on-chip: RAMPSoC. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Giovanni Beltrame, Luca Fossati, Donatella Sciuto |
Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
ReSP, Operating System, Emulation, OpenMP, MPSoC, codesign |
14 | Leandro Fiorin, Gianluca Palermo, Cristina Silvano |
A security monitoring service for NoCs. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
MultiProcessor System-on-Chip (MP-SoC), security, embedded systems, Network-on-Chip (NoC) |
14 | Joachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya |
A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications. |
EMSOFT |
2008 |
DBLP DOI BibTeX RDF |
actor-oriented design, mpsoc scheduling, software synthesis |
14 | Mingsong Lv, Ying Guo, Nan Guan, Qingxu Deng |
RTNoC: A Simulation Tool for Real-Time Communication Scheduling on Networks-on-Chips. |
CSSE (4) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Ümit Y. Ogras, Radu Marculescu, Diana Marculescu |
Variation-adaptive feedback control for networks-on-chip with multiple clock domains. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
dynamic voltage-frequency scaling, voltage-frequency island, networks-on-chip, MPSoC, feedback control, parameter variation |
14 | Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda |
MAPS: an integrated framework for MPSoC application parallelization. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
MPSoC programming, parallelization, software, embedded |
14 | Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li 0018, Li-Shiuan Peh |
Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Srinivasan Murali, Luca Benini, Giovanni De Micheli |
An Application-Specific Design Methodology for On-Chip Crossbar Generation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Mirko Loghi, Luca Benini, Massimo Poncino |
Power macromodeling of MPSoC message passing primitives. |
ACM Trans. Embed. Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
multiprocessor, system-on-chip, macromodeling, Communication primitives |
14 | Ines Viskic, Samar Abdi, Daniel D. Gajski |
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. |
LCTES |
2007 |
DBLP DOI BibTeX RDF |
custom communication SW, pin/cycle accurate models, MPSoC, system level design, transaction level models, platform based design, automatic synthesis, on-chip communication |
14 | Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto |
Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Matthieu Briere, Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, Fabien Mieyeville, Frédéric Gaffiot, Ian O'Connor |
System level assessment of an optical NoC in an MPSoC platform. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Ahmed Amine Jerraya |
HW/SW implementation from abstract architecture models. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Jan Willem van den Brand, Marco Bekooij |
Streaming consistency: a model for efficient MPSoC design. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis 0001, Soo-Ik Chae, Ahmed Amine Jerraya |
Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. |
SCOPES |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere |
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Chengmo Yang, Alex Orailoglu |
Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules. |
CODES+ISSS |
2007 |
DBLP DOI BibTeX RDF |
multiprocessor task schedulihng, reconfiguration, adaptive execution |
14 | Junqing Sun, Gregory D. Peterson, Olaf O. Storaasli |
Sparse Matrix-Vector Multiplication Design on FPGAs. |
FCCM |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Emiliano Dolif, Michele Lombardi 0001, Martino Ruggiero, Michela Milano, Luca Benini |
Communication-aware stochastic allocation and scheduling framework for conditional task graphs in multi-processor systems-on-chip. |
EMSOFT |
2007 |
DBLP DOI BibTeX RDF |
multimedia dataflow streaming, scheduling, allocation |
14 | Alessandro Dalla Torre, Martino Ruggiero, Luca Benini |
MP-Queue: an Efficient Communication Library for Embedded Streaming Multimedia Platforms. |
ESTIMedia |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Michele Pittau, Andrea Alimonda, Salvatore Carta, Andrea Acquaviva |
Impact of Task Migration on Streaming Multimedia for Embedded Multiprocessors: A Quantitative Evaluation. |
ESTIMedia |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Youcef Bouchebaba, Essaid Bensoudane, Bruno Lavigueur, Pierre G. Paulin, Gabriela Nicolescu |
Two-level tiling for MPSoC architecture. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Salvatore Carta, Andrea Acquaviva, Pablo García Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias |
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
thermal studies, FPGA, operating system, emulation, MPSoC |
14 | Pramod Chandraiah, Rainer Dömer |
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa |
Efficient Synchronization for Embedded On-Chip Multiprocessors. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Application-specific heterogeneous multiprocessor synthesis using extensible processors. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Junggyu Park, Hyojung Song, Seungmo Cho, Najeong Han, Kyungjeon Kim, Jinman Park |
A Real-time Media Framework for Asymmetric MPSoC. |
ISORC |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini |
An integrated open framework for heterogeneous MPSoC design space exploration. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Luca Benini |
Application specific NoC design. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
application-specific integrated systems, systems on chip, networks on chip, design methodologies |
14 | Stefano Bertozzi, Andrea Acquaviva, Davide Bertozzi, Antonio Poggiali |
Supporting task migration in multi-processor systems-on-chip: a feasibility study. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
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14 | Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo |
Contrasting a NoC and a traditional interconnect fabric with layout awareness. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
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14 | Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt |
System-level power-performance trade-offs in bus matrix communication architecture synthesis. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs |
14 | Noel Eisley, Vassos Soteriou, Li-Shiuan Peh |
High-level power analysis for multi-core chips. |
CASES |
2006 |
DBLP DOI BibTeX RDF |
simulation, chip multiprocessor (CMP), multi-core, power analysis, system-on-a-chip (SoC) |
14 | Akash Kumar 0001, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha |
Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip. |
ESTIMedia |
2006 |
DBLP DOI BibTeX RDF |
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14 | Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt |
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
customized memory hierarchy, multiprocessor data reuse analysis, scratch pad memory management |
14 | Srinivasan Murali, Giovanni De Micheli |
An Application-Specific Design Methodology for STbus Crossbar Generation. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
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14 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin |
Using data compression in an MPSoC architecture for improving performance. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
compression, MPSoC |
14 | Ali Erdem Özcan, Sébastien Jean, Jean-Bernard Stefani |
Bringing Ease and Adaptability to MPSoC Software Design: A Component-Based Approach. |
CASSIS |
2005 |
DBLP DOI BibTeX RDF |
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14 | Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon |
Analyzing On-Chip Communication in a MPSoC Environment. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
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14 | Mirko Loghi, Massimo Poncino, Luca Benini |
Cycle-accurate power analysis for multiprocessor systems-on-a-chip. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
low power, multiprocessor, system-on-chip |
14 | Kai Richter 0001, Marek Jersak, Rolf Ernst |
A Formal Approach to MpSoC Performance Verification. |
Computer |
2003 |
DBLP DOI BibTeX RDF |
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