Search results for "PI-Bus"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Francesc Moll, Joan Figueras, Antonio Rubio 0001	Data Dependence of Delay Distribution for a Planar Bus.	PATMOS	2008	DBLP DOI BibTeX RDF
20	Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Functional Self-Testing for Bus-Based Symmetric Multiprocessors.	DATE	2008	DBLP DOI BibTeX RDF
20	Hong Hee Lee, Gwan Su Kim, Jung Hoon Lee, Byung Jin Kim	Real-Time Communications on IEC 61850 Process Bus Based Distributed Sampled Measured Values Applications in Merging Unit.	ICIC (1)	2008	DBLP DOI BibTeX RDF	SV, Merging Unit, IRIG-B, Time Synchronization, IEC 61850
20	Youngjin Cho, Younghyun Kim 0001, Sangyoung Park, Naehyuck Chang	System-level power estimation using an on-chip bus performance monitoring unit.	ICCAD	2008	DBLP DOI BibTeX RDF
20	Chenglie Du, Gang Li	A Software Dual-Bus Architecture Suitable for Distributed Real-Time Embedded System.	CSSE (4)	2008	DBLP DOI BibTeX RDF
20	Lin Chen, Wanzhong Sun, Zhixin Wang, Chao Zhou	A SystemC-Based Transaction Level Modeling of On-Chip-Bus.	CSSE (4)	2008	DBLP DOI BibTeX RDF
20	Shimin Li, Ladan Tahvildari	E-BUS: a toolkit for extracting business services from java software systems.	ICSE Companion	2008	DBLP DOI BibTeX RDF	business services
20	Hariharan Sankaran, Srinivas Katkoori	Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis.	DELTA	2008	DBLP DOI BibTeX RDF	Simulated Annealing, HLS, Encoding, Crosstalk, Binding, Reordering
20	Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar	Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	Performance evaluation, VLIW, ASIP, Clustered VLIW processors
20	Dimka Karastoyanova, Branimir Wetzstein, Tammo van Lessen, Daniel Wutke, Jörg Nitzsche, Frank Leymann	Semantic Service Bus: Architecture and Implementation of a Next Generation Middleware.	ICDE Workshops	2007	DBLP DOI BibTeX RDF
20	Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley	Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus.	ASYNC	2007	DBLP DOI BibTeX RDF
20	Mingxian Jin, Johnnie W. Baker	On the Power of the Multiple Associative Computing (MASC) Model Related to That of Reconfigurable Bus-Based Models.	IPDPS	2007	DBLP DOI BibTeX RDF
20	Tyler Pace, Shruti Ramalingam, David Roedl	Celerometer and idling reminder: persuasive technology for school bus eco-driving.	CHI Extended Abstracts	2007	DBLP DOI BibTeX RDF	automobile cockpit design, automobile interfaces, designing for eco-driving, persuasive technology, captology, mission-critical systems
20	Carl Collins, Amy Grude, Matthew Scholl, Robert Thompson 0003	txt bus: wait time information on demand.	CHI Extended Abstracts	2007	DBLP DOI BibTeX RDF	user interface design, motivation, SMS, public transportation
20	Tan Yan, Martin D. F. Wong	Untangling twisted nets for bus routing.	ICCAD	2007	DBLP DOI BibTeX RDF
20	Zonghua Gu 0001, Xiuqiang He 0001, Mingxuan Yuan	Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-Checking.	DAC	2007	DBLP DOI BibTeX RDF
20	Andy Gean Ye, Jonathan Rose	Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
20	Muhammet Mustafa Ozdal, Martin D. F. Wong	Algorithmic study of single-layer bus routing for high-speed boards.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
20	Lijun Gao, Keshab K. Parhi	Models for Architectural Power and Power Grid Noise Analysis on Data Bus.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	augmented DBT model, SCTA model, STCTA model, power consumption, switching activity, power spectrum, transition probability, power grid noise, transition activity
20	Gunar Schirner, Rainer Dömer	Quantitative analysis of transaction level models for the AMBA bus.	DATE	2006	DBLP DOI BibTeX RDF
20	Feng Wang 0004, Yuan Xie 0001, Narayanan Vijaykrishnan, Mary Jane Irwin	On-chip bus thermal analysis and optimization.	DATE	2006	DBLP DOI BibTeX RDF
20	Rikard Thid, Ingo Sander, Axel Jantsch	Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads.	DSD	2006	DBLP DOI BibTeX RDF
20	Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi	Leveraging Optical Technology in Future Bus-based Chip Multiprocessors.	MICRO	2006	DBLP DOI BibTeX RDF
20	Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou	A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication.	ASP-DAC	2006	DBLP DOI BibTeX RDF
20	Ergün Eraslan, Diyar Akay, Mustafa Kurt	Usability Ranking of Intercity Bus Passenger Seats Using Fuzzy Axiomatic Design Theory.	CDVE	2006	DBLP DOI BibTeX RDF	Fuzzy Axiomatic Design, Usability, Conformance Testing, Cooperative Engineering
20	Ken Ueno, Michiaki Tatsubori	Early Capacity Testing of an Enterprise Service Bus.	ICWS	2006	DBLP DOI BibTeX RDF
20	Abdul Samad Shibghatullah, Tillal Eldabi, Jasna Kuljis	A proposed multiagent model for bus crew scheduling.	WSC	2006	DBLP DOI BibTeX RDF
20	Bernhard Fechner	A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments.	PARELEC	2006	DBLP DOI BibTeX RDF
20	Donghai Li, Guang-Sheng Ma, Gang Feng	Optimized Design of Interconnected Bus on Chip for Low Power.	International Conference on Computational Science (4)	2006	DBLP DOI BibTeX RDF
20	Hsun-Chieh Yu, Rung-Bin Lin	Is more redundancy better for on-chip bus encoding.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Hadi Parandeh-Afshar, Ali Afzali-Kusha, Ali Khaki-Firooz	A very high performance address BUS encoder.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Min Chen 0024, Yu Cao 0001	Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design.	ISQED	2006	DBLP DOI BibTeX RDF
20	Ahmed Elkammar, Norman Scheinberg, Srinivasa Vemuru	Bus Encoding Scheme To Eliminate Unwanted Signal Transitions.	DELTA	2006	DBLP DOI BibTeX RDF
20	Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao	Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion.	APCCAS	2006	DBLP DOI BibTeX RDF
20	Pervez Khaled, Masud H. Chowdhury	Prospects and Challenges of Handling Power Bus Modeling and Supply Noise in Package-Chip C0-design Approach.	APCCAS	2006	DBLP DOI BibTeX RDF
20	N. Venkateswaran 0002, S. Balaji, V. Sridhar	Fault tolerant bus architecture for deep submicron based processors.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF	deep submicron technology, fault tolerance, interconnect, electromigration
20	Andy Gean Ye, Jonathan Rose	Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits.	FPGA	2005	DBLP DOI BibTeX RDF	datapath regularity, reconfigurable fabric, FPGA architecture, routing architecture, area efficiency
20	Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud	Hardware Engines for Bus Encryption: A Survey of Existing Techniques.	DATE	2005	DBLP DOI BibTeX RDF
20	Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo	Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture.	DATE	2005	DBLP DOI BibTeX RDF
20	Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng	Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip.	DSD	2005	DBLP DOI BibTeX RDF
20	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Automated throughput-driven synthesis of bus-based communication architectures.	ASP-DAC	2005	DBLP DOI BibTeX RDF
20	Sujan Pandey, Manfred Glesner, Max Mühlhäuser	Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture.	SBCCI	2005	DBLP DOI BibTeX RDF	on-chip communication architecture synthesis, optimization, algorithms
20	Ivan Petkov, Paul Amblard, Marin Hristov	Systematic Design Flow for Fast Hardware/Software Prototype Generation from Bus Functional Model for MPSoC.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
20	Srinivasa R. Sridhara, Naresh R. Shanbhag	A low-power bus design using joint repeater insertion and coding.	ISLPED	2005	DBLP DOI BibTeX RDF	low-power, coding, crosstalk, repeaters
20	Shiqiong Tong, Michael Kleinberg, Karen Nan Miu	A distributed slack bus model and its impact on distribution system application techniques.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
20	Paul C. F. Tong, Ping-Ping Xu, Wensong Chen, John Hui, Patty Z. Q. Liu	A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pump.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
20	Yan Zhang 0028, Travis N. Blalock, Mircea R. Stan	A three-level toggle-avoid bus signaling scheme.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
20	Sudeep Pasricha, Mohamed Ben-Romdhane	Using TLM for Exploring Bus-based SoC Communication Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
20	Srinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan	Joint Equalization and Coding for On-Chip Bus Communication.	ISQED	2005	DBLP DOI BibTeX RDF
20	Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan	A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems.	VLSI Design	2005	DBLP DOI BibTeX RDF
20	Tina Lindkvist	Additional Knowledge of Bus Invert Coding Schemes.	IWSOC	2005	DBLP DOI BibTeX RDF
20	Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti 0001	The BUSpec platform for automated generation of verification aids for standard bus protocols.	MEMOCODE	2004	DBLP DOI BibTeX RDF
20	Emilia Farcas, Wolfgang Pree, Josef Templ	Bus Scheduling for TDL Components.	Architecting Systems with Trustworthy Components	2004	DBLP DOI BibTeX RDF
20	Markus Tahedl, Hans-Jörg Pfleiderer	Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures.	PATMOS	2004	DBLP DOI BibTeX RDF
20	Tiberiu Seceleanu, Tomi Westerlund	Aspects of Formal and Graphical Design of a Bus System.	DATE	2004	DBLP DOI BibTeX RDF
20	Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou	On compliance test of on-chip bus for SOC.	ASP-DAC	2004	DBLP DOI BibTeX RDF
20	Changfan Zhang, Jing He 0003, Xiaoqing Zhu	Research of intelligent humidity control system based on field-bus.	ICARCV	2004	DBLP DOI BibTeX RDF
20	Ming Zhu, Harsha Narravula, Constantine Katsinis, Diana Hecht	A Channel Caching Scheme on an Optical Bus-Based Distributed Architecture.	IPDPS	2004	DBLP DOI BibTeX RDF
20	Rainer Finocchiaro, Stefan Lankes, Andreas Jabs	Design of a Real-Time CORBA Event Service Customised for the CAN Bus.	IPDPS	2004	DBLP DOI BibTeX RDF	distributed real-time embedded (DRE) applications, Controller Area Network (CAN), Event Service, Real-Time CORBA
20	Sungchan Kim, Chaeseok Im, Soonhoi Ha	Efficient exploration of on-chip bus architectures and memory allocation.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	communication architecture optimization, design space exploration, system-on-a-chip, memory allocation
20	Muhammet Mustafa Ozdal, Martin D. F. Wong	A provably good algorithm for high performance bus routing.	ICCAD	2004	DBLP DOI BibTeX RDF
20	Sathish Gopalakrishnan, Lui Sha, Marco Caccamo	Hard Real-Time Communication in Bus-Based Networks.	RTSS	2004	DBLP DOI BibTeX RDF
20	Armin Fügenschuh, Alexander Martin 0001, Peter Stöveken	Integrated Optimization of School Starting Times and Public Bus Services.	OR	2004	DBLP DOI BibTeX RDF
20	Suvodeep Gupta, Srinivas Katkoori	Intra-Bus Crosstalk Estimation Using Word-Level Statistics.	VLSI Design	2004	DBLP DOI BibTeX RDF
20	Zhiqiang Liu, Cheng Zhu, Huanye Sheng, Peng Ding	A Q-Based Framework for Demand Bus Simulation.	CIS	2004	DBLP DOI BibTeX RDF
20	Astrit Ademaj, Håkan Sivencrona, Günther Bauer 0001, Jan Torin	Evaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology.	DSN	2003	DBLP DOI BibTeX RDF
20	Li-Da Huang, Hung-Ming Chen, D. F. Wong 0001	Global Wire Bus Configuration with Minimum Delay Uncertainty.	DATE	2003	DBLP DOI BibTeX RDF
20	Sebastian Schönberg	Impact of PCI-Bus Load on Applications in a PC Architecture.	RTSS	2003	DBLP DOI BibTeX RDF
20	Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu	On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
20	MinYong Jeon, Hyunil Byun, JooHo Ha, KiTaek Lee, JooHyoung Kim, JiYoung Seo, KyungWoo Lee, SeungHo Lee	A system-on-chip featuring variable bus architecture and enhanced video coprocessors for MPEG-4 multimedia applications.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
20	Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen	Comparison of synthesized bus and crossbar interconnection architectures.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
20	Eun-Gu Jung, Byung-Soo Choi, Dong-Ik Lee	High performance asynchronous bus for SoC.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
20	Stephan Eberle, Peter Göhner	Adaptive Information Exchange with Field Bus Systems.	ICCSA (1)	2003	DBLP DOI BibTeX RDF
20	Clayton Gibbs	Backplane Test Bus Applications For IEEE STD 1149.1.	ITC	2003	DBLP DOI BibTeX RDF
20	Stephen K. Sunter	Testing High Frequency ADCs and DACs with a Low Frequency Analog Bus.	ITC	2003	DBLP DOI BibTeX RDF
20	Kousuke Shinoda, Itsuki Noda, Masayuki Ohta, Yoichiro Kumada, Hideyuki Nakashima	Is Dial-a-Ride Bus Reasonable in Large Scale Towns? Evaluation of Usability of Dial-a-Ride Systems by Simulation.	MAMUS	2003	DBLP DOI BibTeX RDF
20	Wei-Chung Cheng, Massoud Pedram	Power-optimal encoding for a DRAM address bus.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
20	Unni Narayanan, Ki-Seok Chung, Taewhan Kim	Enhanced bus invert encodings for low-power.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
20	Jürgen Zimmer, Louise A. Dennis	Inductive Theorem Proving and Computer Algebra in the MathWeb Software Bus.	AISC	2002	DBLP DOI BibTeX RDF
20	Joep L. W. Kessels, Ad M. G. Peeters, Torsten Kramer, Markus Feuser, Klaus Ully	Designing an Asynchronous Bus Interface.	ASYNC	2001	DBLP DOI BibTeX RDF
20	Michele Favalli, Cecilia Metra	Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures.	IOLTW	2001	DBLP DOI BibTeX RDF
20	Yewen Li, Luoming Meng	High Availability Connection Management via Software Bus and Mobile Agent in Network Management Environment.	MATA	2001	DBLP DOI BibTeX RDF
20	Claudia Kretzschmar, Robert Siegmund, Dietmar Müller 0001	Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses.	PATMOS	2000	DBLP DOI BibTeX RDF
20	Alexandre David, Wang Yi 0001	Modelling and analysis of a commercial field bus protocol.	ECRTS	2000	DBLP DOI BibTeX RDF
20	Paul Pop, Petru Eles, Zebo Peng	Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis.	DATE	2000	DBLP DOI BibTeX RDF
20	Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki	CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip.	DATE	2000	DBLP DOI BibTeX RDF
20	Yi Pan 0001, Yamin Li, Jie Li 0002, Keqin Li 0001, Si-Qing Zheng	Computing Distance Maps Efficiently Using an Optical Bus.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
20	Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi	Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models.	MTDT	2000	DBLP DOI BibTeX RDF
20	Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj	Power Bus Maximum Voltage Drop in Digital VLSI Circuits.	ISQED	2000	DBLP DOI BibTeX RDF
20	Naehyuck Chang, Kwanho Kim, Jinsung Cho	Bus encoding for low-power high-performance memory systems.	DAC	2000	DBLP DOI BibTeX RDF
20	J. Bruce Millar, Peter Gillingham	Two High-Bandwidth Memory Bus Structures.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF	SLDRAM, Direct Rambus, DRAM, memory design
20	Ahmed E. Kamal 0001, Hossam S. Hassanein	Throughput analysis of WDM-based dual-bus local area networks.	IPCCC	1999	DBLP DOI BibTeX RDF
20	Hettihe P. Dharmasena, Ramachandran Vaidyanathan	Lower Bounds on the Loading of Degree-2 Multiple Bus Networks for Binary-Tree Algorithms.	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
20	Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi	Interconnect Diagnosis of Bus-Connected Multi-RAM Systems.	MTDT	1999	DBLP DOI BibTeX RDF
20	Raffaele Boi, Simona Brigati, Fabrizio Francesconi, Carla Ghidini, Piero Malcovati, Franco Maloberti, Matteo Poletti	Switched-capacitor Litton-code matched filter for satellite ODBH bus.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
20	Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada	Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
20	Daniela Ferrero	A Technique for the (d, s, N)-Bus Network Problem.	SCCC	1999	DBLP DOI BibTeX RDF
20	Sudhakar Bobba, Ibrahim N. Hajj	Estimation of maximum current envelope for power bus analysis and design.	ISPD	1998	DBLP DOI BibTeX RDF
20	Kimmo Kaario, Pertti Raatikainen	Dimensioning of a Multimedia Switching Bus.	EUROMICRO	1998	DBLP DOI BibTeX RDF
20	Manfred Kunde, Kay Guertzig	Efficient Sorting and Routing on Reconfigurable Meshes Using Restricted Bus Length.	IPPS	1997	DBLP DOI BibTeX RDF