Search results for "PLL"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Zhao Zhang 0004, Jincheng Yang, Liyuan Liu, Peng Feng 0001, Jian Liu 0021, Nanjian Wu	A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
13	Youngwoo Jo, Hyojun Kim, SeongHwan Cho	A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
13	Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada	Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting.	IEICE Trans. Electron.	2018	DBLP DOI BibTeX RDF
13	Chua-Chin Wang, Zong-You Hou, Chih-Lin Chen, Doron Shmilovitz	A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits.	Circuits Syst. Signal Process.	2018	DBLP DOI BibTeX RDF
13	Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath	PLL architecture with a composite PFD and variable loop filter.	IET Circuits Devices Syst.	2018	DBLP DOI BibTeX RDF
13	Jili Zhang, Yu Li 0004, Shengxi Diao, Xuefei Bai, Fujiang Lin	A 3 mW 1.2-3.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth.	J. Circuits Syst. Comput.	2018	DBLP DOI BibTeX RDF
13	Aravinda Koithyar, T. K. Ramesh 0001	A faster phase frequency detector using transmission gate-based latch for the reduced response time of the PLL.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
13	Heng Wu, Xiongfei Wang	Instability Effect of PLL on Voltage-Source Converters during Grid Faults: Large-Signal Modeling and Design-Oriented Analysis.	CoRR	2018	DBLP BibTeX RDF
13	Dmytro Cherniak, Carlo Samori, Roberto Nonis, Salvatore Levantino	PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
13	Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Mark Neidengard, Nasser A. Kurd, Amr Elshazly	A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
13	Zhiqiang Huang, Bingwei Jiang, Howard C. Luong	A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
13	Majid Jalalifar, Gyung-Su Byun	A Wide-Range Low-Power PLL-Based PI Multiphase Generator Using an Adaptive Frequency Tracking Technique.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
13	Won Namgoong	A Modified Proportional-Integral Loop Filter to Suppress DCO Noise in Digital PLL.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
13	Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong	A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
13	Eugene Koskin, Dimitri Galayko, Orla Feely, Elena Blokhina	Generation of a Clocking Signal in Synchronized All-Digital PLL Networks.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
13	Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen 0001, Robert Bogdan Staszewski	An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
13	SeongJin Oh, Sung-Jin Kim, Imran Ali, Thi Kim Nga Truong, Dong-Soo Lee, YoungGun Pu, Sang-Sun Yoo, Minjae Lee, Keum-Cheol Hwang, Youngoo Yang, Kang-Yoon Lee	A 3.9 mW Bluetooth Low-Energy Transmitter Using All-Digital PLL-Based Direct FSK Modulation in 55 nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
13	Marco Crepaldi, Gian Nicola Angotzi, Antonio Maviglia, Francesco Diotalevi, Luca Berdondini	A 5 pJ/pulse at 1-Gpps Pulsed Transmitter Based on Asynchronous Logic Master-Slave PLL Synthesis.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
13	Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong	An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
13	Fanyang Li, Tao Kou, Shuying Cheng	An accuracy improved hearing aid readout circuit using a gain-enhanced and OTA-free pseudo-PLL feedback technique.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
13	Lanhua Xia, Jianhui Wu, Zhikuang Cai	A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
13	Sanjeev Tannirkulam Chandrasekaran, Arindam Sanyal	A Digital PLL Based 2nd-Order Δ∑ Bandpass Time-Interleaved ADC.	MWSCAS	2018	DBLP DOI BibTeX RDF
13	Priya Pallavi, Ch. V. Rama Rao	Phase-locked Loop (PLL) Based Phase Estimation in Single Channel Speech Enhancement.	INTERSPEECH	2018	DBLP DOI BibTeX RDF
13	Sehmi Saad, Mongia Mhiri, Aymen Ben Hammadi, Kamel Besbes	A 0.14-3.5 GHz All Digital PLL with improved fast frequency-lock and a novel TDC-based self-calibration capability.	ICM	2018	DBLP DOI BibTeX RDF
13	Prasanna Ravi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay	PPAP and iPPAP: PLL-Based Protection Against Physical Attacks.	ISVLSI	2018	DBLP DOI BibTeX RDF
13	Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov	Development of Time-Varying PLL Macromodel for Jitter Evaluation.	EWDTS	2018	DBLP DOI BibTeX RDF
13	Gyusung Park, Minsu Kim, Chris H. Kim, Bongjin Kim, Vijay Reddy	All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits.	IRPS	2018	DBLP DOI BibTeX RDF
13	Olev Märtens, Mart Min, Paul Annus, Raul Land, Andrei Krivoshei, Margus Metshein	PLL-based extraction of the cardiac component from the bio-impedance signal.	I2MTC	2018	DBLP DOI BibTeX RDF
13	Dongin Kim, SeongHwan Cho	A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop.	ASP-DAC	2018	DBLP DOI BibTeX RDF
13	Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi	A switched-loop-filter PLL with fast phase-error correction technique.	ASP-DAC	2018	DBLP DOI BibTeX RDF
13	Konstantinos F. Krommydas, Antonio T. Alexandridis	Dynamic Analysis of PLL-Synchronized Power Inverter Interface for Grid-Connected PV Systems.	ACC	2018	DBLP DOI BibTeX RDF
13	Arjun Ramaswami Palaniappan, Liter Siek	A 0.0186 mm2, 0.65 V Supply, 9.53 ps RMS Jitter All-Digital PLL for Medical Implants.	NORCAS	2018	DBLP DOI BibTeX RDF
13	Lorenzo Bartolomei, Alessandro Mingotti, Lorenzo Peretto, Roberto Tinarelli, Paola Rinaldi	Accuracy Verification of PLL-Based Acquisition System for Low-Cost Applications.	AMPS	2018	DBLP DOI BibTeX RDF
13	Simon Buhr, Martin Kreißig, Frank Ellinger	Low Power 16 Phase Ring Oscillator and PLL for Use in sub-ns Time Synchronization over Ethernet.	ICECS	2018	DBLP DOI BibTeX RDF
13	Carsten Andrich, Julia Bauer, Peter Große, Alexander Ihlow, Giovanni Del Galdo	A Fast and Stable Time Locked Loop for Network Time Synchronization with Parallel FLL and PLL.	ISPCS	2018	DBLP DOI BibTeX RDF
13	Zakaria Chedjara, Ahmed Massoum, Sarra Massoum, Patrice Wira, Ahmed Safa, Abdelmadjid Gouichiche	A novel robust PLL algorithm applied to the control of a shunt active power filter using a self tuning filter concept.	ICIT	2018	DBLP DOI BibTeX RDF
13	Ksh Milan Singh, Sanjoy Debbarma, Piyush Pratap Singh	Doppler velocity measurement using closed-loop Goertzel algorithm in PLL technique.	ICIT	2018	DBLP DOI BibTeX RDF
13	Shravan S. Nagam, Peter R. Kinget	A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation.	CICC	2018	DBLP DOI BibTeX RDF
13	Daniel Friedman	Hybrid PLL architectures and implementations.	CICC	2018	DBLP DOI BibTeX RDF
13	Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng 0001, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang 0002, Hanli Liu, Kenichi Okada, Akira Matsuzawa	A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.	CICC	2018	DBLP DOI BibTeX RDF
13	Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Robert Bogdan Staszewski	A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi	A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Didem Turker, Ade Bekele, Parag Upadhyaya, Bob Verbruggen, Ying Cao 0010, Shaojun Ma, Christophe Erdmann, Brendan Farley, Yohan Frans, Ken Chang	A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Behrooz Abiri, Ali Hajimiri	A 69-to-79GHz CMOS multiport PA/radiator with +35.7dBm CW EIRP and integrated PLL.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Luca Bertulessi, Luigi Grimaldi, Dmytro Cherniak, Carlo Samori, Salvatore Levantino	A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Cheng-Ru Ho, Mike Shuo-Wei Chen	A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Young-Ju Kim 0001, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom, Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee 0002, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Min-Woo Won, Gun-hee Cho, Hyun-Soo Park, Hyung-Kyu Kim, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Jae-Koo Park, Yong Jae Lee, Yong-Jun Kim, Young-Hun Seo, Beob-Rae Cho, Chang-Ho Shin, ChanYong Lee, YoungSeok Lee, Yoon-Gue Song, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byeong-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang	A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Daniel Weyer, Mehmet Batuhan Dayanik, Sunmin Jang, Michael P. Flynn	A 36.3-to-38.2GHz -216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Jahnavi Sharma, Harish Krishnaswamy	A dividerless reference-sampling RF PLL with -253.5dB jitter FOM and <-67dBc Reference Spurs.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula 0001, Xi Li, Naveen John, Visvesh S. Sathe 0001	A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi, Carlo Samori, Roberto Nonis, Salvatore Levantino	A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation.	ISSCC	2018	DBLP DOI BibTeX RDF
13	Chia-Yu Yao, Wei-Chun Hsia, Chien-Te Yu	Controlling a switched beam array antenna using PLL frequency synthesizers based on the congruence modulo.	ISCAS	2018	DBLP DOI BibTeX RDF
13	Marco Crepaldi, Gian Nicola Angotzi, Alessandro Barcellona, Luca Berdondini	A 1 Gbps UWB OOK Receiver with Double PLL All-Digital CDR and Data Packet Re-Synchronizer.	ISCAS	2018	DBLP DOI BibTeX RDF
13	Arzu Ergintav, Frank Herzel, Dietmar Kissinger, Herman Jalli Ng	An Investigation of Phase Noise of a Fractional-N PLL in the Course of FMCW Chirp Generation.	ISCAS	2018	DBLP DOI BibTeX RDF
13	Dmytro Cherniak, Luigi Grimaldi, Carlo Samori, Salvatore Levantino	Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators.	ISCAS	2018	DBLP DOI BibTeX RDF
13	Debashis Dhar, Paul T. M. van Zeijl, Dusan M. Milosevic, Hao Gao 0001, Peter G. M. Baltus	Analysis of the Effect of PFD Sampling on Charge-Pump PLL Stability.	ISCAS	2018	DBLP DOI BibTeX RDF
13	Razieh Abedi, Rouzbeh Kananizadeh, Amir Esmaili, Omeed Momeni, Payam Heydari	A 53-61GHz Low-Power PLL With Harmonic Positive Feedback VCO in 65nm CMOS.	ISCAS	2018	DBLP DOI BibTeX RDF
13	Andrea Donno, Stefano D'Amico, Roberto Nonis, Peter Thurner	Low noise active loop filter for radar PLL applications.	ICICDT	2018	DBLP DOI BibTeX RDF
13	Zakia Berber, Samir Kameche	Optimal choice for phase margin on mm-Wave PLL frequency synthesizer for 5G wireless communications systems.	SDS	2018	DBLP DOI BibTeX RDF
13	Abhishek Godave, K. Aurobindo, Pranali Choudhari, Anita Jadhav	Design of Multi-PLL Board Using ARM7 Controller.	ICCCNT	2018	DBLP DOI BibTeX RDF
13	Zakia Berber, Samir Kameche	Influence of Loop Bandwidth Parameter on Integer PLL Frequency Synthesizer Performances in 80 GHz mm-Wave 5G Frequency Band.	AICCSA	2018	DBLP DOI BibTeX RDF
13	Jingcheng Tao, Chun-Huat Heng	A 1.6-GHz 3.3-mW 1.5-MHz Wide Bandwidth ΔΣ Fractional-N PLL with a Single Path FIR Phase Noise Filtering.	A-SSCC	2018	DBLP DOI BibTeX RDF
13	Zhao Zhang 0004, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng 0001, Jian Liu 0021, Nanjian Wu	A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range.	A-SSCC	2018	DBLP DOI BibTeX RDF
13	Taikun Ma, Zipeng Chen, Jianxi Wu, Wei Zheng, Shufu Wang, Nan Qi, Baoyong Chi	A CMOS 76-81 GHz 2TX 3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator.	A-SSCC	2018	DBLP DOI BibTeX RDF
13	Faeze Noruzpur, Sina Mahdavi, Maryam Poreh, Shima Tayyeb Ghasemi	A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18μm Technology.	MIXDES	2018	DBLP DOI BibTeX RDF
13	Kazuki Miyao, Tatsuya Okafuji, Takao Kihara, Tsutomu Yoshimura	Study of mutual injection pulling in a 5-GHz, 0.18-μm CMOS cascaded PLL.	APCCAS	2018	DBLP DOI BibTeX RDF
13	Thomas Nikas, Evangelos Pikasis, Adonis Bogris, Dimitris Syvridis	An Optoelectronic PLL Synthesizer with Optical Comb Reference.	ECOC	2018	DBLP DOI BibTeX RDF
13	Michael H. Bierhoff	A General PLL-Type Algorithm for Speed Sensorless Control of Electrical Drives.	IEEE Trans. Ind. Electron.	2017	DBLP DOI BibTeX RDF
13	Hany A. Hamed, Ahmed F. Abdou, Ehab H. E. Bayoumi, E. E. El-Kholy	Frequency Adaptive CDSC-PLL Using Axis Drift Control Under Adverse Grid Condition.	IEEE Trans. Ind. Electron.	2017	DBLP DOI BibTeX RDF
13	Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu	A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
13	Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu	A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
13	Yining Zhang, Ranran Zhou, Woogeun Rhee, Zhihua Wang 0001	A 1.9-mW 750-kb/s 2.4-GHz F-OOK Transmitter With Symmetric FM Template and High-Point Modulation PLL.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
13	Jian Zhao 0004, Xi Wang 0004, Yang Zhao 0007, Guo Ming Xia, An Ping Qiu, Yan Su, Yong Ping Xu	A 0.23-µg Bias Instability and 1-µg/√Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
13	Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho	A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
13	Dongyi Liao, Hechen Wang, Fa Foster Dai, Yang Xu 0017, Roc Berenguer, Sara Munoz Hermoso	An 802.11a/b/g/n Digital Fractional-N PLL With Automatic TDC Linearity Calibration for Spur Cancellation.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
13	Ying Wu 0003, Mina Shahmohammadi, Yue Chen, Ping Lu 0002, Robert Bogdan Staszewski	A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
13	Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu	A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
13	Menxi Xie, Huiqing Wen, Canyan Zhu, Yong Yang	DC Offset Rejection Improvement in Single-Phase SOGI-PLL Algorithms: Methods Review and Experimental Evaluation.	IEEE Access	2017	DBLP DOI BibTeX RDF
13	Zhao Zhang 0004, Liyuan Liu, Peng Feng 0001, Nanjian Wu	A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
13	Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim	A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
13	Toru Nakura, Tetsuya Iizuka, Kunihiro Asada	A PLL Compiler from Specification to GDSII.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
13	Zule Xu, Takayuki Kawahara	A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design.	IEICE Trans. Electron.	2017	DBLP DOI BibTeX RDF
13	Yu-Lung Lo, Wei-Hsiang Ho	A Low-Voltage PLL Design Using a New Calibration Technique for Low-Power Implantable Biomedical Systems.	Circuits Syst. Signal Process.	2017	DBLP DOI BibTeX RDF
13	Xiaosen Liu, Adrian I. Colli-Menchi, Edgar Sánchez-Sinencio	Ultrasonic Electric Scalpels Based on a Sliding-Mode Controller With an Auxiliary PLL Frequency Discriminator.	IEEE Trans. Biomed. Circuits Syst.	2017	DBLP DOI BibTeX RDF
13	Adesh Kumar, Gaurav Verma, Mukul Kumar Gupta	FM Receiver Design Using Programmable PLL.	Wirel. Pers. Commun.	2017	DBLP DOI BibTeX RDF
13	Manas Kumar Hati, Tarun Kanti Bhattacharyya	A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in ΔΣ fractional-N PLL frequency synthesizer.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
13	Qiwei Huang, Chenchang Zhan, Jinwook Burm	A low-complexity locking-accelerated digital PLL with multi-output bang-bang phase detector.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
13	Umakanta Nanda, Debiprasad Priyabrata Acharya	Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
13	Jianfu Lin, Zheng Song 0002, Meng Wei 0001, Baoyong Chi	A 6.6 mW 1.25-2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
13	Diego Paolo Ferruzzo Correa, Átila M. Bueno, José Roberto Castilho Piqueira	Stability of small-amplitude periodic solutions near Hopf bifurcations in time-delayed fully-connected PLL networks.	Commun. Nonlinear Sci. Numer. Simul.	2017	DBLP DOI BibTeX RDF
13	Tianwei Liu, Xiaoran Wang, Rui Wang 0035, Guoying Wu, Tao Zhang 0034, Ping Gui	A Temperature Compensated Triple-Path PLL With KVCO Non-Linearity Desensitization Capable of Operating at 77 K.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
13	Sang-Geun Bae, Gyungmin Kim, Chulwoo Kim	A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
13	Federico Bizzarri, Angelo Brambilla, Sergio Callegari	Efficient and Reliable Small-Signal Estimate of Quantization Noise Contribution to Phase Noise in ΔΣ Fractional-N PLL.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
13	Feiran Lei, Marvin H. White	Reference Injected Phase-Locked Loops (PLL-RIs).	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
13	Zhikuang Cai, Haobo Xu, Shanwen Hu, Jun Yang	Built-in jitter measurement circuit for PLL based on variable vernier delay line.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
13	Xincun Ji, Xiaojuan Xia, Zixuan Wang, Leisheng Jin	A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
13	Tao Yang 0022, Sichen Yu, Huixiang Han, Xiaolu Liu, Dashan Pan, Xi Tan, Na Yan, Fan Ye, Junyu Wang, Hao Min	A 3.2-to-4.6 GHz fast-settling all-digital PLL with feed forward frequency presetting.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
13	Zhao Zhang 0004, Jincheng Yang, Liyuan Liu, Peng Feng 0001, Jian Liu 0021, Nanjian Wu	A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
13	Yajun He, Ziqiang Wang, Han Liu, Fangxu Lv, Shuai Yuan 0005, Chun Zhang, Zhihua Wang 0001, Hanjun Jiang	An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes.	MWSCAS	2017	DBLP DOI BibTeX RDF
13	Feiran Lei, Marvin H. White	A low noise, inductor-less, integer-N RF synthesizer using phase-locked loop with reference injection (PLL-RI).	MWSCAS	2017	DBLP DOI BibTeX RDF