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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 153 occurrences of 86 keywords
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Results
Found 1868 publication records. Showing 1868 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Zhao Zhang 0004, Jincheng Yang, Liyuan Liu, Peng Feng 0001, Jian Liu 0021, Nanjian Wu |
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(5), pp. 933-944, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Youngwoo Jo, Hyojun Kim, SeongHwan Cho |
A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(10), pp. 2170-2174, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada |
Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 101-C(4), pp. 218-223, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Chua-Chin Wang, Zong-You Hou, Chih-Lin Chen, Doron Shmilovitz |
A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 37(4), pp. 1692-1703, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath |
PLL architecture with a composite PFD and variable loop filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 12(3), pp. 256-262, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Jili Zhang, Yu Li 0004, Shengxi Diao, Xuefei Bai, Fujiang Lin |
A 3 mW 1.2-3.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 27(8), pp. 1850117:1-1850117:18, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Aravinda Koithyar, T. K. Ramesh 0001 |
A faster phase frequency detector using transmission gate-based latch for the reduced response time of the PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 46(4), pp. 842-854, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Heng Wu, Xiongfei Wang |
Instability Effect of PLL on Voltage-Source Converters during Grid Faults: Large-Signal Modeling and Design-Oriented Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1811.08926, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
13 | Dmytro Cherniak, Carlo Samori, Roberto Nonis, Salvatore Levantino |
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3), pp. 914-924, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Mark Neidengard, Nasser A. Kurd, Amr Elshazly |
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7), pp. 2109-2117, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Zhiqiang Huang, Bingwei Jiang, Howard C. Luong |
A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7), pp. 2118-2126, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Majid Jalalifar, Gyung-Su Byun |
A Wide-Range Low-Power PLL-Based PI Multiphase Generator Using an Adaptive Frequency Tracking Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(7), pp. 903-907, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Won Namgoong |
A Modified Proportional-Integral Loop Filter to Suppress DCO Noise in Digital PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(8), pp. 974-978, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong |
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9), pp. 2691-2702, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Eugene Koskin, Dimitri Galayko, Orla Feely, Elena Blokhina |
Generation of a Clocking Signal in Synchronized All-Digital PLL Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(6), pp. 809-813, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen 0001, Robert Bogdan Staszewski |
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11), pp. 3756-3768, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | SeongJin Oh, Sung-Jin Kim, Imran Ali, Thi Kim Nga Truong, Dong-Soo Lee, YoungGun Pu, Sang-Sun Yoo, Minjae Lee, Keum-Cheol Hwang, Youngoo Yang, Kang-Yoon Lee |
A 3.9 mW Bluetooth Low-Energy Transmitter Using All-Digital PLL-Based Direct FSK Modulation in 55 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9), pp. 3037-3048, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Marco Crepaldi, Gian Nicola Angotzi, Antonio Maviglia, Francesco Diotalevi, Luca Berdondini |
A 5 pJ/pulse at 1-Gpps Pulsed Transmitter Based on Asynchronous Logic Master-Slave PLL Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3), pp. 1096-1109, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong |
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(12), pp. 1819-1823, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Fanyang Li, Tao Kou, Shuying Cheng |
An accuracy improved hearing aid readout circuit using a gain-enhanced and OTA-free pseudo-PLL feedback technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 15(16), pp. 20180285, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Lanhua Xia, Jianhui Wu, Zhikuang Cai |
A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 15(4), pp. 20171215, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Sanjeev Tannirkulam Chandrasekaran, Arindam Sanyal |
A Digital PLL Based 2nd-Order Δ∑ Bandpass Time-Interleaved ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018, pp. 286-289, 2018, IEEE, 978-1-5386-7392-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Priya Pallavi, Ch. V. Rama Rao |
Phase-locked Loop (PLL) Based Phase Estimation in Single Channel Speech Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INTERSPEECH ![In: Interspeech 2018, 19th Annual Conference of the International Speech Communication Association, Hyderabad, India, 2-6 September 2018., pp. 1161-1164, 2018, ISCA. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Sehmi Saad, Mongia Mhiri, Aymen Ben Hammadi, Kamel Besbes |
A 0.14-3.5 GHz All Digital PLL with improved fast frequency-lock and a novel TDC-based self-calibration capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 30th International Conference on Microelectronics, ICM 2018, Sousse, Tunisia, December 16-19, 2018, pp. 276-279, 2018, IEEE, 978-1-5386-8167-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Prasanna Ravi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay |
PPAP and iPPAP: PLL-Based Protection Against Physical Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 620-625, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov |
Development of Time-Varying PLL Macromodel for Jitter Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2018 IEEE East-West Design & Test Symposium, EWDTS 2018, Kazan, Russia, September 14-17, 2018, pp. 1-7, 2018, IEEE, 978-1-5386-5710-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Gyusung Park, Minsu Kim, Chris H. Kim, Bongjin Kim, Vijay Reddy |
All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 5, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Olev Märtens, Mart Min, Paul Annus, Raul Land, Andrei Krivoshei, Margus Metshein |
PLL-based extraction of the cardiac component from the bio-impedance signal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
I2MTC ![In: IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2018, Houston, TX, USA, May 14-17, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-2222-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Dongin Kim, SeongHwan Cho |
A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018, pp. 283-284, 2018, IEEE, 978-1-5090-0602-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi |
A switched-loop-filter PLL with fast phase-error correction technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018, pp. 307-308, 2018, IEEE, 978-1-5090-0602-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Konstantinos F. Krommydas, Antonio T. Alexandridis |
Dynamic Analysis of PLL-Synchronized Power Inverter Interface for Grid-Connected PV Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACC ![In: 2018 Annual American Control Conference, ACC 2018, Milwaukee, WI, USA, June 27-29, 2018, pp. 2127-2132, 2018, IEEE, 978-1-5386-5428-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Arjun Ramaswami Palaniappan, Liter Siek |
A 0.0186 mm2, 0.65 V Supply, 9.53 ps RMS Jitter All-Digital PLL for Medical Implants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCAS ![In: 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip (SoC), Tallinn, Estonia, October 30-31, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-7656-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Lorenzo Bartolomei, Alessandro Mingotti, Lorenzo Peretto, Roberto Tinarelli, Paola Rinaldi |
Accuracy Verification of PLL-Based Acquisition System for Low-Cost Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AMPS ![In: 9th IEEE International Workshop on Applied Measurements for Power Systems, AMPS 2018, Bologna, Italy, September 26-28, 2018, pp. 1092-1095, 2018, IEEE, 978-1-5386-5375-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Simon Buhr, Martin Kreißig, Frank Ellinger |
Low Power 16 Phase Ring Oscillator and PLL for Use in sub-ns Time Synchronization over Ethernet. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018, pp. 53-56, 2018, IEEE, 978-1-5386-9562-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Carsten Andrich, Julia Bauer, Peter Große, Alexander Ihlow, Giovanni Del Galdo |
A Fast and Stable Time Locked Loop for Network Time Synchronization with Parallel FLL and PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPCS ![In: IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication, ISPCS 2018, Geneva, Switzerland, September 30 - October 5, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-4263-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Zakaria Chedjara, Ahmed Massoum, Sarra Massoum, Patrice Wira, Ahmed Safa, Abdelmadjid Gouichiche |
A novel robust PLL algorithm applied to the control of a shunt active power filter using a self tuning filter concept. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIT ![In: IEEE International Conference on Industrial Technology, ICIT 2018, Lyon, France, February 20-22, 2018, pp. 1124-1131, 2018, IEEE, 978-1-5090-5949-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Ksh Milan Singh, Sanjoy Debbarma, Piyush Pratap Singh |
Doppler velocity measurement using closed-loop Goertzel algorithm in PLL technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIT ![In: IEEE International Conference on Industrial Technology, ICIT 2018, Lyon, France, February 20-22, 2018, pp. 1508-1513, 2018, IEEE, 978-1-5090-5949-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Shravan S. Nagam, Peter R. Kinget |
A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, CA, USA, April 8-11, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-2483-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Daniel Friedman |
Hybrid PLL architectures and implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, CA, USA, April 8-11, 2018, pp. 1-89, 2018, IEEE, 978-1-5386-2483-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng 0001, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang 0002, Hanli Liu, Kenichi Okada, Akira Matsuzawa |
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, CA, USA, April 8-11, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-2483-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Robert Bogdan Staszewski |
A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 448-450, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi |
A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 396-398, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Didem Turker, Ade Bekele, Parag Upadhyaya, Bob Verbruggen, Ying Cao 0010, Shaojun Ma, Christophe Erdmann, Brendan Farley, Yohan Frans, Ken Chang |
A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 378-380, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Behrooz Abiri, Ali Hajimiri |
A 69-to-79GHz CMOS multiport PA/radiator with +35.7dBm CW EIRP and integrated PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 404-406, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Luca Bertulessi, Luigi Grimaldi, Dmytro Cherniak, Carlo Samori, Salvatore Levantino |
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 252-254, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Cheng-Ru Ho, Mike Shuo-Wei Chen |
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 394-396, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Young-Ju Kim 0001, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom, Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee 0002, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Min-Woo Won, Gun-hee Cho, Hyun-Soo Park, Hyung-Kyu Kim, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Jae-Koo Park, Yong Jae Lee, Yong-Jun Kim, Young-Hun Seo, Beob-Rae Cho, Chang-Ho Shin, ChanYong Lee, YoungSeok Lee, Yoon-Gue Song, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byeong-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang |
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 204-206, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Daniel Weyer, Mehmet Batuhan Dayanik, Sunmin Jang, Michael P. Flynn |
A 36.3-to-38.2GHz -216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 250-252, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Jahnavi Sharma, Harish Krishnaswamy |
A dividerless reference-sampling RF PLL with -253.5dB jitter FOM and <-67dBc Reference Spurs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 258-260, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula 0001, Xi Li, Naveen John, Visvesh S. Sathe 0001 |
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 302-304, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi, Carlo Samori, Roberto Nonis, Salvatore Levantino |
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 248-250, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Chia-Yu Yao, Wei-Chun Hsia, Chien-Te Yu |
Controlling a switched beam array antenna using PLL frequency synthesizers based on the congruence modulo. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-4, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Marco Crepaldi, Gian Nicola Angotzi, Alessandro Barcellona, Luca Berdondini |
A 1 Gbps UWB OOK Receiver with Double PLL All-Digital CDR and Data Packet Re-Synchronizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Arzu Ergintav, Frank Herzel, Dietmar Kissinger, Herman Jalli Ng |
An Investigation of Phase Noise of a Fractional-N PLL in the Course of FMCW Chirp Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-4, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Dmytro Cherniak, Luigi Grimaldi, Carlo Samori, Salvatore Levantino |
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Debashis Dhar, Paul T. M. van Zeijl, Dusan M. Milosevic, Hao Gao 0001, Peter G. M. Baltus |
Analysis of the Effect of PFD Sampling on Charge-Pump PLL Stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Razieh Abedi, Rouzbeh Kananizadeh, Amir Esmaili, Omeed Momeni, Payam Heydari |
A 53-61GHz Low-Power PLL With Harmonic Positive Feedback VCO in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Andrea Donno, Stefano D'Amico, Roberto Nonis, Peter Thurner |
Low noise active loop filter for radar PLL applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: 2018 International Conference on IC Design & Technology, ICICDT 2018, Otranto, Italy, June 4-6, 2018, pp. 77-80, 2018, IEEE, 978-1-5386-2550-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Zakia Berber, Samir Kameche |
Optimal choice for phase margin on mm-Wave PLL frequency synthesizer for 5G wireless communications systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SDS ![In: Fifth International Conference on Software Defined Systems, SDS 2018, Barcelona, Spain, April 23-26, 2018, pp. 223-228, 2018, IEEE, 978-1-5386-5900-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Abhishek Godave, K. Aurobindo, Pranali Choudhari, Anita Jadhav |
Design of Multi-PLL Board Using ARM7 Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 9th International Conference on Computing, Communication and Networking Technologies, ICCCNT 2018, Bengaluru, India, July 10-12, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-4430-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Zakia Berber, Samir Kameche |
Influence of Loop Bandwidth Parameter on Integer PLL Frequency Synthesizer Performances in 80 GHz mm-Wave 5G Frequency Band. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: 15th IEEE/ACS International Conference on Computer Systems and Applications, AICCSA 2018, Aqaba, Jordan, October 28 - Nov. 1, 2018, pp. 1-2, 2018, IEEE Computer Society, 978-1-5386-9120-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Jingcheng Tao, Chun-Huat Heng |
A 1.6-GHz 3.3-mW 1.5-MHz Wide Bandwidth ΔΣ Fractional-N PLL with a Single Path FIR Phase Noise Filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018, pp. 215-218, 2018, IEEE, 978-1-5386-6413-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Zhao Zhang 0004, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng 0001, Jian Liu 0021, Nanjian Wu |
A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018, pp. 227-230, 2018, IEEE, 978-1-5386-6413-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Taikun Ma, Zipeng Chen, Jianxi Wu, Wei Zheng, Shufu Wang, Nan Qi, Baoyong Chi |
A CMOS 76-81 GHz 2TX 3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018, pp. 83-86, 2018, IEEE, 978-1-5386-6413-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Faeze Noruzpur, Sina Mahdavi, Maryam Poreh, Shima Tayyeb Ghasemi |
A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18μm Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: 25th International Conference `Mixed Design of Integrated Circuits and System`, MIXDES 2018, Gdynia, Poland, June 21-23, 2018, pp. 109-115, 2018, IEEE, 978-83-63578-14-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Kazuki Miyao, Tatsuya Okafuji, Takao Kihara, Tsutomu Yoshimura |
Study of mutual injection pulling in a 5-GHz, 0.18-μm CMOS cascaded PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018, pp. 175-178, 2018, IEEE, 978-1-5386-8240-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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13 | Thomas Nikas, Evangelos Pikasis, Adonis Bogris, Dimitris Syvridis |
An Optoelectronic PLL Synthesizer with Optical Comb Reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECOC ![In: European Conference on Optical Communication, ECOC 2018, Rome, Italy, September 23-27, 2018, pp. 1-3, 2018, IEEE, 978-1-5386-4862-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
13 | Michael H. Bierhoff |
A General PLL-Type Algorithm for Speed Sensorless Control of Electrical Drives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 64(12), pp. 9253-9260, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Hany A. Hamed, Ahmed F. Abdou, Ehab H. E. Bayoumi, E. E. El-Kholy |
Frequency Adaptive CDSC-PLL Using Axis Drift Control Under Adverse Grid Condition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 64(4), pp. 2671-2682, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu |
A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(1), pp. 8-20, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu |
A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(4), pp. 1123-1133, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Yining Zhang, Ranran Zhou, Woogeun Rhee, Zhihua Wang 0001 |
A 1.9-mW 750-kb/s 2.4-GHz F-OOK Transmitter With Symmetric FM Template and High-Point Modulation PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(10), pp. 2627-2635, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Jian Zhao 0004, Xi Wang 0004, Yang Zhao 0007, Guo Ming Xia, An Ping Qiu, Yan Su, Yong Ping Xu |
A 0.23-µg Bias Instability and 1-µg/√Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(4), pp. 1053-1065, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho |
A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(12), pp. 3446-3457, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Dongyi Liao, Hechen Wang, Fa Foster Dai, Yang Xu 0017, Roc Berenguer, Sara Munoz Hermoso |
An 802.11a/b/g/n Digital Fractional-N PLL With Automatic TDC Linearity Calibration for Spur Cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(5), pp. 1210-1220, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Ying Wu 0003, Mina Shahmohammadi, Yue Chen, Ping Lu 0002, Robert Bogdan Staszewski |
A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(7), pp. 1885-1903, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu |
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(9), pp. 2306-2320, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Menxi Xie, Huiqing Wen, Canyan Zhu, Yong Yang |
DC Offset Rejection Improvement in Single-Phase SOGI-PLL Algorithms: Methods Review and Experimental Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 5, pp. 12810-12819, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Zhao Zhang 0004, Liyuan Liu, Peng Feng 0001, Nanjian Wu |
A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(3), pp. 929-941, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim |
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(1), pp. 344-353, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Toru Nakura, Tetsuya Iizuka, Kunihiro Asada |
A PLL Compiler from Specification to GDSII. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12), pp. 2741-2749, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Zule Xu, Takayuki Kawahara |
A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 100-C(4), pp. 370-372, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Yu-Lung Lo, Wei-Hsiang Ho |
A Low-Voltage PLL Design Using a New Calibration Technique for Low-Power Implantable Biomedical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 36(12), pp. 4809-4828, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Xiaosen Liu, Adrian I. Colli-Menchi, Edgar Sánchez-Sinencio |
Ultrasonic Electric Scalpels Based on a Sliding-Mode Controller With an Auxiliary PLL Frequency Discriminator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 11(6), pp. 1226-1235, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Adesh Kumar, Gaurav Verma, Mukul Kumar Gupta |
FM Receiver Design Using Programmable PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 97(1), pp. 773-787, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Manas Kumar Hati, Tarun Kanti Bhattacharyya |
A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in ΔΣ fractional-N PLL frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 61, pp. 21-34, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Qiwei Huang, Chenchang Zhan, Jinwook Burm |
A low-complexity locking-accelerated digital PLL with multi-output bang-bang phase detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 67, pp. 19-24, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Umakanta Nanda, Debiprasad Priyabrata Acharya |
Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 64, pp. 92-98, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Jianfu Lin, Zheng Song 0002, Meng Wei 0001, Baoyong Chi |
A 6.6 mW 1.25-2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 66, pp. 119-127, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Diego Paolo Ferruzzo Correa, Átila M. Bueno, José Roberto Castilho Piqueira |
Stability of small-amplitude periodic solutions near Hopf bifurcations in time-delayed fully-connected PLL networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. Nonlinear Sci. Numer. Simul. ![In: Commun. Nonlinear Sci. Numer. Simul. 45, pp. 66-74, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Tianwei Liu, Xiaoran Wang, Rui Wang 0035, Guoying Wu, Tao Zhang 0034, Ping Gui |
A Temperature Compensated Triple-Path PLL With KVCO Non-Linearity Desensitization Capable of Operating at 77 K. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(11), pp. 2835-2843, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Sang-Geun Bae, Gyungmin Kim, Chulwoo Kim |
A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 64-II(10), pp. 1132-1136, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Federico Bizzarri, Angelo Brambilla, Sergio Callegari |
Efficient and Reliable Small-Signal Estimate of Quantization Noise Contribution to Phase Noise in ΔΣ Fractional-N PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(6), pp. 1494-1503, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Feiran Lei, Marvin H. White |
Reference Injected Phase-Locked Loops (PLL-RIs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7), pp. 1651-1660, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Zhikuang Cai, Haobo Xu, Shanwen Hu, Jun Yang |
Built-in jitter measurement circuit for PLL based on variable vernier delay line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(3), pp. 20161116, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Xincun Ji, Xiaojuan Xia, Zixuan Wang, Leisheng Jin |
A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(8), pp. 20170065, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Tao Yang 0022, Sichen Yu, Huixiang Han, Xiaolu Liu, Dashan Pan, Xi Tan, Na Yan, Fan Ye, Junyu Wang, Hao Min |
A 3.2-to-4.6 GHz fast-settling all-digital PLL with feed forward frequency presetting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(2), pp. 20161215, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Zhao Zhang 0004, Jincheng Yang, Liyuan Liu, Peng Feng 0001, Jian Liu 0021, Nanjian Wu |
A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(11), pp. 20170422, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Yajun He, Ziqiang Wang, Han Liu, Fangxu Lv, Shuai Yuan 0005, Chun Zhang, Zhihua Wang 0001, Hanjun Jiang |
An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 791-794, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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13 | Feiran Lei, Marvin H. White |
A low noise, inductor-less, integer-N RF synthesizer using phase-locked loop with reference injection (PLL-RI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 357-360, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
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