Search results for "RTL"

Hits ?▲	Authors	Title	Venue	Year	Link
15	John Adler, Andreas G. Veneris	Leveraging Software Configuration Management in Automated RTL Design Debug.	IEEE Des. Test	2017	DBLP DOI BibTeX RDF
15	Miroslav Siro, Dominik Macko, Katarína Jelemenská	PMS2UPF: An automated transition from ESL to RTL power-intent specification.	DDECS	2017	DBLP DOI BibTeX RDF
15	Michael Schwarz 0010, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz	Cycle-accurate software modeling for RTL verification of embedded systems.	DDECS	2017	DBLP DOI BibTeX RDF
15	L. Martirosyan	Easy to use evaluation of quality characteristics for a hierarchy of RTL compilers.	EWDTS	2017	DBLP DOI BibTeX RDF
15	Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer	RTLcheck: verifying the memory consistency of RTL designs.	MICRO	2017	DBLP DOI BibTeX RDF
15	John Adler, Ryan Berryhill, Andreas G. Veneris	An extensible perceptron framework for revision RTL debug automation.	ASP-DAC	2017	DBLP DOI BibTeX RDF
15	Binod Kumar 0001, Kanad Basu, Masahiro Fujita, Virendra Singh	RTL level trace signal selection and coverage estimation during post-silicon validation.	HLDVT	2017	DBLP DOI BibTeX RDF
15	Tonmoy Roy, Michael Hsiao	Reachability analysis in RTL circuits using k-induction bounded model checking.	HLDVT	2017	DBLP DOI BibTeX RDF
15	Florenc Demrozi, Riccardo Zucchelli, Graziano Pravadelli	Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL.	HLDVT	2017	DBLP DOI BibTeX RDF
15	Tobias Strauch	A Novel RTL ATPG Model Based on Gate Inherent Faults of Complex Gates.	MBMV	2017	DBLP BibTeX RDF
15	Yufei Ma 0002, Yu Cao 0001, Sarma B. K. Vrudhula, Jae-sun Seo	An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks.	FPL	2017	DBLP DOI BibTeX RDF
15	Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun 0003, Wei Zhang 0012, Jason Cong	FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates.	FCCM	2017	DBLP DOI BibTeX RDF
15	Ghaith Kazma, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria	Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories.	NEWCAS	2017	DBLP DOI BibTeX RDF
15	Sonal Pinto, Michael S. Hsiao	Fast Search-Based RTL Test Generation Using Control-Flow Path Guidance.	ICCD	2017	DBLP DOI BibTeX RDF
15	Alec Roelke, Runjie Zhang, Kaushik Mazumdar, Ke Wang 0011, Kevin Skadron, Mircea R. Stan	Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore Chips.	ICCD	2017	DBLP DOI BibTeX RDF
15	Alif Ahmed, Prabhat Mishra 0001	QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models.	ICCD	2017	DBLP DOI BibTeX RDF
15	Toshinori Hosokawa, Shun Takeda, Hiroshi Yamazaki, Masayoshi Yoshimura	Controller augmentation and test point insertion at RTL for concurrent operational unit testing.	IOLTS	2017	DBLP DOI BibTeX RDF
15	Charles Chia-Hao Hsu, Charles H.-P. Wen	Speeding up power verification by merging equivalent power domains in RTL design with UPF.	ITC-Asia	2017	DBLP DOI BibTeX RDF
15	Ghaith Kazma, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria	Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories.	ACM Great Lakes Symposium on VLSI	2017	DBLP DOI BibTeX RDF
15	Liyi Xiao, Anlong Li, Xuebing Cao, Hongchen Li, Rongsheng Zhang, Jie Li 0030, Tianqi Wang	A method to estimate cross-section of circuits at RTL levels.	ASICON	2017	DBLP DOI BibTeX RDF
15	Kelson Gent, Akash Agrawal, Michael S. Hsiao	A framework for fast test generation at the RTL.	VTS	2017	DBLP DOI BibTeX RDF
15	Sonal Pinto, Michael S. Hsiao	RTL functional test generation using factored concolic execution.	ITC	2017	DBLP DOI BibTeX RDF
15	Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle	Analysis of laser-induced errors: RTL fault models versus layout locality characteristics.	Microprocess. Microsystems	2016	DBLP DOI BibTeX RDF
15	Tobias Strauch	A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates.	CoRR	2016	DBLP BibTeX RDF
15	Yu Zhang 0071, Wenlong Feng, Mengxing Huang	Automatic Generation of High-Coverage Tests for RTL Designs using Software Techniques and Tools.	CoRR	2016	DBLP BibTeX RDF
15	Cheng C. Wang, Dejan Markovic	Reconfigure your RTL with EFLX join the SoC revolution.	Hot Chips Symposium	2016	DBLP DOI BibTeX RDF
15	Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra 0001, Yier Jin	Automatic RTL-to-Formal Code Converter for IP Security Formal Verification.	MTV	2016	DBLP DOI BibTeX RDF
15	Zissis Poulos, Ryan Berryhill, John Adler, Andreas G. Veneris	On simulation-based metrics that characterize the behavior of RTL errors.	SummerSim	2016	DBLP BibTeX RDF
15	Haytham Saafan, M. Watheq El-Kharashi, Ashraf Salem	SoC connectivity specification extraction using incomplete RTL design: An approach for Formal connectivity Verification.	IDT	2016	DBLP DOI BibTeX RDF
15	Kelson Gent, Michael S. Hsiao	Fast Multi-level Test Generation at the RTL.	ISVLSI	2016	DBLP DOI BibTeX RDF
15	L. Martirosyan	A quality characteristics estimation methodology for the hierarchy of RTL compilers.	EWDTS	2016	DBLP DOI BibTeX RDF
15	Hamed Najafi Haghi, Mikhail M. Chupilko, Alexander S. Kamkin, Zainalabedin Navabi	ESL design with RTL-verified predesigned abstract communication channels.	EWDTS	2016	DBLP DOI BibTeX RDF
15	Charalampos Ananiadis, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle	On the development of a new countermeasure based on a laser attack RTL fault model.	DATE	2016	DBLP BibTeX RDF
15	William Diehl, Kris Gaj	RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two.	DSD	2016	DBLP DOI BibTeX RDF
15	Dustin Peterson, Oliver Bringmann 0001	SMoSi: A framework for the derivation of sleep mode traces from RTL simulations.	ASP-DAC	2016	DBLP DOI BibTeX RDF
15	Qinhao Wang, Yusuke Kimura, Masahiro Fujita	Automatically adjusting system level designs after RTL/gate-level ECO.	HLDVT	2016	DBLP DOI BibTeX RDF
15	Tomás Grimm, Djones Lettnin, Michael Hübner 0001	Automatic generation of RTL connectivity checkers from SystemC TLM and IP-XACT descriptions.	NORCAS	2016	DBLP DOI BibTeX RDF
15	Yufei Ma 0002, Naveen Suda, Yu Cao 0001, Jae-sun Seo, Sarma B. K. Vrudhula	Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.	FPL	2016	DBLP DOI BibTeX RDF
15	Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Sungkwan Ku, Eric Rotenberg	AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores.	ISPASS	2016	DBLP DOI BibTeX RDF
15	William Diehl, Kris Gaj	High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two.	FCCM	2016	DBLP DOI BibTeX RDF
15	Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler	On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study.	FDL	2016	DBLP DOI BibTeX RDF
15	H. Mohamed, Pavlos I. Lazaridis, David Upton, Umar F. Khan, Bahghtar Saeed, Adel Jaber, Yong Zhang 0054, Peter Mather, Maria F. Q. Vieira, K. W. Barlee, D. S. W. Atkinson, Albena Mihovska, Liljana Gavrilovska, Ian A. Glover	Partial discharge detection using low cost RTL-SDR model for wideband spectrum sensing.	ICT	2016	DBLP DOI BibTeX RDF
15	Liang Wang 0055, Kevin Skadron	Lumos+: Rapid, pre-RTL design space exploration on accelerator-rich heterogeneous architectures with reconfigurable logic.	ICCD	2016	DBLP DOI BibTeX RDF
15	Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria	Towards formal abstraction, modeling, and analysis of Single Event Transients at RTL.	ISCAS	2016	DBLP DOI BibTeX RDF
15	Romain Champon, Vincent Beroulle, Athanasios Papadimitriou, David Hély, Gilles Genévrier, Frédéric Cézilly	Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices.	IOLTS	2016	DBLP DOI BibTeX RDF
15	Jaime Espinosa, Carles Hernández 0001, Jaume Abella 0001	Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection.	IOLTS	2016	DBLP DOI BibTeX RDF
15	Jian Hu, Tun Li, Sikun Li	Equivalence checking between SLM and RTL using machine learning techniques.	ISQED	2016	DBLP DOI BibTeX RDF
15	Khaled Khalifa, Khaled Salah 0001	An RTL power optimization technique based on System Verilog assertions.	UEMCON	2016	DBLP DOI BibTeX RDF
15	Donggyu Kim, Adam M. Izraelevitz, Christopher Celio, Hokeun Kim, Brian Zimmer, Yunsup Lee, Jonathan Bachrach, Krste Asanovic	Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL.	ISCA	2016	DBLP DOI BibTeX RDF
15	Ashish Sharma 0005, Ruby Ansar, Manoj Singh Gaur, Lava Bhargava, Vijay Laxmi	Reducing FIFO buffer power using architectural alternatives at RTL.	VDAT	2016	DBLP DOI BibTeX RDF
15	Sri Harsha Gade, Praveen Kumar, Sujay Deb	A Pre-RTL floorplanner tool for automated CMP design space exploration with thermal awareness.	VDAT	2016	DBLP DOI BibTeX RDF
15	Tom Davidson, Elias Vansteenkiste, Karel Heyse, Karel Bruneel, Dirk Stroobandt	Identification of Dynamic Circuit Specialization Opportunities in RTL Code.	ACM Trans. Reconfigurable Technol. Syst.	2015	DBLP DOI BibTeX RDF
15	Elias Kougianos, Saraju P. Mohanty	A nature-inspired firefly algorithm based approach for nanoscale leakage optimal RTL structure.	Integr.	2015	DBLP DOI BibTeX RDF
15	Robert W. Stewart, Louise Crockett, Dale Atkinson, Kenneth Barlee, David H. Crawford, Iain Chalmers, Mike McLernon, Ethem Sozer	A low-cost desktop software defined radio design environment using MATLAB, simulink, and the RTL-SDR.	IEEE Commun. Mag.	2015	DBLP DOI BibTeX RDF
15	Bijan Alizadeh, Payman Behnam, Somayeh Sadeghi Kohan	A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.	IEEE Trans. Computers	2015	DBLP DOI BibTeX RDF
15	Raghuraman Balasubramanian, Vinay Gangadhar, Ziliang Guo, Chen-Han Ho, Cherin Joseph, Jaikrishnan Menon, Mario Paulo Drumond, Robin Paul, Sharath Prasad, Pradip Valathol, Karthikeyan Sankaralingam	Enabling GPGPU Low-Level Hardware Explorations with MIAOW: An Open-Source RTL Implementation of a GPGPU.	ACM Trans. Archit. Code Optim.	2015	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Francesco Stefanni, Tara Ghasempouri, Michele Lora, Giovanni Auditore, Mirella Negro Marcigaglia	Reusing RTL Assertion Checkers for Verification of SystemC TLM Models.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
15	Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang	A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
15	Liang Chen 0014, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori	Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control Paths.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Franco Fummi, Sara Vinco	A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications.	ACM Trans. Design Autom. Electr. Syst.	2015	DBLP DOI BibTeX RDF
15	Jordi Cortadella, Marc Galceran Oms, Michael Kishinevsky, Sachin S. Sapatnekar	RTL Synthesis: From Logic Synthesis to Automatic Pipelining.	Proc. IEEE	2015	DBLP DOI BibTeX RDF
15	Syed Saif Abrar, Maksim Jenihhin, Jaan Raik	SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores.	DDECS	2015	DBLP DOI BibTeX RDF
15	Khyati Vachhani, Arvind Mallari Rao	Experimental study on wide band FM receiver using GNURadio and RTL-SDR.	ICACCI	2015	DBLP DOI BibTeX RDF
15	Syed Saif Abrar, Maksim Jenihhin, Jaan Raik	FSMD RTL design manipulation for clock interface abstraction.	ICACCI	2015	DBLP DOI BibTeX RDF
15	David J. Greaves	Layering RTL, SAFL, Handel-C and Bluespec constructs on Chisel HCL.	MEMOCODE	2015	DBLP DOI BibTeX RDF
15	Prateek Puri, Michael S. Hsiao	Fast Stimuli Generation for Design Validation of RTL Circuits Using Binary Particle Swarm Optimization.	ISVLSI	2015	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Riccardo Filippozzi, Graziano Pravadelli, Francesco Stefanni	RTL property abstraction for TLM assertion-based verification.	DATE	2015	DBLP BibTeX RDF
15	Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao	Branch guided functional test generation at the RTL.	ETS	2015	DBLP DOI BibTeX RDF
15	Jianlei Yang 0001, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai	Early stage real-time SoC power estimation using RTL instrumentation.	ASP-DAC	2015	DBLP DOI BibTeX RDF
15	Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz	Architectural System Modeling for Correct-by-Construction RTL Design.	MBMV	2015	DBLP BibTeX RDF
15	Michael Papamichael, Cagla Cakir, Chen Sun 0003, Chia-Hsin Owen Chen, James C. Hoe, Ken Mai, Li-Shiuan Peh, Vladimir Stojanovic	DELPHI: a framework for RTL-based architecture design evaluation using DSENT models.	ISPASS	2015	DBLP DOI BibTeX RDF
15	Amani Darwish, Laurent Fesquet, Gilles Sicard	RTL simulation of an asynchronous reading architecture for an event-driven image sensor.	EBCCSP	2015	DBLP DOI BibTeX RDF
15	Shimpei Sato, Kenji Kise	ArchHDL: A Novel Hardware RTL Design Environment in C++.	ARC	2015	DBLP DOI BibTeX RDF
15	E. G. Sierra, Germán Augusto Ramírez Arroyave	Low cost SDR spectrum analyzer and analog radio receiver using GNU radio, raspberry Pi2 and SDR-RTL dongle.	LATINCOM	2015	DBLP DOI BibTeX RDF
15	Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz	Architectural system modeling for correct-by-construction RTL design.	FDL	2015	DBLP DOI BibTeX RDF
15	Veselin N. Ivanovic, Nevena Radovic, Srdjan Jovanovski, Zdravko Uskokovic	Local frequency estimation-based space/spatial-frequency optimal filter developed in the RTL design methodology versus the corresponding GPU-based implementations.	MECO	2015	DBLP DOI BibTeX RDF
15	Raghuraman Balasubramanian, Vinay Gangadhar, Ziliang Guo, Chen-Han Ho, Cherin Joseph, Jaikrishnan Menon, Mario Paulo Drumond, Robin Paul, Sharath Prasad, Pradip Valathol, Karthikeyan Sankaralingam	MIAOW - An open source RTL implementation of a GPGPU.	COOL Chips	2015	DBLP DOI BibTeX RDF
15	Andrew Becker, Djordje Maksimovic, David Novo, Mohsen Ewaida, Andreas G. Veneris, Barbara Jobstmann, Paolo Ienne	FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction.	Haifa Verification Conference	2015	DBLP DOI BibTeX RDF
15	Vijay Kiran Kalyanam, Martin Saint-Laurent, Jacob A. Abraham	Power-aware multi-voltage custom memory models for enhancing RTL and low power verification.	ICCD	2015	DBLP DOI BibTeX RDF
15	Prateek Puri, Michael S. Hsiao	SI-SMART: Functional test generation for RTL circuits using loop abstraction and learning recurrence relationships.	ICCD	2015	DBLP DOI BibTeX RDF
15	Jian Hu, Tun Li, Sikun Li	Formal equivalence checking between SLM and RTL descriptions.	SoCC	2015	DBLP DOI BibTeX RDF
15	Mark A. Wickert, McKenna R. Lovejoy	Hands-on software defined radio experiments with the low-cost RTL-SDR dongle.	SP/SPE	2015	DBLP DOI BibTeX RDF
15	Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang	Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS.	LATS	2015	DBLP DOI BibTeX RDF
15	Athanasios Papadimitriou, Marios Tampas, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle	Validation of RTL laser fault injection model with respect to layout information.	HOST	2015	DBLP DOI BibTeX RDF
15	Sharad Bagri, Kelson Gent, Michael S. Hsiao	Signal domain based reachability analysis in RTL circuits.	ISQED	2015	DBLP DOI BibTeX RDF
15	Spandana Rachamalla, Arun Joseph, Rahul M. Rao, Diwesh Pandey	Virtual logic netlist: Enabling efficient RTL analysis.	ISQED	2015	DBLP DOI BibTeX RDF
15	Wen-Ping Lee, Cheng-Yen Wang	Reusable and flexible verification methodology from architecture to RTL design.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
15	Nicole Fern, Shrikant Kulkarni, Kwang-Ting (Tim) Cheng	Hardware Trojans hidden in RTL don't cares - Automated insertion and prevention methodologies.	ITC	2015	DBLP DOI BibTeX RDF
15	Jaime Espinosa, Carles Hernández 0001, Jaume Abella 0001, David de Andrés, Juan-Carlos Ruiz-Garcia	Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification.	DAC	2015	DBLP DOI BibTeX RDF
15	Tiago Rogério Mück, Antônio Augusto Fröhlich	Aspect-oriented RTL HW design using SystemC.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
15	Hratch Mangassarian, Bao Le, Andreas G. Veneris	Debugging RTL Using Structural Dominance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
15	Lingyi Liu, Shobha Vasudevan	Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL.	ACM Trans. Design Autom. Electr. Syst.	2014	DBLP DOI BibTeX RDF
15	Abhishek Jain 0003, Hima Gupta, Sandeep Jana, Krishna Kumar	Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL.	CoRR	2014	DBLP BibTeX RDF
15	Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke	Automated Design Error Localization in RTL Designs.	IEEE Des. Test	2014	DBLP DOI BibTeX RDF
15	Tariq Bashir Ahmad, Maciej J. Ciesielski	Fast time-parallel C-based event-driven RTL simulation.	DDECS	2014	DBLP DOI BibTeX RDF
15	Carla Purdy, Chandan Singh, Rashna Seli	Fixing power bugs at RTL stage using PSL assertions.	MWSCAS	2014	DBLP DOI BibTeX RDF
15	Tomoaki Sato, Sorawat Chivapreecha, Phichet Moungnoul	Wiring control by RTL design for reconfigurable wave-pipelined circuits.	APSIPA	2014	DBLP DOI BibTeX RDF
15	Zeineb Bel Hadj Amor, Laurence Pierre, Dominique Borrione	A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
15	Shilpa Pendyala, Srinivas Katkoori	Interval Arithmetic and Self Similarity Based Subthreshold Leakage Optimization in RTL Datapaths.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
15	Shilpa Pendyala, Srinivas Katkoori	Self similarity and interval arithmetic based leakage optimization in RTL datapaths.	VLSI-SoC	2014	DBLP DOI BibTeX RDF