Search results for "coprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Hoseok Chang, Junho Cho, Wonyong Sung	Compiler-Based Performance Evaluation of an SIMD Processor with a Multi-Bank Memory Unit.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Multi-bank memory, Vectorizing compiler, Data allocation, On-chip memory, SIMD processor
11	Sorin Alexander Huss	Embedded systems for IT security applications: properties and design considerations.	SIN	2009	DBLP DOI BibTeX RDF	fpga, embedded systems, cryptography, system-on-chip
11	Daniela Genius, Alix Munier Kordon, Khouloud Zine el Abidine	A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor.	Euro-Par	2009	DBLP DOI BibTeX RDF
11	Fabian Scheler, Wanja Hofer, Benjamin Oechslein, Rudi Pfister, Wolfgang Schröder-Preikschat, Daniel Lohmann	Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system.	CASES	2009	DBLP DOI BibTeX RDF	ciao, priority-driven, rate-monotonic priority inversion, tricore, real-time systems, interrupt handling
11	Thomas Popp, Mario Kirschbaum, Stefan Mangard	Practical Attacks on Masked Hardware.	CT-RSA	2009	DBLP DOI BibTeX RDF	DPA-Resistant Masked Logic Styles, MDPL, Prototype Chip, Hardware AES, PDF-Attack, PRNG
11	François Bodin	Keynote: Compilers in the Manycore Era.	HiPEAC	2009	DBLP DOI BibTeX RDF
11	Jason D. Bakos, Panormitis E. Elenis	A Special-Purpose Architecture for Solving the Breakpoint Median Problem.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
11	Camille Vuillaume, Katsuyuki Okeya, Tsuyoshi Takagi	Short-Memory Scalar Multiplication for Koblitz Curves.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Efficiency, Public key cryptosystems, Smartcards, Koblitz Curves
11	Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Masaaki Shirase, Tsuyoshi Takagi	Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
11	Fabrice Urban, Ronan Poullaouec, Jean-François Nezan, Olivier Déforges	A Flexible Heterogeneous Hardware/Software Solution for Real-Time HD H.264 Motion Estimation.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
11	Boguslaw Szlachetko, Andrzej Lewandowski	FPGA Implementation of the Gradient Adaptive Lattice Filter Structure for Feature Extraction.	Computer Recognition Systems 2	2008	DBLP DOI BibTeX RDF
11	Xu Guo 0001, Zhimin Chen 0002, Patrick Schaumont	Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors.	SAMOS	2008	DBLP DOI BibTeX RDF
11	Yaping Li, Minghua Chen 0001	Privacy Preserving Joins.	ICDE	2008	DBLP DOI BibTeX RDF
11	Junfeng Fan, Lejla Batina, Kazuo Sakiyama, Ingrid Verbauwhede	FPGA Design for Algebraic Tori-Based Public-Key Cryptography.	DATE	2008	DBLP DOI BibTeX RDF
11	Magnus Själander, Andrei Sergeevich Terechko, Marc Duranton	A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures.	DSD	2008	DBLP DOI BibTeX RDF
11	Alexander Klimm, Oliver Sander, Jürgen Becker 0001, Sylvain Subileau	A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA.	ARCS	2008	DBLP DOI BibTeX RDF	Hyperelliptic Curve Cryptography (HECC), FPGA, embedded systems, Public Key Cryptography (PKC), reconfigurable hardware
11	Rong Dong, David Hermann, Robert L. Brennan, Edward Chau	Joint filterbank structures for integrating audio coding into hearing aid applications.	ICASSP	2008	DBLP DOI BibTeX RDF
11	Enrique Cantó, Francesc Fons, Mariano López	Self-recofigurable embedded systems on Spartan-3.	FPL	2008	DBLP DOI BibTeX RDF
11	Zhijun Wang 0001, Hao Che, Jiannong Cao 0001	An Integrated Solution for Policy Filtering and Traffic Anomaly Detection.	ATC	2008	DBLP DOI BibTeX RDF
11	Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli	ADAPTO: full-adder based reconfigurable architecture for bit level operations.	ISCAS	2008	DBLP DOI BibTeX RDF
11	Jian Wang, Gang Hua 0003	Implementing high definition video codec on TI DM6467 SOC.	SoCC	2008	DBLP DOI BibTeX RDF
11	Holger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann, Peter Pirsch	A parallel hardware architecture for connected component labeling based on fast label merging.	ASAP	2008	DBLP DOI BibTeX RDF
11	Darren Moore	Demonstration of bird species detection using an acoustic wireless sensor network.	LCN	2008	DBLP DOI BibTeX RDF
11	Ankush Varma, Bruce L. Jacob, Eric Debes, Igor Kozintsev, Paul Klein	Accurate and fast system-level power modeling: An XScale-based case study.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	embedded systems, SystemC, Power modeling
11	Fred B. Schneider	Trusted Computing in Context.	IEEE Secur. Priv.	2007	DBLP DOI BibTeX RDF
11	Rami Rom, Jacob Erel, Michael Glikson, Randy A. Lieberman, Kobi Rosenblum, Ofer Binah, Ran Ginosar, David L. Hayes 0001	Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme.	IEEE Trans. Neural Networks	2007	DBLP DOI BibTeX RDF
11	Eric Simpson, Pengyuan Yu, Patrick Schaumont, Sumit Ahuja, Sandeep K. Shukla	VT Matrix Multiply Design for MEMOCODE '07.	MEMOCODE	2007	DBLP DOI BibTeX RDF
11	Giovanni Danese, Francesco Leporati, Marco Bera, Mauro Giachero, Nelson Nazzicari, Alvaro Spelgatti	An Application Specific Processor for Montecarlo Simulations.	PDP	2007	DBLP DOI BibTeX RDF
11	Hadi Moradi, Eun Kwon, Dae Neung Sohn, JungHyun Han	A Real-Time GPU-Based Wall Detection Algorithm for Mapping and Navigation in Indoor Environments.	HCI (9)	2007	DBLP DOI BibTeX RDF
11	Xiandong Meng, Vipin Chaudhary	An adaptive data prefetching scheme for biosequence database search on reconfigurable platforms.	SAC	2007	DBLP DOI BibTeX RDF	FPGA, data prefetching, DMA, Smith-Waterman algorithm
11	Shigeru Yamashita, Masaki Nakanishi	A practical framework to utilize quantum search.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
11	Mei Wen, Nan Wu 0003, Chunyuan Zhang, Wei Wu, Qianming Yang, Changqing Xun	FT64: Scientific Computing with Streams.	HiPC	2007	DBLP DOI BibTeX RDF
11	Yusaku Yamamoto, Takeshi Fukaya, Takashi Uneyama, Masami Takata, Kinji Kimura, Masashi Iwasaki, Yoshimasa Nakamura	Accelerating the Singular Value Decomposition of Rectangular Matrices with the CSX600 and the Integrable SVD.	PaCT	2007	DBLP DOI BibTeX RDF
11	Ahmed Sherif Zekri, Stanislav G. Sedukhin	Performance Evaluation of Basic Linear Algebra Subroutines on a Matrix Co-processor.	PPAM	2007	DBLP DOI BibTeX RDF
11	Libo Huang, Ming-che Lai, Kui Dai, Hong Yue, Li Shen 0007	Hardware Support for Arithmetic Units of Processor with Multimedia Extension.	MUE	2007	DBLP DOI BibTeX RDF
11	Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano	Performance Improvement Methodology for ClearSpeed's CSX600.	ICPP	2007	DBLP DOI BibTeX RDF
11	Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto	Arithmetic Operators for Pairing-Based Cryptography.	CHES	2007	DBLP DOI BibTeX RDF	FPGA, elliptic curve, hardware accelerator, finite field arithmetic, ? T pairing
11	Venkata Krishnan	Towards an integrated IO and clustering solution using PCI express.	CLUSTER	2007	DBLP DOI BibTeX RDF
11	Seng Lin Shee, Sri Parameswaran	Design Methodology for Pipelined Heterogeneous Multiprocessor System.	DAC	2007	DBLP DOI BibTeX RDF
11	Nigel C. Paver, Moinul H. Khan, Bradley C. Aldrich	Optimizing mobile multimedia using SIMD techniques.	Multim. Tools Appl.	2006	DBLP DOI BibTeX RDF	Multimedia, Mobile, Architecture, Programming, SIMD
11	Sridhar Rajagopal, Joseph R. Cavallaro	Truncated Online Arithmetic with Applications to Communication Systems.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Dynamic truncation, finite precision, communication systems, online arithmetic
11	Mauricio Varea, Bashir M. Al-Hashimi, Luis Alejandro Cortés, Petru Eles, Zebo Peng	Dual Flow Nets: Modeling the control/data-flow relation in embedded systems.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Dual flow nets, tripartite graph, modeling, embedded systems, Petri nets, formal verification, symbolic model checking, CTL, LTL
11	Carsten Albrecht, Andreas C. Döring, Frank Penczek, Torben Schneider, Hannes Schulz	Impact of Coprocessors on a Multithreaded Processor Design Using Prioritized Threads.	PDP	2006	DBLP DOI BibTeX RDF
11	Götz Kappen, Tobias G. Noll	Application specific instruction processor based implementation of a GNSS receiver on an FPGA.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
11	Min Wu, Xiaoyang Zeng, Jun Han 0003, Yongyi Wu, Yibo Fan	A high-performance platform-based SoC for information security.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Petros Oikonomakos, Jacques J. A. Fournier, Simon W. Moore	Implementing Cryptography on TFT Technology for Secure Display Applications.	CARDIS	2006	DBLP DOI BibTeX RDF
11	Jianjun Guo, Kui Dai, Zhiying Wang 0003	A High Performance Heterogeneous Architecture and Its Optimization Design.	HPCC	2006	DBLP DOI BibTeX RDF	SDTA, ASIP, Data Parallel
11	Chun-Hua Chen, Jinn-ke Jan, Chao-Hsing Hsu	One-Server Private Information Retrieval Scheme combined with Mutual Authentication by ElGamal Signature.	ICICIC (3)	2006	DBLP DOI BibTeX RDF
11	Bishwaranjan Bhattacharjee, Naoki Abe, Kenneth A. Goldman, Bianca Zadrozny, Vamsavardhana R. Chillakuru, Marysabel del Carpio, Chidanand Apté	Using secure coprocessors for privacy preserving collaborative data mining and analysis.	DaMoN	2006	DBLP DOI BibTeX RDF	data mining, privacy, collaboration, federation
11	Francisco Fons, Mariano Fons, Enrique Cantó, Mariano López	Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip.	ARC	2006	DBLP DOI BibTeX RDF
11	Manhee Lee, Eun Jung Kim 0001, Ki Hwan Yum, Mazin S. Yousif	An Overview of Security Issues in Cluster Interconnects.	CCGRID	2006	DBLP DOI BibTeX RDF
11	Yongxin Ma, Xiaoyang Zeng, Min Wu, Chengshou Sun	A new low cost and reconfigurable RSA crypto-processor.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet	Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor.	IOLTS	2006	DBLP DOI BibTeX RDF
11	Nizamettin Aydin, Tughrul Arslan	Power Driven Reconfigurable Complex Continuous Wavelet Transform.	AHS	2006	DBLP DOI BibTeX RDF
11	Thomas J. Wollinger, Guido Bertoni, Luca Breveglieri, Christof Paar	Performance of HECC Coprocessors Using Inversion-Free Formulae.	ICCSA (3)	2006	DBLP DOI BibTeX RDF
11	Rama Sangireddy, Prabhu Rajamani, Shwetha Gaddam	Performance Optimization with Scalable Reconfigurable Computing Systems.	VLSI Design	2006	DBLP DOI BibTeX RDF
11	Marc Joye, Pascal Paillier	Fast Generation of Prime Numbers on Portable Devices: An Update.	CHES	2006	DBLP DOI BibTeX RDF
11	Nigel C. Paver, Moinul H. Khan, Bradley C. Aldrich, Christopher D. Emmons	Accelerating Mobile Video: A 64-Bit SIMD Architecture for Handheld Applications.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	architecture, SIMD, SOC, multi-media, wireless video
11	Arnaldo S. R. Oliveira, Valery Sklyarov, António de Brito Ferrari	ARPA - A Technology Independent and Synthetizable System-on-Chip Model for Real-Time Applications.	DSD	2005	DBLP DOI BibTeX RDF
11	Tom Van Court, Yongfeng Gu, Martin C. Herbordt	Three-Dimensional Template Correlation: Object Recognition in 3D Voxel Data.	CAMP	2005	DBLP DOI BibTeX RDF
11	Chun-Hua Chen, Chi-Min Lan, Gwoboa Horng	Protecting Customer's Privacy in Querying Valuable Information Combined with E-Payment Scheme.	ICITA (2)	2005	DBLP DOI BibTeX RDF
11	Nicolau Canyellas, Enrique Cantó, Giuseppe Forte, Mariano López	Hardware-Software Codesign of a Fingerprint Identification Algorithm.	AVBPA	2005	DBLP DOI BibTeX RDF
11	Yuxing Tang, Kun Deng, HongJia Cao, Xingming Zhou	Trace-Based Runtime Instruction Rescheduling for Architecture Extension.	ICESS	2005	DBLP DOI BibTeX RDF
11	Young H. Cho, William H. Mangione-Smith	Fast Reconfiguring Deep Packet Filter for 1+ Gigabit Network.	FCCM	2005	DBLP DOI BibTeX RDF
11	Flavius Gruian, Zoran A. Salcic	Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
11	Henrik Svensson, Viktor Öwall, Krzysztof Kuchcinski	Implementation aspects of a novel speech packet loss concealment method.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
11	Chun-Hua Chen, Chi-Min Lan, Gwoboa Horng	A practical voting system for small-scale election.	ITRE	2005	DBLP DOI BibTeX RDF
11	Seraj Ahmad, Rabi N. Mahapatra	TCAM enabled on-chip logic minimization.	DAC	2005	DBLP DOI BibTeX RDF	on-chip, logic minimization, TCAM
11	Kenneth A. Goldman, Enriquillo Valdez	Matchbox: Secure Data Sharing.	IEEE Internet Comput.	2004	DBLP DOI BibTeX RDF
11	Rama Sangireddy, Huesung Kim, Arun K. Somani	Low-Power High-Performance Reconfigurable Computing Cache Architectures.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
11	Prabhat Mishra 0001, Nikil D. Dutt	Modeling and validation of pipeline specifications.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	Modeling of processor pipeline, pipeline validation, pipelined processor specification, architecture description language
11	Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo	The design of dynamically reconfigurable datapath coprocessors.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	coarse-grain reconfigurable fabric, reconfigurable datapath, Loop pipelining, interconnection design, datapath synthesis
11	Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne	Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors.	DATE	2004	DBLP DOI BibTeX RDF
11	Roman L. Lysecky, Frank Vahid	A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning.	DATE	2004	DBLP DOI BibTeX RDF	FPGA fabric, self-improving chips, synthesis, reconfigurable computing, dynamic optimization, system-on-a-chip, platforms, codesign, Hardware/software partitioning, just-in-time compilation, configurable logic, place and route, warp processors
11	Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger	Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards.	DATE	2004	DBLP DOI BibTeX RDF
11	Patrick Schaumont, Ingrid Verbauwhede	Interactive Cosimulation with Partial Evaluation.	DATE	2004	DBLP DOI BibTeX RDF
11	Imed Aouadi, Omar Hammami	Analysis and Hardware Design of a Scalable Dual JPEG-2000 Entropy Coder.	DSD	2004	DBLP DOI BibTeX RDF
11	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors.	FPL	2004	DBLP DOI BibTeX RDF
11	Enrique Cantó, Nicolau Canyellas, Mariano Fons, Francisco Fons, Mariano López	FPGA Implementation of the Ridge Line Following Fingerprint Algorithm.	FPL	2004	DBLP DOI BibTeX RDF
11	Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer	FPGA Custom DSP for ECG Signal Analysis and Compression.	FPL	2004	DBLP DOI BibTeX RDF
11	Jun-Cheol Jeon, Kee-Young Yoo	An Evolutionary Approach to the Design of Cellular Automata Architecture for Multiplication in Elliptic Curve Cryptography over Finite Fields.	PRICAI	2004	DBLP DOI BibTeX RDF	Evolutionary Computation, Cellular Automata, Finite Fields, Elliptic Curve Cryptography, Multiplication, Irreducible Polynomial
11	Kuen Hung Tsoi, Chun Hok Ho, Jackson H. C. Yeung, Philip Heng Wai Leong	An Arithmetic Library and Its Application to the N-body Problem.	FCCM	2004	DBLP DOI BibTeX RDF
11	Ju-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo	A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications.	Graphics Hardware	2004	DBLP DOI BibTeX RDF
11	Markus Lorch, Jim Basney, Dennis G. Kafura	A hardware-secured credential repository for Grid PKIs.	CCGRID	2004	DBLP DOI BibTeX RDF
11	Howon Kim 0001, Thomas J. Wollinger, YongJe Choi, Kyoil Chung, Christof Paar	Hyperelliptic Curve Coprocessors on a FPGA.	WISA	2004	DBLP DOI BibTeX RDF
11	Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt	Introduction of local memory elements in instruction set extensions.	DAC	2004	DBLP DOI BibTeX RDF	ad-hoc functional units, genetic algorithm, ASIPs, coprocessors, instruction set extensions, customizable processors
11	Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang	Active Memory Processor: A Hardware Garbage Collector for Real-Time Java Embedded Devices.	IEEE Trans. Mob. Comput.	2003	DBLP DOI BibTeX RDF	active memory, real-time systems, embedded systems, Garbage collection, Java virtual machine
11	Tilman Glökler, Andreas Hoffmann 0002, Heinrich Meyr	Methodical Low-Power ASIP Design Space Exploration.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	ICORE, low power, ASIP, application-specific instruction set processor, low energy, LISA
11	Martin Simka, Viktor Fischer, Milos Drutarovský	Hardware-Software Codesign in Embedded Asymmetric Cryptographiy Application - A Case Study.	FPL	2003	DBLP DOI BibTeX RDF
11	Mehdi-Laurent Akkar, Nicolas T. Courtois, Romain Duteuil, Louis Goubin	A Fast and Secure Implementation of Sflash.	Public Key Cryptography	2003	DBLP DOI BibTeX RDF	Matsumoto-Imai cryptosystem C, C- trapdoor function, Digital Signatures, Smart cards, DPA, PKI, Power Analysis, SPA, portable devices, Addition Chains, Multivariate Cryptography, HFE
11	Osvaldo Colavin, Davide Rizzo	A scalable wide-issue clustered VLIW with a reconfigurable interconnect.	CASES	2003	DBLP DOI BibTeX RDF	clustered VLIW, reconfigurable co-processor (RCP), modulo scheduling, IDCT
11	Premkumar T. Devanbu, Stuart G. Stubblebine	Stack and Queue Integrity on Hostile Platforms.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	correctness of memories, oblivious ram, security, data structures, software protection
11	Domingo Benitez	Performance of Remote FPGA-Based Coprocessors for Image-Processing Applications.	DSD	2002	DBLP DOI BibTeX RDF
11	Rama Sangireddy, Huesung Kim, Arun K. Somani	Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing.	HiPC	2002	DBLP DOI BibTeX RDF
11	Jan Schmidt, Martin Novotný, Martin Jäger, Milos Becvár, Michal Jáchim	Exploration of Design Space in ECDSA.	FPL	2002	DBLP DOI BibTeX RDF
11	Stephen Charlwood, Jonathan Mangnall, Steven F. Quigley	System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors.	FPL	2002	DBLP DOI BibTeX RDF
11	Tim Kerins, Emanuel M. Popovici, William P. Marnane, Patrick Fitzpatrick	Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2).	FPL	2002	DBLP DOI BibTeX RDF
11	Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner	Fly - A Modifiable Hardware Compiler.	FPL	2002	DBLP DOI BibTeX RDF
11	Chris Lattner, Shashank Shekhar, Anand Shukla, Vikram S. Adve	Addressing Fundamental Bottlenecks in Link-Time and Dynamic Optimization.	IPDPS	2002	DBLP DOI BibTeX RDF
11	Wieland Fischer, Jean-Pierre Seifert	Note on Fast Computation of Secret RSA Exponents.	ACISP	2002	DBLP DOI BibTeX RDF	Carmichael's $lambda$-function, Secret exponent, Short public key, RSA, Chinese Remainder Theorem, Key generation