Search results for "datapath"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Yang Sun 0001, Joseph R. Cavallaro	A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards.	SoCC	2008	DBLP DOI BibTeX RDF
9	Saraju P. Mohanty	ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis.	ISQED	2008	DBLP DOI BibTeX RDF
9	Ravi Surepeddi	System Verilog for Quality of Results (QoR).	ISQED	2008	DBLP DOI BibTeX RDF	System Verilog Design Quality Results
9	Sabyasachi Das, Sunil P. Khatri	An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products.	VLSI Design	2008	DBLP DOI BibTeX RDF
9	Sean O'Melia, Adam J. Elbirt	Instruction Set Extensions for Enhancing the Performance of Symmetric-Key Cryptography.	ACSAC	2008	DBLP DOI BibTeX RDF
9	Jad Naous, David Erickson, G. Adam Covington, Guido Appenzeller, Nick McKeown	Implementing an OpenFlow switch on the NetFPGA platform.	ANCS	2008	DBLP DOI BibTeX RDF	flow switching, computer networks, packet switching, programmable networks, OpenFlow, NetFPGA
9	George R. Roelke, Rusty O. Baldwin, Barry E. Mullins, Yong C. Kim	A Cache Architecture for Extremely Unreliable Nanotechnologies.	IEEE Trans. Reliab.	2007	DBLP DOI BibTeX RDF
9	Lesley Shannon, Paul Chow	SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
9	Montek Singh, Steven M. Nowick	The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
9	Brandon J. Jasionowski, Michelle K. Lay, Martin Margala	A Processor-In-Memory Architecture for Multimedia Compression.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
9	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
9	Ka-Ming Keung, Vineela Manne, Akhilesh Tyagi	A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
9	Han Liang, Piyush Mishra, Kaijie Wu 0001	Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Concurrent error detection, register-transfer level, single-event upsets, hardware redundancy
9	Namrata Shekhar, Sudhakar Kalla, Florian Enescu	Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
9	Sivaram Gopalakrishnan, Priyank Kalla	Optimization of polynomial datapaths using finite ring algebra.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	arithmetic datapaths, finite ring algebra, modulo arithmetic, polynomial datapaths, High-level synthesis
9	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi	Low test application time resource binding for behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	CDFG, high-level synthesis, Testability, test synthesis
9	Jeffrey M. Arnold	The Architecture and Development Flow of the S5 Software Configurable Processor.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	software configurable processor, reconfigurable architectures, embedded computing, instruction set extension
9	Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu	Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	robust hardware, back-end design automation, power-constant architectures, DFY, side-channel attacks, DFM, mitigation
9	Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest	Semi Custom Design: A Case Study on SIMD Shufflers.	PATMOS	2007	DBLP DOI BibTeX RDF
9	María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida	Area optimization of multi-cycle operators in high-level synthesis.	DATE	2007	DBLP DOI BibTeX RDF
9	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal	Very wide register: an asymmetric register file organization for low power embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
9	Fabio Campi, Antonio Deledda, Matteo Pizzotti, Luca Ciccarelli, Pier Luigi Rolandi, Claudio Mucci, Andrea Lodi 0002, Arseni Vitkovski, Luca Vanzolini	A dynamically adaptive DSP for heterogeneous reconfigurable platforms.	DATE	2007	DBLP DOI BibTeX RDF
9	Amir Hormati, Nathan Clark, Scott A. Mahlke	Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping.	CGO	2007	DBLP DOI BibTeX RDF
9	Kiran Puttaswamy, Gabriel H. Loh	Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors.	HPCA	2007	DBLP DOI BibTeX RDF
9	Andrew Lines	The Vortex: A Superscalar Asynchronous Processor.	ASYNC	2007	DBLP DOI BibTeX RDF
9	Shin-Yi Lin, Chih-Tsun Huang	A High-Throughput Low-Power AES Cipher for Network Applications.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, low-power AES cipher, two-stage pipeline, CCM mode, design-for-test circuitry, 4.27 Gbits/s, 333 MHz, 40.9 mW, CMOS technology, network applications
9	Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, Jon Altuna	Joint Source-Channel Decoding ASIP Architecture for Sensor Networks.	ICESS	2007	DBLP DOI BibTeX RDF	DSC, Sensor Networks, VLIW, ASIP, Turbo Codes, Joint Source-Channel Coding, Factor Graphs
9	Kristopher D. Peterson, Justin L. Tripp	Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA Compiler.	FPL	2007	DBLP DOI BibTeX RDF
9	Jérémie Detrey, Florent de Dinechin	Floating-Point Trigonometric Functions for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
9	Evangelos Koukis, Nectarios Koziris	Efficient Block Device Sharing over Myrinet with Memory Bypass.	IPDPS	2007	DBLP DOI BibTeX RDF
9	Xiaojun Wang, Miriam Leeser	K-means Clustering for Multispectral Images Using Floating-Point Divide.	FCCM	2007	DBLP DOI BibTeX RDF
9	Byeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seungjin Lee 0001, Hoi-Jun Yoo	A low-power handheld GPU using logarithmic arithmetic and triple DVFS power domains.	Graphics Hardware	2007	DBLP DOI BibTeX RDF	handheld systems, low-power, GPU, hardware architecture, 3D computer graphics
9	Joseph J. Sharkey, Dmitry V. Ponomarev	An L2-miss-driven early register deallocation for SMT processors.	ICS	2007	DBLP DOI BibTeX RDF	register files, simultaneous multithreading
9	Shorin Kyo, Takuya Koga, Hanno Lieske, Shouhei Nomoto, Shin'ichiro Okazaki	A low-cost mixed-mode parallel processor architecture for embedded systems.	ICS	2007	DBLP DOI BibTeX RDF	embedded systems, parallel architectures, SIMD, MIMD, multimedia processing, tile architectures, mixed-mode
9	Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen	Latency-Tolerant Virtual Cluster Architecture for VLIW DSP.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Klaus Gaedke, Malte Borsum, Marco Georgi, Andreas Kluger, Jean-Pierre Le Glanic, Pascal Bernard	Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi	MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Henrik Svensson, Thomas Lenart, Viktor Öwall	Accelerating Vector Operations by Utilizing Reconfigurable Coprocessor Architectures.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu	Rapid C to FPGA Prototyping with Multithreaded Emulation Engine.	ISCAS	2007	DBLP DOI BibTeX RDF
9	K. T. Gardiner, Alexandre Yakovlev, Alexandre V. Bystrov	A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits.	IOLTS	2007	DBLP DOI BibTeX RDF
9	Mustafa Parlak, Ilker Hamzaoglu	A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm.	AHS	2007	DBLP DOI BibTeX RDF
9	Ben Cope, Peter Y. K. Cheung, Wayne Luk	Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective.	ASAP	2007	DBLP DOI BibTeX RDF
9	Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii	Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	function calls, integer programming problem, behavioral synthesis
9	Zhenyu Liu 0001, Yiqing Huang 0002, Yang Song 0002, Satoshi Goto, Takeshi Ikenaga	Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	variable block size motion estimation, VLSI, H.264
9	Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingrid Verbauwhede	Side-channel resistant system-level design flow for public-key cryptography.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	elliptic curve cryptography, side-channel attack, system-level modeling
9	Elias Mizan, Tileli Amimeur, Margarida F. Jacome	Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
9	Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai	AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs.	VLSI Design	2007	DBLP DOI BibTeX RDF
9	Saraju P. Mohanty, Elias Kougianos	Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis.	VLSI Design	2007	DBLP DOI BibTeX RDF
9	Thaísa Leal da Silva, Cláudio Machado Diniz, João Alberto Vortmann, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi	A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder.	PSIVT	2007	DBLP DOI BibTeX RDF	8x8 2-D DCT, H.264/AVC standard, Video compression, Architectural Design
9	Lovleen Bhatia, Jayesh Gaur, Praveen Tiwari, Raj S. Mitra, Sunil H. Matange	Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation.	DAC	2007	DBLP DOI BibTeX RDF
9	Yuming Zhu, L. Li, Chaitali Chakrabarti	Study of energy and performance of space-time decoding systems in concatenation with turbo decoding.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
9	Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija	Energy optimization of pipelined digital systems using circuit sizing and supply scaling.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
9	Huai-Yi Hsu, Jih-Chiang Yeo, An-Yeu Wu	Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
9	Thomas Lenart, Viktor Öwall	Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
9	Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng	Simulation-Based Functional Test Generation for Embedded Processors.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Simulation, learning, test generation, functional test
9	Akshay Sharma, Carl Ebeling, Scott Hauck	PipeRoute: a pipelining-aware router for reconfigurable architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	Soheil Ghiasi, Elaheh Bozorgzadeh, Po-Kuan Huang, Roozbeh Jafari, Majid Sarrafzadeh	A Unified Theory of Timing Budget Management.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	Ying Yi, Roger F. Woods	Hierarchical synthesis of complex DSP functions using IRIS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	Bin Wu, Jianwen Zhu, Farid N. Najm	Dynamic-range estimation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	Olivier Rochecouste, Gilles Pokam, André Seznec	A case for a complexity-effective, width-partitioned microarchitecture.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	Power analysis
9	Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Compiler-directed thermal management for VLIW functional units.	LCTES	2006	DBLP DOI BibTeX RDF	VLIW, thermal, IPC
9	Jie S. Hu, Shuai Wang 0006, Sotirios G. Ziavras	In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability.	DSN	2006	DBLP DOI BibTeX RDF
9	Ju-Ho Sohn, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo	Design and test of fixed-point multimedia co-processor for mobile applications.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
9	Namrata Shekhar, Priyank Kalla, Florian Enescu	Equivalence verification of arithmetic datapaths with multiple word-length operands.	DATE	2006	DBLP DOI BibTeX RDF
9	Tingting Sha, Milo M. K. Martin, Amir Roth	NoSQ: Store-Load Communication without a Store Queue.	MICRO	2006	DBLP DOI BibTeX RDF
9	Michael L. Chu, Scott A. Mahlke	Compiler-directed Data Partitioning for Multicluster Processors.	CGO	2006	DBLP DOI BibTeX RDF
9	Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau	Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems.	SiPS	2006	DBLP DOI BibTeX RDF
9	Christos A. Papachristou, J. Weaver, R. Vijayakumar, Francis G. Wolff	A Dynamic Reconfigurable Fabric for Platform SoCs.	FPL	2006	DBLP DOI BibTeX RDF
9	Andrea Lodi 0002, Claudio Mucci, Massimo Bocchi, Andrea Cappelli, Mario de Dominicis, Luca Ciccarelli	A Multi-Context Pipelined Array for Embedded Systems.	FPL	2006	DBLP DOI BibTeX RDF
9	Reiner W. Hartenstein	RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances.	IPDPS	2006	DBLP DOI BibTeX RDF
9	Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura, Hideharu Amano	Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor.	IPDPS	2006	DBLP DOI BibTeX RDF
9	Xiaojun Wang, Sherman Braganza, Miriam Leeser	Advanced Components in the Variable Precision Floating-Point Library.	FCCM	2006	DBLP DOI BibTeX RDF
9	Rodrigo Agís, Javier Díaz 0001, Eduardo Ros 0001, Richard R. Carrillo, Eva M. Ortigosa	Event-Driven Simulation Engine for Spiking Neural Networks on a Chip.	ARC	2006	DBLP DOI BibTeX RDF
9	Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk	A Flexible Multi-port Caching Scheme for Reconfigurable Platforms.	ARC	2006	DBLP DOI BibTeX RDF
9	Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems.	ARC	2006	DBLP DOI BibTeX RDF	RSA, Elliptic Curve Cryptography (ECC), Public-Key Cryptography (PKC), Reconfigurable architecture, FPGA implementation
9	T. S. Ganesh, Viswanathan Subramanian, Arun K. Somani	SEU Mitigation Techniques for Microprocessor Control Logic.	EDCC	2006	DBLP DOI BibTeX RDF
9	Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng 0012, Hillel Miller, Magdy S. Abadir	Extracting a Simplified View of Design Functionality Based on Vector Simulation.	Haifa Verification Conference	2006	DBLP DOI BibTeX RDF
9	Yunan Xiang, R. Pettibon, Martin Margala	A versatile computation module for adaptable multimedia processors.	ISCAS	2006	DBLP DOI BibTeX RDF
9	André Borin Soares, Altamiro Amadeu Susin, Leticia V. Guimaraes	Automatic generation of neural networks for image processing.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede	A fast dual-field modular arithmetic logic unit and its hardware implementation.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Jeffrey M. Arnold	Software Configurable Processors.	ASAP	2006	DBLP DOI BibTeX RDF
9	Wann-Yun Shieh, Hsin-Dar Chen	Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB.	EUC Workshops	2006	DBLP DOI BibTeX RDF	register leakage power, high-end embedded processor, dynamic voltage scaling (DVS), reorder buffer
9	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective.	ISQED	2006	DBLP DOI BibTeX RDF
9	Vyas Krishnan, Srinivas Katkoori	Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation.	ISQED	2006	DBLP DOI BibTeX RDF
9	Bruce F. Cockburn, Keith Boyle	Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells.	CCECE	2006	DBLP DOI BibTeX RDF
9	Joseph J. Sharkey, Dmitry Ponomarev 0001	Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch.	ICPP	2006	DBLP DOI BibTeX RDF
9	Brent Welch, Marc Unangst	S13 - Cluster storage and file system technologies.	SC	2006	DBLP DOI BibTeX RDF
9	Saraju P. Mohanty, Elias Kougianos	Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
9	Harald Widiger, Stephan Kubisch, Thomas Bahls, Dirk Timmermann	An Integrated Hardware Solution for MAC Address Translation, MPLS, and Traffic Management in Access Networks.	LCN	2006	DBLP DOI BibTeX RDF
9	Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, Han-Chiang Chen	Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator.	LCN	2006	DBLP DOI BibTeX RDF
9	Jen-Wei Yang, Po-Tsang Huang, Wei Hwang	On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Jung-Lin Yang, Hsu-Ching Tien, Chia-Ming Hsu, Sung-Min Lin	High-Level Synthesis for Self-Timed Systems.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Jordi Cortadella, Michael Kishinevsky, Bill Grundmann	Synthesis of synchronous elastic architectures.	DAC	2006	DBLP DOI BibTeX RDF	protocols, synthesis, latency-tolerance, latency-insensitive design
9	Ruby B. Lee, Xiao Yang 0001, Zhijie Shi	Single-Cycle Bit Permutations with MOMR Execution.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	bit permutations, cryptographic acceleration, multi-word operation, datarich execution, MOMR, high performance secure computing, security, cryptography, permutation, processor, instruction set architecture, ISA
9	Maria Athanasaki, Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris, Panayotis Tsanakas	Hyperplane Grouping and Pipelined Schedules: How to Execute Tiled Loops Fast on Clusters of SMPs.	J. Supercomput.	2005	DBLP DOI BibTeX RDF	tile grouping, loop tiling, hyperplanes, pipelined schedules, supernodes
9	Koushik Maharatna, Swapna Banerjee, Eckhard Grass, Milos Krstic, Alfonso Troya	Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
9	Xun Liu, Marios C. Papaefthymiou	HyPE: hybrid power estimation for IP-based systems-on-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
9	Lin Zhong 0001, Niraj K. Jha	Interconnect-aware low-power high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
9	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Built-in sequential fault self-testing of array multipliers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
9	Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark D. Aagaard, Clark W. Barrett, Don Syme	An industrially effective environment for formal hardware verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF