Search results for "microprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Y. Abulafia, Avner Kornfeld	Estimation of FMAX and ISB in microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
14	Prabhat Mishra 0001, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir	A methodology for validation of microprocessors using symbolic simulation.	Int. J. Embed. Syst.	2005	DBLP DOI BibTeX RDF
14	Rebecca M. Gott, Jason Baumgartner, Paul Roessler, S. I. Joe	Functional formal verification on designs of pSeries microprocessors and communication subsystems.	IBM J. Res. Dev.	2005	DBLP DOI BibTeX RDF
14	Nathan T. Slingerland, Alan Jay Smith	Multimedia extensions for general purpose microprocessors: a survey.	Microprocess. Microsystems	2005	DBLP DOI BibTeX RDF
14	Kunle Olukotun, Lance Hammond	The future of microprocessors.	ACM Queue	2005	DBLP DOI BibTeX RDF
14	Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt	Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors.	DSN	2005	DBLP DOI BibTeX RDF
14	Steven A. Guccione	Microprocessors: The New LUT.	ERSA	2005	DBLP BibTeX RDF
14	Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura	Dynamic Instruction Cascading on GALS Microprocessors.	PATMOS	2005	DBLP DOI BibTeX RDF
14	Jinwen Xi, Peixin Zhong	Fast Energy Estimation of Multi-processor System-on-Chip with Energy Macro-Models for Embedded Microprocessors.	MSV	2005	DBLP BibTeX RDF
14	Fred A. Bower, Daniel J. Sorin, Sule Ozev	A Mechanism for Online Diagnosis of Hard Faults in Microprocessors.	MICRO	2005	DBLP DOI BibTeX RDF
14	Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda	A perturbation-aware noise convergence methodology for high frequency microprocessors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
14	Himyanshu Anand, Jayanta Bhadra, Alper Sen 0001, Magdy S. Abadir, Kenneth G. Davis	Establishing latch correspondence for embedded circuits of PowerPC microprocessors.	HLDVT	2005	DBLP DOI BibTeX RDF
14	Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil	Compressing Functional Tests for Microprocessors.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
14	Hector Arteaga, Hussain Al-Asaad	On Increasing the Observability of Modern Microprocessors.	CDES	2005	DBLP BibTeX RDF
14	Carlos García 0001, Christian Tenllado, Luis Piñuel, Manuel Prieto 0001	JPEG2000 Optimization in General Purpose Microprocessors.	PARCO	2005	DBLP BibTeX RDF
14	Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson 0001, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi	Electrical and optical on-chip interconnects in scaled microprocessors.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
14	Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors.	DFT	2005	DBLP DOI BibTeX RDF
14	Ruby B. Lee, Peter C. S. Kwan, John Patrick McGregor, Jeffrey S. Dwoskin, Zhenghong Wang	Architecture for Protecting Critical Secrets in Microprocessors.	ISCA	2005	DBLP DOI BibTeX RDF
14	Lieven Eeckhout, Koen De Bosschere	Efficient architectural design of high performance microprocessors.	Adv. Comput.	2004	DBLP DOI BibTeX RDF
14	Nikolaos Kavvadias, Periklis Neofotistos, Spiridon Nikolaidis 0001, C. A. Kosmatopoulos, Theodore Laopoulos	Measurements analysis of the software-related power consumption in microprocessors.	IEEE Trans. Instrum. Meas.	2004	DBLP DOI BibTeX RDF
14	Thomas Hauser, Timothy Mattox, Raymond P. LeBeau, Henry G. Dietz, P. George Huang	Code Optimizations for Complex Microprocessors Applied to CFD Software.	SIAM J. Sci. Comput.	2004	DBLP DOI BibTeX RDF
14	Victor V. Zyuban, David M. Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma	Integrated Analysis of Power and Performance for Pipelined Microprocessors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
14	Howard Falk	Decisive Aspects in the Evolution of Microprocessors.	Proc. IEEE	2004	DBLP DOI BibTeX RDF
14	Dezsö Sima	Decisive aspects in the evolution of microprocessors.	Proc. IEEE	2004	DBLP DOI BibTeX RDF
14	Tao Jiang, Eric Pettus, Daksh Lehther	A mixed-mode extraction flow for high performance microprocessors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
14	Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek	Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration.	FPL	2004	DBLP DOI BibTeX RDF
14	Brian F. Veale, John K. Antonio, Monte P. Tull	Code Re-ordering for a Class of Reconfigurable Microprocessors.	FPL	2004	DBLP DOI BibTeX RDF
14	Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke, Peter M. Kogge	Cache implications of aggressively pipelined high performance microprocessors.	ISPASS	2004	DBLP DOI BibTeX RDF
14	Fernando Cortez Sica, Claudionor José Nunes Coelho Jr., José Augusto Miranda Nacif, Harry Foster, Antônio Otávio Fernandes	Exception handling in microprocessors using assertion libraries.	SBCCI	2004	DBLP DOI BibTeX RDF	exceptions handling, assertions
14	Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge	Microarchitectural power modeling techniques for deep sub-micron microprocessors.	ISLPED	2004	DBLP DOI BibTeX RDF	power modeling, deep sub-micron
14	Bryan Black, Donald Nelson, Clair Webb, Nick Samra	3D Processing Technology and Its Impact on iA32 Microprocessors.	ICCD	2004	DBLP DOI BibTeX RDF
14	Miroslav N. Velev	A new generation of ISCAS benchmarks from formal verification of high-level microprocessors.	ISCAS (5)	2004	DBLP BibTeX RDF
14	Shubhendu S. Mukherjee, Joel S. Emer, Tryggve Fossum, Steven K. Reinhardt	Cache Scrubbing in Microprocessors: Myth or Necessity?	PRDC	2004	DBLP DOI BibTeX RDF
14	Siva G. Narendra, Vasantha Erraguntla, James W. Tschanz, Nitin Borkar	Design Challenges in Sub-100nm High Performance Microprocessors.	VLSI Design	2004	DBLP DOI BibTeX RDF
14	Raman Srinivas	Building Giga-Transistor [Enterprise] Microprocessors.	VLSI Design	2004	DBLP DOI BibTeX RDF
14	Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers	The Case for Lifetime Reliability-Aware Microprocessors.	ISCA	2004	DBLP DOI BibTeX RDF
14	Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark	Formal online methods for voltage/frequency control in multiple clock domain microprocessors.	ASPLOS	2004	DBLP DOI BibTeX RDF	MCD processors, formal methods, dynamic voltage/frequency scaling
14	Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De	Design optimizations for microprocessors at low temperature.	DAC	2004	DBLP DOI BibTeX RDF	electrothermal modeling, low temperature, refrigeration, power, microprocessor, CMOS, frequency, cooling
14	James W. Tschanz, Siva G. Narendra, Yibin Ye, Bradley A. Bloechel, Shekhar Borkar, Vivek De	Dynamic sleep transistor and body bias for active leakage power control of microprocessors.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
14	James W. Tschanz, Siva G. Narendra, Raj Nair, Vivek De	Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
14	Siva G. Narendra, Ali Keshavarzi, Bradley A. Bloechel, Shekhar Borkar, Vivek De	Forward body bias for microprocessors in 130-nm technology generation and beyond.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
14	David M. Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, Philip G. Emma, Michael G. Rosenfield	New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors.	IBM J. Res. Dev.	2003	DBLP DOI BibTeX RDF
14	Gustavo Liñán, Servando Espejo-Meana, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez	An Improved Elementary Processing Unit For High-Density CNN-Based Mixed-Signal Microprocessors For Vision.	J. Circuits Syst. Comput.	2003	DBLP DOI BibTeX RDF
14	S. Belhardj, S. Mimouni, Abdelkader Saïdane, M. Benzohra	Using microchannels to cool microprocessors: a transmission-line-matrix study.	Microelectron. J.	2003	DBLP DOI BibTeX RDF
14	Alain J. Martin, Mika Nyström, Catherine G. Wong	Three Generations of Asynchronous Microprocessors.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
14	Alex Orailoglu, Alexander V. Veidenbaum	Guest Editors' Introduction: Application-Specific Microprocessors.	IEEE Des. Test Comput.	2003	DBLP BibTeX RDF
14	Miroslav N. Velev, Randal E. Bryant	Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors.	J. Symb. Comput.	2003	DBLP DOI BibTeX RDF
14	Prabhat Mishra 0001, Nikil D. Dutt	A Methodology for Validation of Microprocessors using Equivalence Checking.	MTV	2003	DBLP DOI BibTeX RDF
14	Yu Bai 0001, R. Iris Bahar	A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors.	ISVLSI	2003	DBLP DOI BibTeX RDF
14	Joydeep Ray, James C. Hoe	High-level modeling and FPGA prototyping of microprocessors.	FPGA	2003	DBLP DOI BibTeX RDF	operation-centric, FPGA, evaluation, prototyping, microprocessor, microarchitecture
14	Fulvio Corno, Giovanni Squillero, Matteo Sonza Reorda	Code generation for functional validation of pipelined microprocessors.	ETW	2003	DBLP DOI BibTeX RDF
14	Toshihiro Hattori	Design methodology of low-power microprocessors.	ASP-DAC	2003	DBLP DOI BibTeX RDF
14	David G. Malham	Cutting the cord - In-circuit programmable microprocessors and RF data links free the performer from cables.	ICMC	2003	DBLP BibTeX RDF
14	Mauro Olivieri, Marco Raspa	Power Efficiency of Application-Dependent Self-Configuring Pipeline Depth in DSP Microprocessors.	IPDPS	2003	DBLP DOI BibTeX RDF
14	Feng-Jiann Shiao, Jong-Jiann Shieh	An Issue Logic for Superscalar Microprocessors.	CAINE	2003	DBLP BibTeX RDF
14	Shyh-Ming Huang, Ing-Jer Huang, Chung-Fu Kao	Reconfigurable real-time address trace compressor for embedded microprocessors.	FPT	2003	DBLP DOI BibTeX RDF
14	Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos	Virtual-scan: a novel approach for software-based self-testing of microprocessors.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
14	John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald 0001, Russell P. Kraft	3D direct vertical interconnect microprocessors test vehicle.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	SiGe HBT, direct vertical integration, finite state machine, interconnect, microprocessor, adder, register file, 3D integration, current mode logic
14	Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi	Thermal Management of High Performance Microprocessors.	DFT	2003	DBLP DOI BibTeX RDF
14		A VLSI System Perspective for Microprocessors Beyond 90nm.	ISQED	2003	DBLP DOI BibTeX RDF
14	Thomas Schubert	High level formal verification of next-generation microprocessors.	DAC	2003	DBLP DOI BibTeX RDF	formal property verification
14	Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee	Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI [microprocessors].	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
14	Daniel Etiemble	Computer arithmetic and hardware: "off the shelf" microprocessors versus "custom hardware".	Theor. Comput. Sci.	2002	DBLP DOI BibTeX RDF
14	Gang Qu 0001, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak	Code Coverage-Based Power Estimation Techniques for Microprocessors.	J. Circuits Syst. Comput.	2002	DBLP DOI BibTeX RDF
14	Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching-Nan Juan, Tai-An Lu	A Retargetable Embedded In-Circuit Emulation Module for Microprocessors.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
14	Tamás Roska, Ángel Rodríguez-Vázquez	Toward visual microprocessors.	Proc. IEEE	2002	DBLP DOI BibTeX RDF
14	Stephen B. Furber	Validating the AMULET Microprocessors.	Comput. J.	2002	DBLP DOI BibTeX RDF
14	Nobuo Hataoka, Hiroaki Kokubo, Yasunari Obuchi, Akio Amano	Compact and robust speech recognition for embedded use on microprocessors.	IEEE Workshop on Multimedia Signal Processing	2002	DBLP DOI BibTeX RDF
14	Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose	AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors.	DATE	2002	DBLP DOI BibTeX RDF
14	Miroslav N. Velev	Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer.	DATE	2002	DBLP DOI BibTeX RDF
14	Prabhat Mishra 0001, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama	Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units.	DATE	2002	DBLP DOI BibTeX RDF
14	José F. Martínez, Jose Renau, Michael C. Huang 0001, Milos Prvulovic, Josep Torrellas	Cherry: checkpointed early resource recycling in out-of-order microprocessors.	MICRO	2002	DBLP DOI BibTeX RDF
14	Bob Bentley	High level validation of next-generation microprocessors.	HLDVT	2002	DBLP DOI BibTeX RDF
14	Veerle Desmet, Bart Goeman, Koenraad De Bosschere	Independent Hashing as Confidence Mechanism for Value Predictors in Microprocessors.	Euro-Par	2002	DBLP DOI BibTeX RDF
14	Steven M. Martin, Krisztián Flautner, Trevor N. Mudge, David T. Blaauw	Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads.	ICCAD	2002	DBLP DOI BibTeX RDF
14	Chris H. Kim, Kaushik Roy 0001	Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors.	ISLPED	2002	DBLP DOI BibTeX RDF
14	Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev 0001	A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors.	ICCD	2002	DBLP DOI BibTeX RDF
14	Edith Kussener, Hervé Barthélemy, Alexandre Malherbe, Andreas Kaiser	Versatile macromodel for the power supply of submicronic CMOS microprocessors based on voltage down DC-DC converter.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
14	Mike Mayberry, John Johnson, Navid Shahriari, Mike Tripp	Realizing the Benefits of Structural Test for Intel Microprocessors.	ITC	2002	DBLP DOI BibTeX RDF
14	Grady Giles	Is Scan (Alone) Sufficient to Test Today?s Microprocessors? Not Quite, but We Can?t Get the Job Done Without It.	ITC	2002	DBLP DOI BibTeX RDF
14	Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar	Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.	DAC	2002	DBLP DOI BibTeX RDF	Dual-Vt design, multiple threshold, optimization, sizing
14	Thomas Lundqvist	A WCET Analysis Method for Pipelined Microprocessors with Cache Memories.		2002	RDF
14	Phillip J. Restle, Timothy G. McNamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. McCredie	A clock distribution network for microprocessors.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
14	R.-Ming Shiu, Hui-Yue Hwang, Jean Jyh-Jiun Shann	Aggressive Schduling for Memory Accesses of CISC Superscalar Microprocessors.	J. Inf. Sci. Eng.	2001	DBLP BibTeX RDF
14	Marius Evers, Tse-Yu Yeh	Understanding branches and designing branch predictors for high-performance microprocessors.	Proc. IEEE	2001	DBLP DOI BibTeX RDF
14	Daniel Kröning	Formal verification of pipelined microprocessors.		2001	RDF
14	Joel B. Nickel, Arun K. Somani	REESE: A Method of Soft Error Detection in Microprocessors.	DSN	2001	DBLP DOI BibTeX RDF
14	Gurindar S. Sohi	Microprocessors - 10 Years Back, 10 Years Ahead.	Informatics	2001	DBLP DOI BibTeX RDF
14	Sinan Kaptanoglu, John East, Tim Garverick, Scott Hauck, Tavana Tavana, Steven Trimberger, Ronnie Vasishta	Is marriage in the cards for programmable logic, microprocessors and ASICs?	FPGA	2001	DBLP DOI BibTeX RDF
14	Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham	Full chip false timing path identification: applications to the PowerPCTM microprocessors.	DATE	2001	DBLP DOI BibTeX RDF
14	Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti	Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing.	MICRO	2001	DBLP DOI BibTeX RDF
14	Eric Rotenberg	Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems.	MICRO	2001	DBLP DOI BibTeX RDF
14	Phillip J. Restle, Albert E. Ruehli, Steven G. Walker	Multi-GHz interconnect effects in microprocessors.	ISPD	2001	DBLP DOI BibTeX RDF	full-wave analysis, simulation, interconnect, inductance, extraction, clock distribution, circuit-tuning
14	James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De	Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.	ISLPED	2001	DBLP DOI BibTeX RDF	dual edge, low power, flip-flops, clocking, triggered, latches
14	Russ Joseph, Margaret Martonosi	Run-time power estimation in high performance microprocessors.	ISLPED	2001	DBLP DOI BibTeX RDF
14	Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar 0002	Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors.	ICCD	2001	DBLP DOI BibTeX RDF
14	Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya B. Gokhale	Mutable Functional Units and Their Applications on Microprocessors.	ICCD	2001	DBLP DOI BibTeX RDF
14	Alessandro De Gloria, Mauro Olivieri	An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
14	Cristiana Bolchini, Fabio Salice, Donatella Sciuto	Designing Reliable Embedded Systems Based on 32 Bit Microprocessors.	IOLTW	2001	DBLP DOI BibTeX RDF
14	Daniel Kröning	Formal verification of pipelined microprocessors.	Ausgezeichnete Informatikdissertationen	2001	DBLP BibTeX RDF