|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 1160 occurrences of 532 keywords
|
|
|
Results
Found 1093 publication records. Showing 1093 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
15 | Peter Pfahler, Georg Piepenbrock |
A Comparison of Modulo Scheduling Techniques for Software Pipelining. |
CC |
1996 |
DBLP DOI BibTeX RDF |
Instruction Level Parallelism, Software Pipelining, VLIW, Superscalar Processors |
15 | Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park |
Eliminating Conditional Branches for Enhancing Instruction Level Parallelism in VLIW Compiler. |
ISPAN |
1996 |
DBLP DOI BibTeX RDF |
Compiler, Instruction Level Parallelism, VLIW, Superscalar, Conditional Branches |
15 | Wade Walker, Harvey G. Cragon |
Interrupt Processing in Concurrent Processors. |
Computer |
1995 |
DBLP DOI BibTeX RDF |
Interrupt processing, imprecise interrupts, concurrent processors, checkpointing, taxonomy, superscalar processors, pipelined processors, out- of-order execution, out-of-order issue, precise interrupts |
15 | Pohua P. Chang, Nancy J. Warter, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu |
Three Architecutral Models for Compiler-Controlled Speculative Execution. |
IEEE Trans. Computers |
1995 |
DBLP DOI BibTeX RDF |
static code scheduling, superpipelining, exception handling, speculative execution, superscalar, Conditional branches, superblock |
15 | Soo-Mook Moon, Scott D. Carson |
Generalized Multiway Branch Unit for VLIW Microprocessors. |
IEEE Trans. Parallel Distributed Syst. |
1995 |
DBLP DOI BibTeX RDF |
generalized multiway branching, VLIW microprocessor, condition tree, mirror normalization, VLIW compiler, Instruction-level parallelism, superscalar microprocessor |
15 | Eric Hao, Po-Yung Chang, Yale N. Patt |
The effect of speculatively updating branch history on branch prediction accuracy, revisited. |
MICRO |
1994 |
DBLP DOI BibTeX RDF |
two-level adaptive branch prediction, speculative execution, superscalar processors, out-of-order execution, dynamic branch prediction |
15 | Michael Upton, Thomas Huff, Trevor N. Mudge, Richard B. Brown |
Resource Allocation in a High Clock Rate Microprocessor. |
ASPLOS |
1994 |
DBLP DOI BibTeX RDF |
floating point latencies, nonblocking cache, resource allocation, pipelining, prefetching, superscalar, decoupled architecture |
15 | William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu |
The Effect of Code Expanding Optimizations on Instruction Cache Design. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
code expanding optimizations, instruction placement, function inline expansion, superscalar optimizations, small caches, medium caches, load forwarding, large caches, C compiler, code expansion, optimisation, cache memory, memory architecture, buffer storage, instruction cache, code optimization, cache design, miss ratio |
15 | Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, John C. Gyllenhaal, Wen-mei W. Hwu |
Speculative execution exception recovery using write-back suppression. |
MICRO |
1993 |
DBLP DOI BibTeX RDF |
exception detection, exception recovery, scheduling, VLIW, speculative execution, superscalar |
15 | Richard E. Hank, Scott A. Mahlke, Roger A. Bringmann, John C. Gyllenhaal, Wen-mei W. Hwu |
Superblock formation using static program analysis. |
MICRO |
1993 |
DBLP DOI BibTeX RDF |
optimization, VLIW, superscalar, static program analysis, superblock, code scheduling |
15 | Mark Smotherman, Shuchi Chawla 0002, Stan Cox, Brian A. Malloy |
Instruction scheduling for the Motorola 88110. |
MICRO |
1993 |
DBLP DOI BibTeX RDF |
MC88110, cache alignment, instruction scheduling, superscalar processors |
15 | Norman P. Jouppi |
The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance. |
IEEE Trans. Computers |
1989 |
DBLP DOI BibTeX RDF |
machine performance, first-order estimate, machine parallelism, instruction-level, machine pipelines, MultiTitan, superscalar machine, performance evaluation, parallel architectures, pipeline processing, CRAY-1 |
8 | Arquimedes Canedo, Takeo Yoshizawa, Hideaki Komatsu |
Automatic parallelization of simulink applications. |
CGO |
2010 |
DBLP DOI BibTeX RDF |
coarse grain dataflow, equation-level parallelism, compilers, multi-core, automatic parallelization, simulink, strands |
8 | Vladimir Marjanovic, Jesús Labarta, Eduard Ayguadé, Mateo Valero |
Overlapping communication and computation by using a hybrid MPI/SMPSs approach. |
ICS |
2010 |
DBLP DOI BibTeX RDF |
hybrid MPI/SMPSs, MPI, parallel programming model, LINPACK |
8 | Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski |
Out-of-order issue logic using sorting networks. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
out-of-order processing, ILP, micro-architecture, issue queue, high speed circuits |
8 | Vladimir Marjanovic, Jesús Labarta, Eduard Ayguadé, Mateo Valero |
Effective communication and computation overlap with hybrid MPI/SMPSs. |
PPoPP |
2010 |
DBLP DOI BibTeX RDF |
hybrid mpi/smpss, mpi, parallel programming model, linpack |
8 | Hans Vandierendonck, André Seznec |
Fetch Gating Control through Speculative Instruction Window Weighting. |
Trans. High Perform. Embed. Archit. Compil. |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Aneesh Aggarwal |
Complexity Effective Bypass Networks. |
Trans. High Perform. Embed. Archit. Compil. |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Christine Rochange, Pascal Sainrat |
A Context-Parameterized Model for Static Analysis of Execution Times. |
Trans. High Perform. Embed. Archit. Compil. |
2009 |
DBLP DOI BibTeX RDF |
timing analysis, Worst-Case Execution Time |
8 | Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero |
DIA: A Complexity-Effective Decoding Architecture. |
IEEE Trans. Computers |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Soontae Kim |
Reducing Area Overhead for Error-Protecting Large L2/L3 Caches. |
IEEE Trans. Computers |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Timothy M. Jones 0001, Michael F. P. O'Boyle, Jaume Abella 0001, Antonio González 0001, Oguz Ergin |
Exploring the limits of early register release: Exploiting compiler analysis. |
ACM Trans. Archit. Code Optim. |
2009 |
DBLP DOI BibTeX RDF |
compiler, energy efficiency, Low-power design, microarchitecture, register file |
8 | Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil |
Synergistic execution of stream programs on multicores with accelerators. |
LCTES |
2009 |
DBLP DOI BibTeX RDF |
CUDAa, partitioning, software pipelining, stream programming, GPU programming |
8 | Pieter Bellens, Josep M. Pérez, Rosa M. Badia, Jesús Labarta |
Exploiting Locality on the Cell/B.E. through Bypassing. |
SAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. Holloway, Gu-Yeon Wei, Michael D. Smith 0001, David M. Brooks |
Voltage emergency prediction: Using signatures to reduce operating margins. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Raül Sirvent, Rosa M. Badia, Jesús Labarta |
Graph-Based Task Replication for Workflow Applications. |
HPCC |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Liqiang He, Cha Narisu |
A Fast Scheme to Investigate Thermal-Aware Scheduling Policy for Multicore Processors. |
APPT |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Hui Zeng, Ju-Young Jung, Kanad Ghose, Dmitry Ponomarev 0001 |
Energy-efficient renaming with register versioning. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
microprocessor, register renaming |
8 | Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer |
IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor. |
HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Suriya Subramanian, Kathryn S. McKinley |
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic. |
HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Ian Horswill |
Very fast action selection for parameterized behaviors. |
FDG |
2009 |
DBLP DOI BibTeX RDF |
reactive planning, agent architectures, behavior-based control |
8 | Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Kanad Ghose |
Selective Writeback: Reducing Register File Pressure and Energy Consumption. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Mahmoud A. Bennaser, Yao Guo 0001, Csaba Andras Moritz |
Data Memory Subsystem Resilient to Process Variations. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
8 | John N. Coleman, Christopher I. Softley, Jiri Kadlec, Rudolf Matousek, Milan Tichý, Zdenek Pohl, Antonin Hermanek, Nico F. Benschop |
The European Logarithmic Microprocesor. |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
General, High-Speed Arithmetic |
8 | Zeshan Chishti, T. N. Vijaykumar |
Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies. |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
Power Management, Performance of Systems, Multithreaded processors |
8 | Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong |
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design. |
ACM J. Emerg. Technol. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
3D packing, microarchitecture, 3D integration, thermal |
8 | Mladen Berekovic, Tim Niggemeier |
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
clustering, distributed computing, DSP, MPEG-4, multi-threading, processor architecture, SMT |
8 | Haitham Akkary, Komal Jothi, Renjith Retnamma, Satyanarayana Nekkalapu, Doug Hall, Shahrokh Shahidzadeh |
On the potential of latency tolerant execution in speculative multithreading. |
IFMT |
2008 |
DBLP DOI BibTeX RDF |
latency-tolerant architectures, chip multiprocessors, speculative multithreading, many-core processors |
8 | José Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo |
Modelling Asynchronous Systems using Probability Distribution Functions. |
PDP |
2008 |
DBLP DOI BibTeX RDF |
modelling, asynchronous, microarchitecture |
8 | Alejandro Duran, Josep M. Pérez, Eduard Ayguadé, Rosa M. Badia, Jesús Labarta |
Extending the OpenMP Tasking Model to Allow Dependent Tasks. |
IWOMP |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Xi E. Chen, Tor M. Aamodt |
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Seyed Masoud Sadjadi, Liana Fong, Rosa M. Badia, Javier Figueroa, Javier Delgado, Xabriel J. Collazo-Mojica, Khalid Saleem, Raju Rangaswami, Shu Shimizu, Hector A. Duran-Limon, Pat Welsh, Sandeep Pattnaik, Anthony Praino, David Villegas, Selim Kalayci, Gargi Dasgupta, Onyeka Ezenwoye, Juan Carlos Martínez, Ivan Rodero, Shuyi Chen, Javier Muñoz, Diego R. López, Julita Corbalán, Hugh Willoughby, Michael McFail, Christine L. Lisetti, Malek Adjouadi |
Transparent grid enablement of weather research and forecasting. |
Mardi Gras Conference |
2008 |
DBLP DOI BibTeX RDF |
WRF, grid enablement, job flow management, modeling, profiling, portal, scientific applications, meta-scheduling |
8 | Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers |
Metrics for Architecture-Level Lifetime Reliability Analysis. |
ISPASS |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals |
Low-Cost Adaptive Data Prefetching. |
Euro-Par |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Guoping Long, Dongrui Fan, Junchao Zhang, Fenglong Song, Nan Yuan, Wei Lin 0004 |
A Performance Model of Dense Matrix Operations on Many-Core Architectures. |
Euro-Par |
2008 |
DBLP DOI BibTeX RDF |
dense matrix, performance model, memory bandwidth, many-core architecture |
8 | Benoît Dupont de Dinechin |
Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors. |
Euro-Par |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Noel Tomás, Julio Sahuquillo, Salvador Petit, Pedro López 0001 |
Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot. |
Euro-Par |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Mahmoud Ben Naser, Csaba Andras Moritz |
Power and performance tradeoffs with process variation resilient adaptive cache architectures. |
SBCCI |
2008 |
DBLP DOI BibTeX RDF |
process variations, leakage power, adaptive cache |
8 | Derek Chiou, Dam Sunwoo, Hari Angepat, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson |
Parallelizing computer system simulators. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, Chih-Wei Liu |
Improving datapathutilization of programmable DSP with composite functional units. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen |
Address compression for scalable load/store queue implementation. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Krishna M. Kavi, Wentong Li, Ali R. Hurson |
A Non-blocking Multithreaded Architecture with Support for Speculative Threads. |
ICA3PP |
2008 |
DBLP DOI BibTeX RDF |
Cache Coherency, Thread Level Speculation, Multithreaded Architectures, Decoupled Architecture |
8 | Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti |
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Zhonglei Wang, Antonio Sánchez, Andreas Herkersdorf |
SciSim: a software performance estimation framework using source code instrumentation. |
WOSP |
2008 |
DBLP DOI BibTeX RDF |
debugging information, software performance estimation, source code instrumentation, microarchitecture |
8 | Shijian Zhang, Weiwu Hu |
Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor. |
PRDC |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Power Reduction of Functional Units Considering Temperature and Process Variations. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Hans Vandierendonck, Sean Rul, Michiel Questier, Koen De Bosschere |
Experiences with Parallelizing a Bio-informatics Program on the Cell BE. |
HiPEAC |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Ernie Chan, Field G. Van Zee, Paolo Bientinesi, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn |
SuperMatrix: a multithreaded runtime scheduling system for algorithms-by-blocks. |
PPoPP |
2008 |
DBLP DOI BibTeX RDF |
algorithms-by-blocks, dynamic scheduling, dependency analysis, out-of-order execution |
8 | Xian-He Sun, Surendra Byna, Yong Chen 0001 |
Server-Based Data Push Architecture for Multi-Processor Environments. |
J. Comput. Sci. Technol. |
2007 |
DBLP DOI BibTeX RDF |
modeling, evaluation, performance measurement, cache memory, simulation of multiple-processor system |
8 | Yulai Zhao 0003, Xianfeng Li, Dong Tong 0001, Xu Cheng 0001 |
An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking. |
J. Comput. Sci. Technol. |
2007 |
DBLP DOI BibTeX RDF |
content associative memory (CAM), tag elimination, waiting instruction buffer, instruction scheduler, energy-efficient architecture |
8 | Steven Swanson, Andrew Schwerin, Martha Mercaldi, Andrew Petersen 0001, Andrew Putnam, Ken Michelson, Mark Oskin, Susan J. Eggers |
The WaveScalar architecture. |
ACM Trans. Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
WaveScalar, multithreading, dataflow computing |
8 | Samuel Williams 0001, John Shalf, Leonid Oliker, Shoaib Kamil 0001, Parry Husbands, Katherine A. Yelick |
Scientific Computing Kernels on the Cell Processor. |
Int. J. Parallel Program. |
2007 |
DBLP DOI BibTeX RDF |
GEMM, SpMV, three level memory, FFT, sparse matrix, Cell processor, Stencil |
8 | Chung-Ho Chen, Kuo-Su Hsiao |
Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
CAM-based wakeup logic, matrix-based wakeup logic, scalable instruction scheduler, wakeup spatial locality, low power, issue logic |
8 | José R. Herrero 0001, Juan J. Navarro |
Exploiting computer resources for fast nearest neighbor classification. |
Pattern Anal. Appl. |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang |
The Implementation and Evaluation of a Low-Power Clock Distribution Network Based on EPIC. |
NPC |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Rajesh Vivekanandham, R. Govindarajan |
A Scalable Low Power Store Queue for Large InstructionWindow Processors. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Shuai Wang 0006, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras |
Asymmetrically Banked Value-Aware Register Files. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Mahmoud Ben Naser, Yao Guo 0001, Csaba Andras Moritz |
Designing Memory Subsystems Resilient to Process Variations. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Antonio Carlos Schneider Beck, Luigi Carro |
Transparent acceleration of data dependent instructions for general purpose processors. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Subhasis Banerjee, G. Surendra, S. K. Nandy 0001 |
Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu |
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Wangyuan Zhang, Xin Fu, Tao Li 0006, José A. B. Fortes |
An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
thread-aware reliability optimization, microarchitecture vulnerability, simultaneous multithreaded architecture, semiconductor transient fault, microprocessor reliability, processor throughput, soft error vulnerability analysis, SPEC CPU 2000 benchmark, microarchitecture structure, microarchitecture reliability profile, fetch policy, thread-level parallelism, multithreading architecture |
8 | Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang |
The Implementation and Design of a Low-Power Clock Distribution Microarchitecture. |
IEEE NAS |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Partha Tirumalai, Yonghong Song, Spiros Kalogeropulos |
Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures. |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Thomas Piquet, Olivier Rochecouste, André Seznec |
Exploiting Single-Usage for Effective Memory Management. |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith 0001, Gu-Yeon Wei, David M. Brooks |
Towards a software approach to mitigate voltage emergencies. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
dynamic optimization framework, voltage emergencies, hardware-software codesign, di/dt |
8 | Somnath Paul, Swarup Bhunia |
Memory based computation using embedded cache for processor yield and reliability improvement. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Qingying Deng, Minxuan Zhang, Jiang Jiang |
A Parallel Infrastructure on Dynamic EPIC SMT. |
ICA3PP |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Piotr Zajac, Jacques Henri Collet |
Production Yield and Self-Configuration in the Future Massively Defective Nanochips. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Hans Vandierendonck, André Seznec |
Fetch Gating Control Through Speculative Instruction Window Weighting. |
HiPEAC |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh |
Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. |
HiPEAC |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary |
Transparent control independence (TCI). |
ISCA |
2007 |
DBLP DOI BibTeX RDF |
control independence, selective re-execution, selective recovery, checkpoints, branch prediction, speculation |
8 | Ernie Chan, Field G. Van Zee, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn |
Satisfying your dependencies with SuperMatrix. |
CLUSTER |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Ernie Chan, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn |
Supermatrix out-of-order scheduling of matrix operations for SMP and multi-core architectures. |
SPAA |
2007 |
DBLP DOI BibTeX RDF |
data affinity, data-flow parallelism, dense linear algebra libraries, dynamic scheduling, out-of-order execution |
8 | Seong-Won Lee, Jean-Luc Gaudiot |
Throttling-Based Resource Management in High Performance Multithreaded Architectures. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
Resource management, power management, multithreading, resource utilization, throttling |
8 | Jaeheon Jeong, Michel Dubois 0001 |
Cache Replacement Algorithms with Nonuniform Miss Costs. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
Cache, power, latency, trace-driven simulations, memory system, replacement policy |
8 | Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero |
Branch predictor guided instruction decoding. |
PACT |
2006 |
DBLP DOI BibTeX RDF |
complexity-effective, instruction decoding, branch predictor |
8 | Mladen Berekovic, Tim Niggemeier |
A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme. |
SAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Zenaide Carvalho da Silva, João Angelo Martini, Ronaldo Augusto Lara Gonçalves |
Extending the PPM Branch Predictor. |
PDP |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Luiz Vinicius Marra Ribas, Ronaldo Augusto de Lara Gonçalves |
Evaluating Branch Prediction Using Two-Level Perceptron Table. |
PDP |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López |
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Xin Fu, James Poe, Tao Li, José A. B. Fortes |
Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior. |
MASCOTS |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Soontae Kim |
Area-efficient error protection for caches. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar |
A Power-Aware Technique for Functional Units in High-Performance Processors. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Anne Bracy, Amir Roth |
Serialization-Aware Mini-Graphs: Performance with Fewer Resources. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Samantika Subramaniam, Gabriel H. Loh |
Store vectors for scalable memory dependence prediction and scheduling. |
HPCA |
2006 |
DBLP DOI BibTeX RDF |
|
8 | P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil |
Construction and use of linear regression models for processor performance analysis. |
HPCA |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Yingmin Li, Benjamin C. Lee, David M. Brooks, Zhigang Hu, Kevin Skadron |
CMP design space exploration subject to physical constraints. |
HPCA |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Venkatesan Packirisamy, Shengyue Wang, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew |
Supporting Speculative Multithreading on Simultaneous Multithreaded Processors. |
HiPC |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Chen-Yong Cher, Il Park 0001, T. N. Vijaykumar |
Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?. |
ARCS |
2006 |
DBLP DOI BibTeX RDF |
|
Displaying result #701 - #800 of 1093 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ 11][ >>] |
|