Search results for "synthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Aleksey Golovinskiy, Wojciech Matusik, Hanspeter Pfister, Szymon Rusinkiewicz, Thomas A. Funkhouser	A statistical model for synthesis of detailed facial geometry.	ACM Trans. Graph.	2006	DBLP DOI BibTeX RDF	texture synthesis, face modeling
19	Shaun Bangay, Chantelle Morkel	Graph matching with subdivision surfaces for texture synthesis on surfaces.	Afrigraph	2006	DBLP DOI BibTeX RDF	vertex region matching, texture synthesis, subdivision surfaces, graph cut
19	Qiang Fang, Jianwu Dang 0001	Speech Synthesis Based on a Physiological Articulatory Model.	ISCSLP	2006	DBLP DOI BibTeX RDF	physiological articulatory model, Chinese vowel, speech synthesis, acoustic model, speech production
19	Muhammad Omer Cheema, Omar Hammami	Customized SIMD unit synthesis for system on programmable chip: a foundation for HW/SW partitioning with vectorization.	ASP-DAC	2006	DBLP DOI BibTeX RDF	AltiVec architecture, SIMD synthesis, vectorization, HW/SW codesign
19	Nadia Mana, Fabio Pianesi	HMM-based synthesis of emotional facial expressions during speech in synthetic talking heads.	ICMI	2006	DBLP DOI BibTeX RDF	MPEG4 facial animation, emotional facial expression modeling, face synthesis, hidden Markov models, talking heads
19	Borzoo Bonakdarpour, Sandeep S. Kulkarni	Automated Incremental Synthesis of Timed Automata.	FMICS/PDMC	2006	DBLP DOI BibTeX RDF	Bounded liveness, Bounded response, Real-time, Formal methods, Synthesis, Transformation, Timed automata
19	Ying Zhang, Raffi R. Kamalian, Alice M. Agogino, Carlo H. Séquin	Design synthesis of microelectromechanical systems using genetic algorithms with component-based genotype representation.	GECCO	2006	DBLP DOI BibTeX RDF	MEMS design synthesis, MOGA, component-based genotype representation, evolutionary multiobjective optimization
19	Yi Lin	3D character animation synthesis from 2D sketches.	GRAPHITE	2006	DBLP DOI BibTeX RDF	animation synthesis, sketching-based interface
19	Hongzhi Liang, Jürgen Dingel, Zinovy Diskin	A comparative survey of scenario-based to state-based model synthesis approaches.	SCESM	2006	DBLP DOI BibTeX RDF	model, UML, petri nets, synthesis, scenario, SDL, state machines, MSC
19	Maria José Pereira Dantas, Leonardo da C. Brito, Paulo Henrique Portela de Carvalho	Multi-objective Memetic Algorithm Applied to the Automated Synthesis of Analog Circuits.	IBERAMIA-SBIA	2006	DBLP DOI BibTeX RDF	multi-objective memetic algorithm, 2D representation, analog circuit, building-blocks, automated synthesis
19	Sujan Pandey, Manfred Glesner	Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.	DAC	2006	DBLP DOI BibTeX RDF	communication bus synthesis, voltage scaling
19	Tao Xu 0002, Krishnendu Chakrabarty	Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	connect-5 algorithm, droplet trace, droplet-based microfluidics, pin-constrained biochip design, synthesis
19	Neal K. Bambha, Shuvra S. Bhattacharyya	Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	scheduling, task graphs, interconnect synthesis, Embedded multiprocessors
19	Roberto Ziller, Klaus Schneider 0001	Combining supervisor synthesis and model checking.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	Ramadge-Wonham, supervisor synthesis, model checking
19	Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh	A scheduling algorithm for optimization and early planning in high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Scheduling, high-level synthesis, data flow graph, bipartite matching
19	Junyu Dong, Mike J. Chantler	Capture and Synthesis of 3D Surface Texture.	Int. J. Comput. Vis.	2005	DBLP DOI BibTeX RDF	texture synthesis, psychophysical experiment, surface texture
19	Sandeep S. Kulkarni, Ali Ebnenasir	Complexity Issues in Automated Synthesis of Failsafe Fault-Tolerance.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	Fault-tolerance, formal methods, distributed programs, program synthesis, automatic addition of fault-tolerance
19	Song Peng, David Fang, John Teifel, Rajit Manohar	Automated synthesis for asynchronous FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	asychronous circuits, programmable logic, automated synthesis
19	Jun Sun 0001, Jin Song Dong	Synthesis of Distributed Processes from Scenario-Based Specifications.	FM	2005	DBLP DOI BibTeX RDF	Synthesis, CSP, LSC
19	Rajeev Alur, Pavol Cerný, P. Madhusudan, Wonhong Nam	Synthesis of interface specifications for Java classes.	POPL	2005	DBLP DOI BibTeX RDF	behavioral interfaces, learning regular languages, model checking, games, abstraction, synthesis, software components
19	Renato Fernandes Hentschke, Jagannathan Narasimhan, David S. Kung 0001	Improving run times by pruned application of synthesis transforms.	SBCCI	2005	DBLP DOI BibTeX RDF	synthesis, filtering, buffering, driver, resizing
19	Sujan Pandey, Manfred Glesner, Max Mühlhäuser	Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture.	SBCCI	2005	DBLP DOI BibTeX RDF	on-chip communication architecture synthesis, optimization, algorithms
19	Robert H. Bell Jr., Lizy Kurian John	Improved automatic testcase synthesis for performance model validation.	ICS	2005	DBLP DOI BibTeX RDF	automatic benchmark synthesis, synthetic benchmarks, benchmarking, performance modeling
19	Lakin Wecker, Faramarz F. Samavati, Marina L. Gavrilova	Iris synthesis: a reverse subdivision application.	GRAPHITE	2005	DBLP DOI BibTeX RDF	biometric synthesis, reverse subdivision, biometrics, multiresolution, image generation
19	Fei Su, Krishnendu Chakrabarty	Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips.	DAC	2005	DBLP DOI BibTeX RDF	synthesis, placement, defect tolerance, microfluidics, biochip
19	Krishnendu Chakrabarty, Fei Su	System-level design automation tools for digital microfluidic biochips.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	synthesis, physical design, microfluidics, biochip
19	Jian S. Dai, Tieshi Zhao, Christopher Nester	Sprained Ankle Physiotherapy Based Mechanism Synthesis and Stiffness Analysis of a Robotic Rehabilitation Device.	Auton. Robots	2004	DBLP DOI BibTeX RDF	sprained ankles, physiotherapy, orientation analysis, parallel robotic mechanisms, rehabilitation, stiffness, mechanism synthesis
19	Andrew Klapper, Jinzhong Xu	Register Synthesis for Algebraic Feedback Shift Registers Based on Non-Primes.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	register synthesis, N-adic numbers, stream cipher, pseudorandom generator, feedback shift register
19	Sinh Hoa Nguyen, Jan G. Bazan, Andrzej Skowron, Hung Son Nguyen	Layered Learning for Concept Synthesis.	Trans. Rough Sets	2004	DBLP DOI BibTeX RDF	Concept synthesis, hierarchical schema, layered learning, rough sets
19	Hyunok Oh, Soonhoi Ha	Fractional Rate Dataflow Model for Efficient Code Synthesis.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	synchronous dataflow (SDF), multimedia, memory optimization, code synthesis
19	Shmuel Moradoff, Dani Lischinski	Constrained synthesis of textural motion for articulated characters.	Vis. Comput.	2004	DBLP DOI BibTeX RDF	Articulated characters, Motion editing/synthesis/reuse, Textural motion, Animation, Constraints
19	Sandeep S. Kulkarni, Ali Ebnenasir	Automated Synthesis of Multitolerance.	DSN	2004	DBLP DOI BibTeX RDF	Fault-tolerance, Formal methods, Distributed programs, Program synthesis, Automatic addition of fault-tolerance
19	Djones Lettnin, Axel G. Braun, Martin Bogdan, Joachim Gerlach, Wolfgang Rosenstiel	Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks.	DATE	2004	DBLP DOI BibTeX RDF	SystemC Synthesis, Hardware Neural Network (HNN), Embedded Systems, Rapid Prototyping, Electrocardiogram (ECG), Digital System Design
19	Abdil Rashid Mohamed, Zebo Peng, Petru Eles	A Heuristic for Wiring-Aware Built-In Self-Test Synthesis.	DSD	2004	DBLP DOI BibTeX RDF	BIST insertion, wiring area, test synthesis
19	Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers	Synthesis of Speed Independent Circuits Based on Decomposition.	ASYNC	2004	DBLP DOI BibTeX RDF	abstraction, synthesis, Decomposition, STGs, speed-independent circuits
19	Ge Wang 0002, Perry R. Cook	ChucK: a programming language for on-the-fly, real-time audio synthesis and multimedia.	ACM Multimedia	2004	DBLP DOI BibTeX RDF	audio synthesis, multimedia, real-time, compiler, concurrency, synchronization, virtual machine, programming language, signal processing
19	Victor Khomenko, Maciej Koutny, Alexandre Yakovlev	Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT.	ACSD	2004	DBLP DOI BibTeX RDF	net unfoldings, partial order techniques, Petri nets, logic synthesis, asynchronous circuits, SAT, signal transition graphs, STG, self-timed circuits
19	Lujin Wang, Klaus Mueller 0001	Generating Sub-Resolution Detail in Images and Volumes Using Constrained Texture Synthesis.	IEEE Visualization	2004	DBLP DOI BibTeX RDF	texture synthesis, semantic zoom
19	Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin 0001	A memory aware behavioral synthesis tool for real-time VLSI circuits.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	memory aware, behavioral synthesis, VLSI circuits
19	Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley	A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits.	DAC	2004	DBLP DOI BibTeX RDF	modeling, synthesis, layout, sizing, parasitic, radio frequency
19	Pawel Kerntopf	A new heuristic algorithm for reversible logic synthesis.	DAC	2004	DBLP DOI BibTeX RDF	reversible logic circuits, synthesis
19	Thomas Ellman, Ryan Deak, Jason Fotinatos	Automated Synthesis of Numerical Programs for Simulation of Rigid Mechanical Systems in Physics-Based Animation.	Autom. Softw. Eng.	2003	DBLP DOI BibTeX RDF	specification, program, synthesis, numerical
19	Lech Józwiak	Advanced AI Search Techniques in Modern Digital Circuit Synthesis.	Artif. Intell. Rev.	2003	DBLP DOI BibTeX RDF	automated design problem solving, double-beam search, genetic engineering algorithm, quick scan, artificial intelligence, heuristic search, circuit synthesis
19	Norimichi Tsumura, Nobutoshi Ojima, Kayoko Sato, Mitsuhiro Shiraishi, Hideto Shimizu, Hirohide Nabeshima, Syuuichi Akazaki, Kimihiko Hori, Yoichi Miyake	Image-based skin color and texture analysis/synthesis by extracting hemoglobin and melanin information in the skin.	ACM Trans. Graph.	2003	DBLP DOI BibTeX RDF	hemoglobin, inverse lighting, melanin, physiologically-based rendering, pyramid-based texture analysis and synthesis, skin texture, independent component analysis, skin color
19	Hitoshi Yamauchi, Jörg Haber, Hans-Peter Seidel	Image Restoration using Multiresolution Texture Synthesis and Image Inpainting.	Computer Graphics International	2003	DBLP DOI BibTeX RDF	multiresolution texture synthesis, image in-painting, frequency decomposition, image restoration
19	Traianos V. Yioultsis, Anne Woo, Andreas C. Cangellaris	Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules.	ICCAD	2003	DBLP DOI BibTeX RDF	Transmission-line modeling of interconnects, interconnects with frequency-dependent losses, passive reduced- order synthesis
19	Anne-Claire Guillou, Patrice Quinton, Tanguy Risset	Hardware Synthesis for Multi-Dimensional Time.	ASAP	2003	DBLP DOI BibTeX RDF	multi-dimensional scheduling, fpga, High-level synthesis, systolic architecture
19	Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong 0001, Anand Raghunathan, Niraj K. Jha	A comprehensive high-level synthesis system for control-flow intensive behaviors.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	control-flow intensive behaviors, high-level synthesis, low power design
19	Marc D. Riedel, Jehoshua Bruck	The synthesis of cyclic combinational circuits.	DAC	2003	DBLP DOI BibTeX RDF	feedback, logic synthesis, cycles, combinational logic
19	Shaojie Wang, Sharad Malik	Synthesizing operating system based device drivers in embedded systems.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	embedded system software, operating system based software synthesis, device driver, correct-by-construction
19	N. Ranganathan, Ashok K. Murugavel	A low power scheduler using game theory.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	game theory, high-level synthesis, low power design, auction theory
19	Laurence Goodby, Alex Orailoglu, Paul M. Chau	Microarchitectural synthesis of performance-constrained, low-power VLSI designs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	DSP datapath design, High-level synthesis, low-power design
19	Haibo Wang 0005, Sarma B. K. Vrudhula	Behavioral synthesis of field programmable analog array circuits.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Programmable circuits, analog synthesis
19	Massimiliano Chiodo	Optimization and synthesis for complex reactive embedded systems by incremental collapsing.	CODES	2002	DBLP DOI BibTeX RDF	real-time systems, embedded systems, finite-state machines, software synthesis
19	Jingcao Hu, Yangdong Deng, Radu Marculescu	System-Level Point-to-Point Communication Synthesis using Floorplanning Information.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	System-leve design, low-power, floorplanning, Communication synthesis, point-to-point communication
19	Aurelio Uncini	Sound Synthesis by Flexible Activation Function Recurrent Neural Networks.	WIRN	2002	DBLP DOI BibTeX RDF	flexible activation function, spline neural networks, power-of-two neural networks, physical model, sound synthesis
19	Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee	PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations.	CASES	2002	DBLP DOI BibTeX RDF	FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization
19	Paul C. Attie, E. Allen Emerson	Synthesis of concurrent programs for an atomic read/write model of computation.	ACM Trans. Program. Lang. Syst.	2001	DBLP DOI BibTeX RDF	specification, temporal logic, concurrent programs, program synthesis, atomic registers
19	Sandeep S. Kulkarni, Anish Arora, Arun Chippada	Polynomial Time Synthesis of Byzantine Agreement.	SRDS	2001	DBLP DOI BibTeX RDF	Fault-tolerance, Formal methods, Program transformation, Distributed programs, Program synthesis
19	Dong-In Kang, Richard Gerber 0001, Manas Saksena	Parametric Design Synthesis of Distributed Embedded Systems.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Design synthesis, statistical performance, distributed systems, embedded systems, soft real-time
19	Hussein Karam, Aboul Ella Hassanien, Masayuki Nakajima 0001	Visual Simulation of Texture/Non-Texture Image Synthesis.	Computer Graphics International	2000	DBLP DOI BibTeX RDF	Double-pushout Construction, Texture Synthesis, Fractals, Graph Grammars, L-System, Pattern Generation, Graph Productions
19	Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien	A Constructive Solution to the Juggling Problem in Processor Array Synthesis.	IPDPS	2000	DBLP DOI BibTeX RDF	Systolic array synthesis, Affine scheduling
19	Tadeusz Luba, Claudio Moraga, Svetlana N. Yanushkevich, Vlad P. Shmerko, Joanna Kolodziejczyk	Application of Design Style in Evolutionary Multi-Level Networks Synthesis.	EUROMICRO	2000	DBLP DOI BibTeX RDF	multi-level synthesis, information theory approach, parallelism, evolutionary design
19	Fabiano Hessel, Philippe Coste, Gabriela Nicolescu, P. LeMarrec, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya	Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification.	ICCD	2000	DBLP DOI BibTeX RDF	Multilanguage, Codesign, Communication Synthesis
19	Robert P. Dick, Niraj K. Jha	COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF	low-power, wireless, client-server, multiobjective, evolutionary, co-synthesis
19	Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan 0002	CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis.	VLSI Design	2000	DBLP DOI BibTeX RDF	Register and Module Assignment Design for low power, High level synthesis, Low power design, Floorplanning
19	Luis Alejandro Cortés, Petru Eles, Zebo Peng	Definitions of Equivalence for Transformational Synthesis of Embedded Systems.	ICECCS	2000	DBLP DOI BibTeX RDF	transformational synthesis, PRES+, explicit notion, Ethernet network coprocessor, embedded systems, Petri nets, computational model, equivalence, embedded systems design, data transformation, formal notation, design cycles, complex task
19	William E. Dougherty, Donald E. Thomas	Unifying behavioral synthesis and physical design.	DAC	2000	DBLP DOI BibTeX RDF	behavioral/high level synthesis, physical design
19	Franco Fummi, Donatella Sciuto, Micaela Serra	Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	sequential circuits, functional testing, Synthesis for testability, logic minimization, redundant faults, redundancies removal
19	Lieu-Hen Chen, Santi Saeyor, Hiroshi Dohi, Mitsuru Ishizuka	A system of 3D hair style synthesis based on the wisp model.	Vis. Comput.	1999	DBLP DOI BibTeX RDF	3D CG hair style, Hair image synthesis, Wisp model, CG human characters, Anthropomorphic agent
19	Craig A. Lindley	Generic Film Forms for Dynamic Virtual Video Synthesis.	ICMCS, Vol. 2	1999	DBLP DOI BibTeX RDF	virtual video, Content-based retrieval, video synthesis
19	Fabiano Hessel, Philippe Coste, P. LeMarrec, Nacer-Eddine Zergainoh, Jean-Marc Daveau, Ahmed Amine Jerraya	Communication Interface Synthesis for Multilanguage Specifications.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	Multilanguage Codesign, Interface Synthesis
19	Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen	Software Synthesis for System Level Design Using Process Execution Trees.	EUROMICRO	1999	DBLP DOI BibTeX RDF	system level design language, simulation, operational semantics, software synthesis
19	Pradip K. Jha, Steven Barnfield, John B. Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi	Synthesis of Arrays and Records.	ICCD	1999	DBLP DOI BibTeX RDF	Aggregate data types, Synthesis, Array, Record
19	Ishwar Parulkar, Sandeep K. Gupta 0001, Melvin A. Breuer	Estimation of BIST Resources During High-Level Synthesis.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	built-in self-test, high-level synthesis, estimation
19	Christos A. Papachristou, Mikhail Baklashov, Kowen Lai	High-Level Test Synthesis for Behavioral and Structural Designs.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	built-in self test, DFT, test synthesis
19	Sanjay Bhansali, Tim J. Hoar	Automated Software Synthesis: An Application in Mechanical CAD.	IEEE Trans. Software Eng.	1998	DBLP DOI BibTeX RDF	geometric constraint-satisfaction, planning, reuse, Program synthesis, domain engineering
19	Paul C. Attie, E. Allen Emerson	Synthesis of Concurrent Systems with Many Similar Processes.	ACM Trans. Program. Lang. Syst.	1998	DBLP DOI BibTeX RDF	temporal logic, concurrent programs, program synthesis
19	Irith Pomeranz, Sudhakar M. Reddy	A Synthesis Procedure for Flexible Logic Functions.	DATE	1998	DBLP DOI BibTeX RDF	comparison units, flexible functions, logic synthesis
19	Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha	IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits.	DATE	1998	DBLP DOI BibTeX RDF	multiplexer re-structuring, low power, high-level synthesis, resource sharing, control-flow, module selection
19	Michael Gasteier, Manfred Glesner, Michael Münch	Generation of Interconnect Topologies for Communication Synthesis.	DATE	1998	DBLP DOI BibTeX RDF	bus generation, channel merging, Communications synthesis
19	Homan Igehy, Lucas Pereira	Image replacement through texture synthesis.	ICIP (3)	1997	DBLP DOI BibTeX RDF	image replacement, undesired feature, synthetic texture, stochastic areas, texture synthesis, image texture, image composition
19	Boon-Lock Yeo, Minerva M. Yeung	Analysis and Synthesis for New Digital Video Applications.	ICIP (1)	1997	DBLP DOI BibTeX RDF	digital video applications, digital TV broadcast, digital video analysis, digital video synthesis, Internet, image processing, research, video databases, digital television, compressed video, CD ROM
19	Kowen Lai, Christos A. Papachristou, Mikhail Baklashov	BIST testability enhancement using high level test synthesis for behavioral and structural designs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	BIST testability, behavioral designs, industrial benchmark, controllability, built-in self test, observability, DFT, transparency, fidelity, structural designs, high level test synthesis
19	Ross B. Ortega, Gaetano Borriello	Communication Synthesis for Embedded Systems with Global Considerations.	CODES	1997	DBLP DOI BibTeX RDF	communication protocols, distributed embedded systems, communication synthesis
19	Jürgen Teich, Tobias Blickle, Lothar Thiele	An evolutionary approach to system-level synthesis.	CODES	1997	DBLP DOI BibTeX RDF	architecture selection, cost constraints, graph-based mapping model, heterogeneous hardware/software architecture, optimal mapping, performance constraints, task-level specification mapping, video-codec implementations, genetic algorithms, scheduling, memories, ASICs, design space exploration, allocation, optimization problem, binding, buses, system-level synthesis, evolutionary approach, algorithm mapping, general-purpose processors, dedicated processors
19	Pai H. Chou, Gaetano Borriello	Software Architecture Synthesis for Retargetable Real-time Embedded Systems.	CODES	1997	DBLP DOI BibTeX RDF	control-dominated, software architecture synthesis, embedded systems, reactive systems, Run-time systems, real-time constraints
19	Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw	Library-less synthesis for static CMOS combinational logic circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	library-less synthesis, resynthesized circuits, size-wise CMOS circuit optimization, static CMOS combinational logic circuits, structural CMOS circuit optimization, transistor level technique, CMOS logic circuits, design space, optimal design, circuit performance
19	Robert P. Dick, Niraj K. Jha	MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems.	ICCAD	1997	DBLP DOI BibTeX RDF	hardware-software, genetic algorithm, embedded system, low power, co-design, multiobjective, co-synthesis
19	Alessandro Armando, Alan Smaill, Ian Green	Automatic Synthesis of Recursive Programs: The Proof-Planning Paradigm.	ASE	1997	DBLP DOI BibTeX RDF	proof-planning paradigm, recursive functional programs, functional programming, correctness proofs, automatic synthesis, recursive programs, unification algorithm
19	Giacomo Buonanno, M. Pugassi, Mariagiovanna Sami	A high-level synthesis approach to design of fault-tolerant systems.	VTS	1997	DBLP DOI BibTeX RDF	hardware-software system, design, embedded system, fault tolerant computing, high-level synthesis, reconfiguration, scheduling algorithm, cost, processor, fault-tolerant system
19	Ellen Sentovich	Quick Conservative Causality Analysis.	ISSS	1997	DBLP DOI BibTeX RDF	quick conservative causality analysis, causality problem, standard logic synthesis techniques, combinational circuits, combinational circuit, conservative algorithm
19	Janos Sztipanovits, Gabor Karsai, Hubertus Franke	Model-Integrated Program Synthesis Environment.	ECBS	1996	DBLP DOI BibTeX RDF	program synthesis, model-based systems, domain-specific software architecture
19	Daniel Scharstein	Stereo Vision for View Synthesis.	CVPR	1996	DBLP DOI BibTeX RDF	image-based scene representations, virtual reality, occlusion, stereo vision, view synthesis
19	Peter Grün, Petru Eles, Krzysztof Kuchcinski, Zebo Peng	Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis.	EUROMICRO	1996	DBLP DOI BibTeX RDF	Petri net-based design representation, internal design representation, hardware structures, conflict freeness, hierarchical Petri net structure, CAMAD, complexity, parallelization process, Petri nets, high-level synthesis, automatic parallelization, design environment, safeness
19	X. Wendling, Raphaël Rochet, Régis Leveugle	Standard and ROM-based synthesis of FSMs with control flow checking capabilities.	VTS	1996	DBLP DOI BibTeX RDF	read-only storage, sequencing error detection, ROM architecture, finite state machines, finite state machine, integrated circuit testing, error detection, automatic testing, integrated circuit design, FSM, automatic synthesis, control flow checking
19	Chittaranjan A. Mandal, P. P. Chakrabarti 0001, Sujoy Ghose	Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach.	VLSI Design	1996	DBLP DOI BibTeX RDF	Multi-port Memory, Genetic Algorithm, VLSI, Binding, Data Path Synthesis
19	Federico Pedersini, Augusto Sarti, Stefano Tubaro	Synthesis of virtual views using non-Lambertian reflectivity models and stereo matching.	ICIP	1995	DBLP DOI BibTeX RDF	nonLambertian reflectivity models, virtual views synthesis, calibrated multicamera system, 3D edges, stereometric algorithms, curvature tuning points, 3D coordinates, estimated object surface, reflection corrected luminance function, texture correction, interpolation, reflectivity, texture mapping, calibration, image matching, cameras, stereo image processing, image texture, stereo matching, reflectivity model, real images, surface interpolation, brightness, image plane, MSE, 3D scene
19	Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Sequential synthesis using S1S.	ICCAD	1995	DBLP DOI BibTeX RDF	S1S, sequntial synthesis, discrete control, finite state machine
19	Chuan-Yu Wang, Kaushik Roy 0001	Control unit synthesis targeting low-power processors.	ICCD	1995	DBLP DOI BibTeX RDF	control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming