Search results for "ASAP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat	Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards.	ASAP	2006	DBLP DOI BibTeX RDF
1	Paul L. Master	Reconfigurable Hardware and Software Architectural Constructs for the Enablement of Resilient Computing Systems.	ASAP	2006	DBLP DOI BibTeX RDF
1	Thorsten von Sydow, Bernd Neumann, Holger Blume, Tobias G. Noll	Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic.	ASAP	2006	DBLP DOI BibTeX RDF
1	Woo Hyung Lee, Pinaki Mazumder	Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder.	ASAP	2006	DBLP DOI BibTeX RDF
1	Grant Martin	Recent Developments in Configurable and Extensible Processors.	ASAP	2006	DBLP DOI BibTeX RDF
1	Thomas Warsaw, Marcin Lukowiak	Architecture design of an H.264/AVC decoder for real-time FPGA implementation.	ASAP	2006	DBLP DOI BibTeX RDF
1	Antoine Scherrer, Antoine Fraboulet, Tanguy Risset	A Generic Multi-Phase On-Chip Traffic Generation Environment.	ASAP	2006	DBLP DOI BibTeX RDF
1		2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA	ASAP	2006	DBLP BibTeX RDF
1	Daesun Oh, Keshab K. Parhi	Low Complexity Design of High Speed Parallel Decision Feedback Equalizers.	ASAP	2006	DBLP DOI BibTeX RDF
1	Drew Taussig, Andreas Hoffmann 0002, Achim Nohl, Andrea Kroll	Application Specific Processing: A Tools Approach.	ASAP	2006	DBLP DOI BibTeX RDF
1	Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede	Throughput Optimized SHA-1 Architecture Using Unfolding Transformation.	ASAP	2006	DBLP DOI BibTeX RDF
1	Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil	Parameterized Looped Schedules for Compact Representationof Execution Sequences.	ASAP	2006	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi	NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm.	ASAP	2006	DBLP DOI BibTeX RDF
1	Yiyu Tan, Chihang Yau, Anthony S. Fong	Architectural Support on Object-Oriented Programming in a JAVA Processor.	ASAP	2006	DBLP DOI BibTeX RDF
1	Humberto Calderon, Stamatis Vassiliadis	Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit.	ASAP	2006	DBLP DOI BibTeX RDF
1	Mythri Alle, Jayanta Biswas, S. K. Nandy 0001	High Performance VLSI Architecture Design for H.264 CAVLC Decoder.	ASAP	2006	DBLP DOI BibTeX RDF
1	Carl Ebeling	Configurable Computing Platforms - Promises, Promises.	ASAP	2006	DBLP DOI BibTeX RDF
1	Peter R. Cappello	Multicore processors as Array Processors: Research Opportunities.	ASAP	2006	DBLP DOI BibTeX RDF
1	Cor Meenderinck, Sorin Cotofana, Casper Lageweg	High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology.	ASAP	2005	DBLP DOI BibTeX RDF
1	Konrad Walus, Mike Mazur, Gabriel Schulhof, Graham A. Jullien	Simple 4-Bit Processor Based On Quantum-Dot Cellular Automata (QCA).	ASAP	2005	DBLP DOI BibTeX RDF
1	Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala	256-State Rate 1/2 Viterbi Decoder on TTA Processor.	ASAP	2005	DBLP DOI BibTeX RDF
1	Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis	Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform.	ASAP	2005	DBLP DOI BibTeX RDF	SIMD extensions, Discrete Wavelet Transform, lifting scheme
1	M. Van Der Horst, Kees van Berkel 0001, Johan Lukkien, Rudolf H. Mak	Recursive Filtering on a Vector DSP with Linear Speedup.	ASAP	2005	DBLP DOI BibTeX RDF
1	Enrico Ng, Gyungho Lee	Eliminating Sorting in IP Lookup Devices using Partitioned Table.	ASAP	2005	DBLP DOI BibTeX RDF
1	Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata	On-line Multioperand Addition Based on On-line Full Adders.	ASAP	2005	DBLP DOI BibTeX RDF
1		16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece	ASAP	2005	DBLP BibTeX RDF
1	Nikolaos Kavvadias, Spiridon Nikolaidis 0001	Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding.	ASAP	2005	DBLP DOI BibTeX RDF
1	Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere	Expression Synthesis in Process Networks generated by LAURA.	ASAP	2005	DBLP DOI BibTeX RDF
1	Andreas Fidjeland, Wayne Luk	Customising Application-Speci.c Multiprocessor Systems: a Case Study.	ASAP	2005	DBLP DOI BibTeX RDF
1	Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal	On the Advantages of Serial Architectures for Low-Power Reliable Computations.	ASAP	2005	DBLP DOI BibTeX RDF
1	Ludovic L'Hours	Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications.	ASAP	2005	DBLP DOI BibTeX RDF
1	Milos D. Ercegovac, Jean-Michel Muller	Variable Radix Real and Complex Digit-Recurrence Division.	ASAP	2005	DBLP DOI BibTeX RDF
1	Stamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev	The Midlifekicker Microarchitecture Evaluation Metric.	ASAP	2005	DBLP DOI BibTeX RDF	pipeline, microarchitecture, ILP
1	Jayaprakash Pisharath, Alok N. Choudhary	Design of a Hardware Accelerator for Density Based Clustering Applications.	ASAP	2005	DBLP DOI BibTeX RDF
1	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware.	ASAP	2005	DBLP DOI BibTeX RDF
1	Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon	Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x.	ASAP	2005	DBLP DOI BibTeX RDF
1		External Referees.	ASAP	2005	DBLP DOI BibTeX RDF
1		Copyright Page.	ASAP	2005	DBLP DOI BibTeX RDF
1	Lejla Batina, Nele Mentens, Bart Preneel, Ingrid Verbauwhede	Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2n).	ASAP	2005	DBLP DOI BibTeX RDF	Multiplication in GF(2^n), Systolic array architecture, Montgomery method for point multiplication, Elliptic Curve Cryptography (ECC), Hardware implementation
1	Sudeep Pasricha, Mohamed Ben-Romdhane	Using TLM for Exploring Bus-based SoC Communication Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
1	Alain Darte, Steven Derrien, Tanguy Risset	Hardware/Software Interface for Multi-Dimensional Processor Arrays.	ASAP	2005	DBLP DOI BibTeX RDF
1	Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina	Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.	ASAP	2005	DBLP DOI BibTeX RDF
1	Bharath N, Nagaraju Bussa	Artificial Deadlock Detection in Process Networks for ECLIPSE.	ASAP	2005	DBLP DOI BibTeX RDF
1	Yang Yang 0040, Tong Jing, Xianlong Hong, Yu Hu 0002, Qi Zhu 0002, Xiaodong Hu 0001, Guiying Yan	Via-Aware Global Routing for Good VLSI Manufacturability and High Yield.	ASAP	2005	DBLP DOI BibTeX RDF
1	Amilcar do Carmo Lucas, Rolf Ernst	An Image Processor for Digital Film.	ASAP	2005	DBLP DOI BibTeX RDF	weak-programing, stream-based architechture, digital .lm, recon.gurable, FPGA
1	Jie Han 0001, Erin Taylor 0001, Jianbo Gao, José A. B. Fortes	Faults, Error Bounds and Reliability of Nanoelectronic Circuits.	ASAP	2005	DBLP DOI BibTeX RDF
1	Maria J. Avedillo, José M. Quintana, Héctor Pettenghi	Logic Models Supporting the Design of MOBILE-based RTD Circuits.	ASAP	2005	DBLP DOI BibTeX RDF
1	João M. P. Cardoso	On Estimations for Compiling Software to FPGA-based Systems.	ASAP	2005	DBLP DOI BibTeX RDF
1	Michael T. Frederick, Nathan A. VanderHorn, Arun K. Somani	Real-time H/W Implementation of the Approximate Discrete Radon Transform.	ASAP	2005	DBLP DOI BibTeX RDF
1	Kuo-Kun Tseng, Ying-Dar Lin, Tsern-Huei Lee, Yuan-Cheng Lai	A Parallel Automaton String Matching with Pre-Hashing and Root-Indexing Techniques for Content Filtering Coprocessor.	ASAP	2005	DBLP DOI BibTeX RDF
1	Jan-Willem van de Waerdt, Stamatis Vassiliadis	Instruction Set Architecture Enhancements for Video Processing.	ASAP	2005	DBLP DOI BibTeX RDF
1		Program Committee.	ASAP	2005	DBLP DOI BibTeX RDF
1	Liang-Kai Wang, Michael J. Schulte	Decimal Floating-Point Square Root Using Newton-Raphson Iteration.	ASAP	2005	DBLP DOI BibTeX RDF
1	Ian Steiner, P. Chan, Laurent Imbert, Graham A. Jullien, Vassil S. Dimitrov, G. H. McGibney	A Fault-Tolerant Modulus Replication Complex FIR Filter.	ASAP	2005	DBLP DOI BibTeX RDF
1	Vida Kianzad, Shuvra S. Bhattacharyya, Gang Qu 0001	CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems.	ASAP	2005	DBLP DOI BibTeX RDF
1	Amir Hosein Kamalizad, Nozar Tabrizi, Nader Bagherzadeh, Akira Hatanaka	A Programmable DSP Architecture for Wireless Communication Systems.	ASAP	2005	DBLP DOI BibTeX RDF
1	Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere	Behavioral specification of control interface for signal processing applications.	ASAP	2005	DBLP DOI BibTeX RDF
1	Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis	Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays.	ASAP	2005	DBLP DOI BibTeX RDF
1	Thi Nguyen, Kaijian Shi	Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs.	ASAP	2005	DBLP DOI BibTeX RDF
1	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti	Exploring Design Space of VLIW Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
1		Message from the Conference Chairs.	ASAP	2005	DBLP DOI BibTeX RDF
1	Moboluwaji O. Sanu, Earl E. Swartzlander Jr.	Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields.	ASAP	2005	DBLP DOI BibTeX RDF
1		Title Page.	ASAP	2005	DBLP DOI BibTeX RDF
1	Tom R. Jacobs, José L. Núñez-Yáñez	A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor.	ASAP	2005	DBLP DOI BibTeX RDF
1	Michael J. Flynn	Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems.	ASAP	2005	DBLP DOI BibTeX RDF
1	Samarjit Chakraborty	Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media Processing.	ASAP	2005	DBLP DOI BibTeX RDF
1		Conference Organizers.	ASAP	2005	DBLP DOI BibTeX RDF
1	Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou	A Low-Power Processor Architecture Optimized forWireless Devices.	ASAP	2005	DBLP DOI BibTeX RDF	Pipeline depth, configurable pipeline, power-adaptive processors, Low power, asynchronous circuits
1	Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael J. Schulte, John Glossner	Instruction Set Extensions for Reed-Solomon Encoding and Decoding.	ASAP	2005	DBLP DOI BibTeX RDF
1	Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers	Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.	ASAP	2005	DBLP DOI BibTeX RDF
1	Björn Jäger, Jörg-Christian Niemann, Ulrich Rückert 0001	Analytical approach to massively parallel architectures for nanotechnologies.	ASAP	2005	DBLP DOI BibTeX RDF
1	Adrian Burian, Perttu Salmela, Jarmo Takala	Complex Fixed-Point Matrix Inversion Using Transport Triggered Architecture.	ASAP	2005	DBLP DOI BibTeX RDF
1	Kiyofumi Tanaka	Casablanca II: Implementation of a Real-Time RISC.	ASAP	2005	DBLP DOI BibTeX RDF
1	Karim Ben Chehida, Michel Auguin	A SW/Configware Codesign Methodology for Control Dominated Applications.	ASAP	2005	DBLP DOI BibTeX RDF
1	Jean-Luc Beuchat, Jean-Michel Muller	Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement.	ASAP	2005	DBLP DOI BibTeX RDF
1	Peter M. Kelly, T. Martin McGinnity, Liam P. Maguire	Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems.	ASAP	2005	DBLP DOI BibTeX RDF
1	Christian Plessl, Marco Platzner	Zippy - A coarse-grained reconfigurable array with support for hardware virtualization.	ASAP	2005	DBLP DOI BibTeX RDF
1	José L. Núñez-Yáñez, Vassilios A. Chouliaras	Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec.	ASAP	2005	DBLP DOI BibTeX RDF
1	Jérémie Detrey, Florent de Dinechin	Table-based polynomials for fast hardware function evaluation.	ASAP	2005	DBLP DOI BibTeX RDF
1	Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich	Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.	ASAP	2005	DBLP DOI BibTeX RDF
1	A. Murat Fiskiran, Ruby B. Lee	On-Chip Lookup Tables for Fast Symmetric-Key Encryption.	ASAP	2005	DBLP DOI BibTeX RDF
1	Ümit Y. Ogras, Jingcao Hu, Radu Marculescu	Communication-Centric SoC Design for Nanoscale Domain.	ASAP	2005	DBLP DOI BibTeX RDF
1	Hans Eberle, Arvinderpal Wander, Nils Gura, Sheueling Chang Shantz, Vipul Gupta	Architectural Extensions for Elliptic Curve Cryptography over GF(2m) on 8-bit Microprocessors.	ASAP	2005	DBLP DOI BibTeX RDF
1	Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, Antonio Rubio 0001	CONAN - A Design Exploration Framework for Reliable Nano-Electronics.	ASAP	2005	DBLP DOI BibTeX RDF
1	Byeong Kil Lee, Lizy Kurian John, Eugene John	Architectural Support for Accelerating Congestion Control Applications in Network Processors.	ASAP	2005	DBLP DOI BibTeX RDF
1		15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA	ASAP	2004	DBLP BibTeX RDF
1	Johann Großschädl, Sandeep S. Kumar, Christof Paar	Architectural Support for Arithmetic in Optimal Extension Fields.	ASAP	2004	DBLP DOI BibTeX RDF
1	Valeriu Beiu	A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments.	ASAP	2004	DBLP DOI BibTeX RDF
1	Gordon J. Brebner, Philip James-Roxby, Eric Keller, Chidamber Kulkarni	Hyper-Programmable Architectures for Adaptable Networked Systems.	ASAP	2004	DBLP DOI BibTeX RDF
1	François Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner	Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence Equations.	ASAP	2004	DBLP DOI BibTeX RDF	multi-rate systems, systems of recurrence equations, data flow systems, 3G mobile telephony, scheduling, FPGA, prototyping, WCDMA
1	Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala	Stride Permutation Networks for Array Processors.	ASAP	2004	DBLP DOI BibTeX RDF
1	Antoine Fraboulet, Tanguy Risset	Efficient On-Chip Communications for Data-Flow IPs.	ASAP	2004	DBLP DOI BibTeX RDF	SoC simulation, system on chip, High level synthesis, interface generation
1	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing.	ASAP	2004	DBLP DOI BibTeX RDF
1	Anup Hosangadi, Farzan Fallah, Ryan Kastner	Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis.	ASAP	2004	DBLP DOI BibTeX RDF
1	Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis	A Low-Power Carry Skip Adder with Fast Saturation.	ASAP	2004	DBLP DOI BibTeX RDF
1	Oliver Amft, Michael Lauffer, Stijn Ossevoort, Fabrizio Macaluso, Paul Lukowicz, Gerhard Tröster	Design of the QBIC Wearable Computing Platform.	ASAP	2004	DBLP DOI BibTeX RDF
1	Tom Van Court, Martin C. Herbordt	Families of FPGA-Based Algorithms for Approximate String Matching.	ASAP	2004	DBLP DOI BibTeX RDF
1	Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott A. Mahlke	Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators.	ASAP	2004	DBLP DOI BibTeX RDF
1	Fabien Castanier, Alberto Ferrante, Vincenzo Piuri	A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems.	ASAP	2004	DBLP DOI BibTeX RDF
1	Rama Sangireddy	Register Organization for Enhanced On-Chip Parallelism.	ASAP	2004	DBLP DOI BibTeX RDF

Publications at "ASAP"( http://dblp.L3S.de/Venues/ASAP )